CN102054747B - Metal layer treatment method - Google Patents
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- CN102054747B CN102054747B CN200910198112A CN200910198112A CN102054747B CN 102054747 B CN102054747 B CN 102054747B CN 200910198112 A CN200910198112 A CN 200910198112A CN 200910198112 A CN200910198112 A CN 200910198112A CN 102054747 B CN102054747 B CN 102054747B
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Abstract
The invention provides a metal layer treatment method, comprising the following steps of: providing a base, wherein the base comprises a substrate and a medium layer which is formed on the surface of the substrate; then forming a contact hole which is disposed within the medium layer and is used for exposing the substrate; forming a metal layer on the surface of the medium layer and within the contact hole, respectively; and then annealing the metal layers; controlling the time interval between the step of annealing and the step of chemically mechanical polishing; subjecting the metal layers which are annealed into chemically mechanical polishing until the medium layer is exposed. The metal layer treatment method provided by the invention has the advantage that the reductions of yield and reliability of the chip which are caused by the large gap disposed within the metal layer in case that the micropores which are disposed within the metal layer are aggregated while applying a relatively large tensional stress on the metal layer can be prevented.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of metal level processing method.
Background technology
In very lagre scale integrated circuit (VLSIC) technology, the silicon dioxide that thermal stability, moisture resistance are arranged is the main insulating material that metal interconnected circuit chien shih is used always, and metallic aluminium then is the main material of circuit interconnection lead in the chip.Yet; With respect to the microminiaturization of element and the increase of integrated level, conductor line number constantly increases in the circuit, makes that resistance (R) and the electric capacity (C) in the conductor line framework produces ghost effect; Cause serious transmission delay (RC Delay); In 130 nanometers and more advanced technology, become the limited principal element of signal transmission speed in the circuit, therefore, prior art adopts the dielectric material of new low electrical resistant material copper and low-k with the reduction transmission delay in semiconductor technology.
But because metallic copper etching difficulty; The interconnection structure of the existing copper that adopts forms groove usually earlier; In groove, fill metallic copper then; Adopt CMP process to remove unnecessary metal copper layer at last, in publication number is the Chinese patent file of CN1866495A, can find more formation scheme about the interconnection structure of existing copper.
Simply introduce the forming process of interconnection structure below in conjunction with accompanying drawing.Fig. 1 to Fig. 4 is the sketch map of the forming process of interconnection structure in the prior art.
As shown in Figure 1, substrate 100 is provided; Form metal level 110 on said substrate 100 surfaces; Certain thickness first dielectric layer 120 of deposition on metal level 110, and utilize first dielectric layer 120 that photoetching, lithographic technique remove corresponding contact hole place until exposing metal level 110 surfaces, to form contact hole opening 121.
As shown in Figure 2, (Physical Vapor Deposition, PVD) method is on first dielectric layer, the 120 surface deposition barrier layers 122 with contact hole opening 121 to utilize physical vapour deposition (PVD).
As shown in Figure 3,122 surface depositions are used for the metal level 123 of filling contact hole opening 121 on the barrier layer to utilize electroplating technology.
As shown in Figure 4, adopt CMP process to remove part metals layer 123, barrier layer 122 until exposing first dielectric layer 120.
In the forming process of existing interconnection structure, metal level forms and annealing is accomplished in same electroplating device, because the metal level after the annealing has very big stress; Because the otherness of electroplating device production capacity and chemical-mechanical polisher production capacity, usually after electroplating formation metal level 123, can wait for that the long time just can carry out CMP process; Along with time lengthening; Metal level after the annealing is under the effect of stress, and big hole shape defective can moved and be gathered into to the microdefect in the metal level 123, thereby cause the interconnection structure electric property low; Reliability reduces, and can make entire device scrap when serious.
Summary of the invention
The technical problem that the present invention solves is that the microdefect in the metal level stand-by period long back metal level after electroplating technology is accomplished is assembled interstitial problem in metal level under stress.
For addressing the above problem, the present invention provides a kind of metal level processing method, comprising: substrate is provided, and said substrate comprises substrate and the dielectric layer that is formed on substrate surface; Be formed with the contact hole that exposes substrate in the said dielectric layer; Be formed with metal level in said dielectric layer surface and the said contact hole; To said metal level annealing; In the time interval between control annealing and the chemico-mechanical polishing, the metal level after the said annealing is carried out chemico-mechanical polishing, until exposing dielectric layer.
Optional, the time interval between annealing and the chemico-mechanical polishing was less than 5 hours.
Optional; Technological parameter to the annealing of said metal level is: annealing temperature be 100 degree to 400 degree, protective gas is the mist of nitrogen and hydrogen, wherein the volume ratio of nitrogen and hydrogen is 100: 3.381; The flow of the mist of nitrogen and hydrogen is 50SCCM to 200SCCM; Annealing time is 30 seconds to 2 hours, and the annealing chilling temperature is 40 degree, and annealing temperature to cooling time of the chilling temperature of annealing be 10 seconds to 200 seconds.
Optional, metal level annealing can annealing device independently or with the integrated annealing device of the equipment of chemico-mechanical polishing in accomplish.
Optional, said substrate is substrate, the patterning of multi layer substrate, classification substrate, silicon-on-insulator substrate, epitaxial silicon substrate, section processes or the substrate that is not patterned.
Optional, said dielectric layer is before-metal medium layer or interlayer dielectric layer.
Optional, the material of said dielectric layer is SiO
2The SiO that perhaps mixes
2
Optional, said metal layer material is a copper.
Optional, the formation method of said metal level is an electroplating technology.
Optional, the concrete parameter of said electroplating technology is: electroplate liquid is selected CuSO for use
4Solution, Cu
2+Concentration is 30g/L to 50g/L, and adding concentration is the inorganic additive of the chloride ion-containing of 40mg/L to 60mg/L in this solution, and the electric current of plating is 4.5 amperes to 45 amperes.
Optional; The concrete parameter of the metal level after the said annealing being carried out chemico-mechanical polishing is: select for use silica as polishing particles; The pH value of polishing fluid is 10 to 11.5, and the flow of polishing fluid is 200 milliliters of per minute to 400 milliliter per minutes, and the rotating speed of grinding pad is 83 rpms to 103 rpms in the glossing; The rotating speed of grinding head is 77 rpms to 97 rpms, and the pressure of glossing is 5500 handkerchief to 6500 handkerchiefs.
Compared with prior art; The present invention has the following advantages: the present invention is through the time interval between control annealing and the chemico-mechanical polishing; Make the substrate that is formed with said metal level after the annealing can directly get into chemical-mechanical polishing step, and do not need long wait; The microdefect building-up effect of having avoided metal level under stress, to produce, thus the space in metal level, formed, cause interconnection structure electric property and reliability low.
Description of drawings
Fig. 1 to Fig. 4 is the sketch map of the forming process of interconnection structure in the prior art;
Fig. 5 is the schematic flow sheet of an embodiment of metal level processing method of the present invention;
Fig. 6 to Fig. 9 is the process sketch map of an embodiment of metal level processing method of the present invention.
Embodiment
Can know that by background technology in the forming process of existing interconnection structure, metal level forms and annealing is accomplished in same electroplating device; Because the metal level after the annealing has very big stress, because the otherness of electroplating device production capacity and chemical-mechanical polisher production capacity, usually after electroplating the formation metal level; Can the long time of wait just can carry out CMP process, along with time lengthening, the metal level after the annealing is under the effect of stress; Big hole shape defective can moved and be gathered into to microdefect in the metal level; Thereby cause the interconnection structure electric property low, reliability reduces, and can make entire device scrap when serious.
For this reason, inventor of the present invention provides a kind of metal level processing method of optimization, comprises the steps: to provide substrate, and said substrate comprises substrate and the dielectric layer that is formed on substrate surface; Be formed with the contact hole that exposes substrate in the said dielectric layer; Be formed with metal level in said dielectric layer surface and the said contact hole; To said metal level annealing; In the time interval between control annealing and the chemico-mechanical polishing, the metal level after the said annealing is carried out chemico-mechanical polishing, until exposing dielectric layer.
Optional, the time interval between annealing and the chemico-mechanical polishing was less than 5 hours.
Optional; Technological parameter to the annealing of said metal level is: annealing temperature be 100 degree to 400 degree, protective gas is the mist of nitrogen and hydrogen, wherein the volume ratio of nitrogen and hydrogen is 100: 3.381; The flow of the mist of nitrogen and hydrogen is 50SCCM to 200SCCM; Annealing time is 30 seconds to 2 hours, and the annealing chilling temperature is 40 degree, and annealing temperature to cooling time of the chilling temperature of annealing be 10 seconds to 200 seconds.
Optional, metal level annealing can annealing device independently or with the integrated annealing device of the equipment of chemico-mechanical polishing in accomplish.
Optional, said substrate is substrate, the patterning of multi layer substrate, classification substrate, silicon-on-insulator substrate, epitaxial silicon substrate, section processes or the substrate that is not patterned.
Optional, said dielectric layer is before-metal medium layer or interlayer dielectric layer.
Optional, the material of said dielectric layer is SiO
2The SiO that perhaps mixes
2
Optional, said metal layer material is a copper.
Optional, the formation method of said metal level is an electroplating technology.
Optional, the concrete parameter of said electroplating technology is: electroplate liquid is selected CuSO for use
4Solution, Cu
2+Concentration is 30g/L to 50g/L, and adding concentration is the inorganic additive of the chloride ion-containing of 40mg/L to 60mg/L in this solution, and the electric current of plating is 4.5 amperes to 45 amperes.
Optional; The concrete parameter of the metal level after the said annealing being carried out chemico-mechanical polishing is: select for use silica as polishing particles; The pH value of polishing fluid is 10 to 11.5, and the flow of polishing fluid is 200 milliliters of per minute to 400 milliliter per minutes, and the rotating speed of grinding pad is 83 rpms to 103 rpms in the glossing; The rotating speed of grinding head is 77 rpms to 97 rpms, and the pressure of glossing is 5500 handkerchief to 6500 handkerchiefs.
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 5 is the schematic flow sheet of an embodiment of metal level processing method of the present invention, and Fig. 6 to Fig. 9 is the process sketch map of an embodiment of metal level processing method of the present invention.Below in conjunction with Fig. 5 to Fig. 9 metal level processing method of the present invention is described.
Step S101 provides substrate, and said substrate comprises substrate and the dielectric layer that is formed on substrate surface; Be formed with the contact hole that exposes substrate in the said dielectric layer; Be formed with metal level in said dielectric layer surface and the said contact hole.
With reference to figure 6, said substrate 200 comprises substrate 210 and the dielectric layer 220 that is formed on substrate 210 surfaces.
Said substrate 210 can be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes or the substrate that is not patterned.
Said dielectric layer 220 is used to isolate metal level and the semiconductor unit that is formed in the dielectric layer 220; Concrete said dielectric layer 220 can be before-metal medium layer (Pre-Metal Dielectric; PMD), also can be interlayer dielectric layer (Inter-Metal Dielectric, ILD); What need particularly point out is that said dielectric layer 220 can also be that single coating also can be the multiple-level stack structure.
Before-metal medium layer is to be deposited on the substrate with MOS device; Utilize depositing operation to form; In before-metal medium layer, can form groove at subsequent technique, form connecting hole with metal filled groove, said connecting hole is used for connecting the electrode of MOS device and the plain conductor of upper layer interconnects layer.
Interlayer dielectric layer is the dielectric layer of postchannel process between metal interconnecting layer, can in subsequent technique, form groove in the interlayer dielectric layer, forms connecting hole with metal filled groove, and said connecting hole is used for connecting the lead of adjacent metal interconnects layer.
The material of said dielectric layer 220 is selected from SiO usually
2The SiO that perhaps mixes
2USG (Undoped Silicon Glass for example; The silex glass that does not have doping), BPSG (BorophosphosilicateGlass; The silex glass of boron phosphorus doped), BSG (Borosilicate Glass, the silex glass of doped with boron), PSG (Phosphosilitcate Glass, the silex glass of Doping Phosphorus) etc.
Said dielectric layer 220 generally selects for use the dielectric material of low-k, the material of said dielectric layer 220 specifically to be selected from the carborundum (BLOK) that silica (Black Diamond) that fluorine silex glass (FSG), carbon mix and nitrogen mix at 130 nanometers and following process node.
The formation technology of said dielectric layer 220 can be any conventional vacuum coating technology; For example atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like are formed on substrate 210 surfaces, here do not do and give unnecessary details.
With reference to figure 7, in said dielectric layer 220, form the contact hole 221 that exposes substrate 210.
The formation step of said contact hole 221 comprises: at said dielectric layer 220 surperficial spin coating photoresists; Then through exposure with on the mask with said contact hole 221 corresponding figure transfer to photoresist; Utilize developer solution that the photoresist of corresponding site is removed then, to form the photoresist figure; With said photoresist figure is mask, and the said dielectric layer 220 of etching is until forming said contact hole 221.
The technology of the said dielectric layer 220 of etching can be known chemical reagent etching technics or plasma etch process, in the present embodiment, is that example is done exemplary illustrated with the plasma etching.
The concrete technological parameter of said plasma etch process is: the etching apparatus chamber pressure is 30 millitorr to 60 millitorrs, and frequency is that the radio-frequency power of 13.6M is 500 watts to 1000 watts, and frequency is that the radio-frequency power of 2M is 200 watts to 400 watts, CF
4Flow is per minute 80 standard cubic centimeters to per minute 120 standard cubic centimeters, CHF
3Flow is per minute 50 standard cubic centimeters to per minute 80 standard cubic centimeters, and with above-mentioned etching technics parameter, the said dielectric layer 220 of etching is until forming said contact hole 221.
With reference to figure 8, in said dielectric layer 210 surfaces and said contact hole 221, form metal level 230.
The material of said metal level 230 can be in aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, the copper one or several; What need particularly point out is; Because metallic copper has the ability of high-melting-point, low-resistance coefficient and high anti-electron transfer, said metal level 230 materials are more preferably used copper, and what still need special instruction is; The said metal level 230 of selecting for use other conductive materials to form still can be worked; Just transmission delay is bigger, specially explains at this, should too not limit protection scope of the present invention.
Present embodiment is that metallic copper is an example with said metal level 230, does exemplary illustrated.
In the present embodiment, selecting the metal level 230 formation technologies of metallic copper for use is electroplating technology.
12. the concrete parameter of said electroplating technology is: the concrete parameter of said electroplating technology is: electroplate liquid is selected CuSO for use
4Solution, Cu
2+Concentration is 30g/L to 50g/L, and adding concentration is the inorganic additive of the chloride ion-containing of 40mg/L to 60mg/L in this solution, and the electric current of plating is 4.5 amperes to 45 amperes.
What need particularly point out is; In other embodiments, in order to improve the electric property of said metal level 230 filling contact holes 221, can be before forming metal level 230 steps; Form one deck barrier layer at contact hole 221 sidewalls and bottom earlier, form the inculating crystal layer of copper then at said barrier layer surface.
Step S102 is to said metal level 230 annealing.
In the existing process steps, the metal grain of the metal level 230 after electroplating technology is accomplished is smaller, along with time lengthening; The metal grain of metal level 230 contacts with each other grows up; In metal level 230, form the space, cause the interconnection structure electric property low, can make entire device scrap when serious.
For this reason, inventor of the present invention takes said metal level 230 annealing through a large amount of experiments, contacts with each other with the metal grain of avoiding occurring metal level 230 and grows up formation cavitation metal level 230 in.
What need particularly point out is; The technological parameter of said annealing process is particularly important; If the parameter of annealing process does not meet technological requirement, inventor of the present invention finds, the metal level 230 after the annealing still can metal grain contacts with each other grows up; Even can occur, the metallic particles annealing growth phenomenon of the metal level 230 after the annealing occurs.
For this reason, inventor of the present invention adopts the technological parameter of annealing process to comprise through a large amount of creativeness experiments: annealing temperature is that 100 degree are to 400 degree; Protective gas is the mist of nitrogen and hydrogen; Wherein the volume ratio of nitrogen and hydrogen is 100: 3.381, and the flow of the mist of nitrogen and hydrogen is 50SCCM to 200SCCM, and annealing time is 30 seconds to 2 hours; The annealing chilling temperature is 40 degree; And annealing temperature to the cooling time of annealing chilling temperature be 10 seconds to 200 seconds, adopts above-mentioned annealing conditions, the metallic particles phenomenon of growing can not appear in the metal level 230 after the annealing.
The annealing of said metal level can for example be carried out in tubular type annealing furnace or the quick anneal oven at annealing device; For metallic particles annealing growth phenomenon appears in avoiding further, metal level annealing can with the integrated annealing device of the equipment of chemico-mechanical polishing in accomplish.
With reference to figure 9, S103 is said like step, in the time interval between control annealing and the chemico-mechanical polishing, the metal level after the said annealing 230 is carried out chemico-mechanical polishing, until exposing dielectric layer 210.
Quality for the metal level 230 that improves formation; Metal level after the said annealing and said metal level 230 carried out interval between the technology of chemico-mechanical polishing less than 5 hours, the time interval between said control annealing and the chemico-mechanical polishing can realize through optimizing parameter and annealing and CMP process parameter.
Said CMP process is selected the glossing of selective removal copper for use; The concrete parameter of said CMP process is: select for use silica as polishing particles; The pH value of polishing fluid is 10 to 11.5; The flow of polishing fluid is 200 milliliters of per minute to 400 milliliter per minutes, and the rotating speed of grinding pad is 83 rpms to 103 rpms in the glossing, and the rotating speed of grinding head is 77 rpms to 97 rpms; The pressure of glossing is 5500 handkerchief to 6500 handkerchiefs, until exposing dielectric layer 210.
The present invention anneals to said metal level 230 through the annealing process of adopt optimizing, and has avoided the crystal grain of metal level 230 to contact with each other and has grown up, and metal level 230 in, forms the space, causes the low phenomenon appearance of interconnection structure electric property.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. a metal level processing method is characterized in that, comprising:
Substrate is provided, and said substrate comprises substrate and the dielectric layer that is formed on substrate surface; Be formed with the contact hole that exposes substrate in the said dielectric layer; Be formed with metal level in said dielectric layer surface and the said contact hole;
To said metal level annealing; Technological parameter to the annealing of said metal level is: annealing temperature be 100 degree to 400 degree, protective gas is the mist of nitrogen and hydrogen, wherein the volume ratio of nitrogen and hydrogen is 100:3.381; The flow of the mist of nitrogen and hydrogen is 50SCCM to 200SCCM; Annealing time is 30 seconds to 2 hours, and the annealing chilling temperature is 40 degree, and annealing temperature to cooling time of the chilling temperature of annealing be 10 seconds to 200 seconds;
The time interval between control annealing and the chemico-mechanical polishing was carried out chemico-mechanical polishing to the metal level after the said annealing, until exposing dielectric layer less than 5 hours.
2. metal level processing method as claimed in claim 1 is characterized in that, metal level annealing can annealing device independently or with the integrated annealing device of the equipment of chemico-mechanical polishing in accomplish.
3. metal level processing method as claimed in claim 1 is characterized in that, said substrate is substrate, the patterning of multi layer substrate, classification substrate, silicon-on-insulator substrate, epitaxial silicon substrate, section processes or the substrate that is not patterned.
4. metal level processing method as claimed in claim 1 is characterized in that, said dielectric layer is before-metal medium layer or interlayer dielectric layer.
5. metal level processing method as claimed in claim 1 is characterized in that, the material of said dielectric layer is SiO
2The SiO that perhaps mixes
2
6. metal level processing method as claimed in claim 1 is characterized in that, said metal layer material is a copper.
7. metal level processing method as claimed in claim 1 is characterized in that, the formation method of said metal level is an electroplating technology.
8. metal level processing method as claimed in claim 7 is characterized in that, the concrete parameter of said electroplating technology is: electroplate liquid is selected CuSO for use
4Solution, Cu
2+Concentration is 30g/L to 50g/L, and adding concentration is the inorganic additive of the chloride ion-containing of 40mg/L to 60mg/L in this solution, and the electric current of plating is 4.5 amperes to 45 amperes.
9. metal level processing method as claimed in claim 1; It is characterized in that; The concrete parameter of the metal level after the said annealing being carried out chemico-mechanical polishing is: select for use silica as polishing particles; The pH value of polishing fluid is 10 to 11.5, and the flow of polishing fluid is 200 milliliters of per minute to 400 milliliter per minutes, and the rotating speed of grinding pad is 83 rpms to 103 rpms in the glossing; The rotating speed of grinding head is 77 rpms to 97 rpms, and the pressure of glossing is 5500 handkerchief to 6500 handkerchiefs.
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| CN200910198112A CN102054747B (en) | 2009-11-02 | 2009-11-02 | Metal layer treatment method |
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| CN103426751B (en) * | 2012-05-14 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN104139331A (en) * | 2013-05-08 | 2014-11-12 | 盛美半导体设备（上海）有限公司 | Chip flattening method |
| CN104241097A (en) * | 2014-09-02 | 2014-12-24 | 上海华力微电子有限公司 | Method for avoiding residual defect of integrated etching of semiconductor device |
| CN105448654A (en) * | 2014-09-02 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor structure |
| CN110267189A (en) * | 2019-07-16 | 2019-09-20 | 大族激光科技产业集团股份有限公司 | A kind of processing method being bonded functional die surface |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5625231A (en) * | 1995-03-10 | 1997-04-29 | Advanced Micro Devices, Inc. | Low cost solution to high aspect ratio contact/via adhesion layer application for deep sub-half micrometer back-end-of line technology |
| CN101127304A (en) * | 2006-08-14 | 2008-02-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device making method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5625231A (en) * | 1995-03-10 | 1997-04-29 | Advanced Micro Devices, Inc. | Low cost solution to high aspect ratio contact/via adhesion layer application for deep sub-half micrometer back-end-of line technology |
| CN101127304A (en) * | 2006-08-14 | 2008-02-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device making method |
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