CN102054750A - Method for forming interconnecting structure - Google Patents
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- CN102054750A CN102054750A CN2009101981155A CN200910198115A CN102054750A CN 102054750 A CN102054750 A CN 102054750A CN 2009101981155 A CN2009101981155 A CN 2009101981155A CN 200910198115 A CN200910198115 A CN 200910198115A CN 102054750 A CN102054750 A CN 102054750A
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Abstract
The invention discloses a method for forming an interconnecting structure. The method comprises the following steps of: providing a substrate; forming a dielectric layer on the surface of the substrate; forming contact holes which expose the substrate in the dielectric layer; forming barrier layers on side walls and the bottoms of the contact holes and the surface of the dielectric layer; forming metal layers which fill the contact holes on the surfaces of the barrier layers; performing annealing and cooling processes on the metal layers for more than three times; and performing chemically mechanical polishing on the metal layers until the dielectric layer is exposed. By the method, large stress formed in the metal layers can be effectively avoided, so that a pore-shaped defect in the formed metal layers caused by excessive stress can be avoided, and the yield and reliability of a chip can be improved. Besides, by the method, a warpage effect of the substrate on which the metal layers are formed generated after the annealing process can be avoided.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly the formation method of interconnection structure.
Background technology
In very lagre scale integrated circuit (VLSIC) technology, the silicon dioxide that thermal stability, moisture resistance are arranged is the main insulating material that metal interconnected circuit chien shih is used always, and metallic aluminium then is the main material of circuit interconnection lead in the chip.Yet, with respect to the microminiaturization of element and the increase of integrated level, conductor line number constantly increases in the circuit, make resistance (R) and electric capacity (C) in the conductor line framework produce ghost effect, cause serious transmission delay (RC Delay), become the limited principal element of signal transmission speed in the circuit in 130 nanometers and more advanced technology, therefore, prior art adopts the dielectric material of new low electrical resistant material copper and low-k with the reduction transmission delay in semiconductor technology.
But because metallic copper etching difficulty, the interconnection structure of the existing copper that adopts forms groove usually earlier, in groove, fill metallic copper then, adopt CMP (Chemical Mechanical Polishing) process to remove unnecessary metal copper layer at last, in publication number is the Chinese patent file of CN1866495A, can find more formation scheme about the interconnection structure of existing copper.
Simply introduce the forming process of interconnection structure below in conjunction with accompanying drawing.Fig. 1 to Fig. 4 is the schematic diagram of the forming process of interconnection structure in the prior art.
As shown in Figure 1, provide substrate 100; Form metal level 110 on described substrate 100 surfaces; Certain thickness first dielectric layer 120 of deposition on metal level 110, and utilize photoetching, lithographic technique to remove first dielectric layer 120 at corresponding contact hole place until exposing metal level 110 surfaces, to form contact hole opening 121.
As shown in Figure 2, (Physical Vapor Deposition, PVD) method is on first dielectric layer, the 120 surface deposition barrier layers 122 with contact hole opening 121 to utilize physical vapour deposition (PVD).
As shown in Figure 3,122 surface depositions are used for the metal level 123 of filling contact hole opening 121 on the barrier layer to utilize electroplating technology.
As shown in Figure 4, adopt CMP (Chemical Mechanical Polishing) process to remove part metals layer 123, barrier layer 122 until exposing first dielectric layer 120.
In the forming process of existing interconnection structure, metal level forms and annealing is finished in same electroplating device, because the metal level after the annealing has very big stress, because the otherness of electroplating device production capacity and chemical-mechanical polisher production capacity, usually after electroplating formation metal level 123, can the long time of wait just can carry out CMP (Chemical Mechanical Polishing) process, along with time lengthening, metal level after the annealing is under the effect of stress, big hole shape defective can be moved and be gathered into to microdefect in the metal level 123, thereby cause the interconnection structure electric property low, reliability reduces, and can make entire device scrap when serious.
Summary of the invention
The technical problem that the present invention solves is to avoid the microdefect in the metal level can move and be gathered into big hole shape defective.
For addressing the above problem, the invention provides a kind of formation method of interconnection structure, comprising: substrate is provided; Form dielectric layer at described substrate surface; In described dielectric layer, form the contact hole that exposes substrate; Form the barrier layer on described contact hole sidewall, bottom and dielectric layer surface; Form the metal level of filling contact hole at described barrier layer surface; Described metal level is carried out annealing, process for cooling more than 3 times; Described metal level is carried out chemico-mechanical polishing until exposing dielectric layer.
Optionally, described metal level is carried out the concrete number of times of annealing, process for cooling more than 3 times less than 20 times.
Optionally, described metal level carried out each concrete technology is in the annealing, process for cooling more than 3 times: to described metal level annealing, annealing temperature is that 100 degree are to 400 degree, annealing time is 10 seconds to 50 seconds, after annealing finishes described metal level is cooled to room temperature, be 15 seconds to 60 seconds cooling time.
Optionally, the technology of the contact hole of described formation exposure substrate is plasma etch process.
Optionally, the material on described barrier layer is tantalum, tantalum nitride, titanium or titanium nitride.
Optionally, described barrier layer is single layer structure or multilayer overlaying structure.
Optionally, before the metal level step of described barrier layer surface formation filling contact hole, also comprise: the inculating crystal layer step that forms copper at described barrier layer surface.
Optionally, the material of described metal level is a copper.
Optionally, the technology of the metal level of described formation filling contact hole is electroplating technology.
Optionally, the concrete parameter of described electroplating technology is: electroplate liquid is selected CuSO for use
4Solution, Cu
2+Concentration is 30g/L to 50g/L, and adding concentration is the inorganic additive of the chloride ion-containing of 40mg/L to 60mg/L in this solution, and the electric current of plating is 4.5 amperes to 45 amperes.
Compared with prior art, the present invention can avoid forming bigger stress effectively in metal level, thereby produces hole shape defective owing to stress is excessive in the metal level that can avoid forming, has improved the yield and the reliability of chip.In addition, the present invention can also avoid being formed with metal level substrate after annealing process is finished and the warpage effect that produces.
Description of drawings
Fig. 1 to Fig. 4 is the existing process schematic diagram that forms interconnection structure;
Fig. 5 is the schematic flow sheet of an embodiment of interconnection structure formation method of the present invention;
Fig. 6 to Figure 11 is the process schematic diagram of an embodiment of the manufacture method of interconnection structure formation method of the present invention.
Embodiment
By background technology as can be known, in the forming process of existing interconnection structure, metal level forms and annealing is finished in same electroplating device, because the metal level after the annealing has very big stress, because the otherness of electroplating device production capacity and chemical-mechanical polisher production capacity, usually after electroplating the formation metal level, can the long time of wait just can carry out CMP (Chemical Mechanical Polishing) process, along with time lengthening, metal level after the annealing is under the effect of stress, big hole shape defective can be moved and be gathered into to microdefect in the metal level, thereby cause the interconnection structure electric property low, and reliability reduces, can make entire device scrap when serious, and the stress that existing annealing causes accumulation also can make and produce the warpage effect by the substrate-like camber that is formed with metal level, can cause device to scrap equally when serious.
For this reason, the present inventor proposes a kind of formation method of interconnection structure, comprising: substrate is provided; Form dielectric layer at described substrate surface; In described dielectric layer, form the contact hole that exposes substrate; Form the barrier layer on described contact hole sidewall, bottom and dielectric layer surface; Form the metal level of filling contact hole at described barrier layer surface; Described metal level is carried out annealing, process for cooling more than 3 times; Described metal level is carried out chemico-mechanical polishing until exposing dielectric layer.
Optionally, described metal level is carried out the concrete number of times of annealing, process for cooling more than 3 times less than 20 times.
Optionally, described metal level carried out each concrete technology is in the annealing, process for cooling more than 3 times: to described metal level annealing, annealing temperature is that 100 degree are to 400 degree, annealing time is 10 seconds to 50 seconds, after annealing finishes described metal level is cooled to room temperature, be 15 seconds to 60 seconds cooling time.
Optionally, the technology of the contact hole of described formation exposure substrate is plasma etch process.
Optionally, the material on described barrier layer is tantalum, tantalum nitride, titanium or titanium nitride.
Optionally, described barrier layer is single layer structure or multilayer overlaying structure.
Optionally, before the metal level step of described barrier layer surface formation filling contact hole, also comprise: the inculating crystal layer step that forms copper at described barrier layer surface.
Optionally, the material of described metal level is a copper.
Optionally, the technology of the metal level of described formation filling contact hole is electroplating technology.
Optionally, the concrete parameter of described electroplating technology is: electroplate liquid is selected CuSO for use
4Solution, Cu
2+Concentration is 30g/L to 50g/L, and adding concentration is the inorganic additive of the chloride ion-containing of 40mg/L to 60mg/L in this solution, and the electric current of plating is 4.5 amperes to 45 amperes.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 5 is the schematic flow sheet of an embodiment of interconnection structure formation method of the present invention, and Fig. 6 to Figure 11 is the process schematic diagram of an embodiment of the manufacture method of interconnection structure formation method of the present invention.Below in conjunction with Fig. 5 to Figure 11 interconnection structure formation method of the present invention is described.
Step S101 provides substrate.
With reference to figure 6, described substrate 200 can be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes or the substrate that is not patterned.
Step S102 forms dielectric layer on described substrate 200 surfaces.
With reference to figure 7, the thickness of described dielectric layer 210 is 20 nanometer to 5000 nanometers, and described dielectric layer 210 is used to isolate metal level and the semiconductor unit that is formed in the dielectric layer 210.Concrete described dielectric layer 210 can be before-metal medium layer (Pre-Metal Dielectric, PMD), also can be interlayer dielectric layer (Inter-Metal Dielectric, ILD), it needs to be noted that described dielectric layer 210 can also be that single coating also can be the multiple-level stack structure.
Before-metal medium layer is to be deposited on the substrate with MOS device, utilize depositing operation to form, can form groove at subsequent technique in before-metal medium layer, form connecting hole with metal filled groove, described connecting hole is used for connecting the electrode of MOS device and the plain conductor of upper layer interconnects layer.
Interlayer dielectric layer is the dielectric layer of postchannel process between metal interconnecting layer, can form groove in the interlayer dielectric layer in subsequent technique, forms connecting hole with metal filled groove, and described connecting hole is used for connecting the lead of adjacent metal interconnects layer.
The material of described dielectric layer 210 is selected from SiO usually
2The perhaps SiO of Can Zaing
2USG (Undoped Silicon Glass for example, the silex glass that does not have doping), BPSG (Borophosphosilicate Glass, the silex glass of boron phosphorus doped), BSG (Borosilicate Glass, the silex glass of doped with boron), PSG (Phosphosilitcate Glass, the silex glass of Doping Phosphorus) etc.
Described dielectric layer 210 generally selects for use the dielectric material of low-k, the material of described dielectric layer 210 specifically to be selected from the carborundum (BLOK) that silica (Black Diamond) that fluorine silex glass (FSG), carbon mix and nitrogen mix at 130 nanometers and following process node.
The formation technology of described dielectric layer 210 can be any conventional vacuum coating technology, for example atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like are not here done and are given unnecessary details.
Step S103 forms the contact hole that exposes substrate 200 in described dielectric layer 210.
With reference to figure 8, the technology of described formation contact hole 211 can be existing graphical technology and etching technics.
Concrete steps comprise: forming the photoresist figure corresponding with contact hole 211 on described dielectric layer 210 surfaces, is mask with described photoresist figure, and the described dielectric layer 210 of etching is until exposing substrate 200, formation contact hole 211.
Described formation photoresist graphics art is specially: at described dielectric layer 210 surperficial spin coating photoresists, then by exposure with on the mask with the corresponding figure transfer of contact hole to photoresist, utilize developer solution that the photoresist of corresponding site is removed then, to form the photoresist figure.
Described etching technics can be any conventional etching technics, for example chemical etching or plasma etch process.In the present embodiment, the using plasma etching technics adopts CF
4, CHF
3, CH
2F
2, CH
3F, C
4F
8Perhaps C
5F
8In one or several as described first dielectric layer 220 of reacting gas etching.
In the present embodiment, with the plasma etch process is example, do exemplary illustrated, concrete etching technics parameter can for: select the plasma-type etching apparatus for use, the etching apparatus chamber pressure is 10 millitorr to 50 millitorrs, the top radio-frequency power is 200 watts to 500 watts, and the bottom radio-frequency power is 150 watts to 300 watts, C
4F
8Flow is that per minute 10 standard cubic centimeters (10SCCM) are to per minute 50 standard cubic centimeters, the CO flow is that per minute 100 standard cubic centimeters are to per minute 200 standard cubic centimeters, the Ar flow is that per minute 300 standard cubic centimeters are to per minute 600 standard cubic centimeters, O
2Flow is that per minute 10 standard cubic centimeters are to per minute 50 standard cubic centimeters.
Step S104 forms the barrier layer on described contact hole 211 sidewalls, bottom and dielectric layer 210 surfaces.
With reference to figure 9, described barrier layer 220 is single layer structure or multilayer overlaying structure, described barrier layer 220 thickness are 20 nanometer to 200 nanometers, described barrier layer 220 is used to stop that the atom of the metal level of follow-up formation spreads in dielectric layer 210, and for providing reasonable adhesive attraction between follow-up metal level that in contact hole 211, forms and dielectric layer 210 sidewalls, also be used to stop the conductive materials of follow-up formation and the silicon atom of dielectric layer 210 to react, reduced the resistance of contact hole 211.
The material on described barrier layer 220 can be selected from tantalum, tantalum nitride, titanium or titanium nitride.
The formation technology on described barrier layer 220 can be physical vapour deposition (PVD), in the present embodiment, described barrier layer 220 is chosen as tantalum and tantalum nitride overlaying structure, described formation technology can be for adopting metal-organic chemical vapor deposition equipment (Metal Organic Chemical Vapor Deposition, MOCVD) technology forms tantalum nitride, adopts physical gas-phase deposition to form one deck tantalum on the tantalum nitride surface then.
Step S105 is at the metal level of described barrier layer 220 surface formation filling contact holes 211.
With reference to Figure 10, described metal level 240 materials are one or several in aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, the copper, and described metal level 240 thickness are 2000 dust to 3000 dusts.
It needs to be noted; because metallic copper has the ability of high-melting-point, low-resistance coefficient and high anti-electron transfer; described metal level 240 materials are more preferably used copper; but of particular note; the metal level 240 of selecting for use other conductive materials to form is higher than in 130 nanometer technologies at process node still can work; just transmission delay is bigger, specially illustrates at this, should too not limit protection scope of the present invention.
Also it needs to be noted; when selecting for use metallic copper to be the material of described metal level 240; in order to improve the formation quality of described metal level 240, also can before forming metal level 240, form the inculating crystal layer (not shown) of copper usually on 220 surfaces, described barrier layer.
In the present embodiment, metal level 240 formation technologies are electroplating technology.
The concrete parameter of described electroplating technology is: the concrete parameter of described electroplating technology is: electroplate liquid is selected CuSO for use
4Solution, Cu
2+Concentration is 30g/L to 50g/L, and adding concentration is the inorganic additive of the chloride ion-containing of 40mg/L to 60mg/L in this solution, and the electric current of plating is 4.5 amperes to 45 amperes.
Step S106 carries out annealing, process for cooling more than 3 times to described metal level 240.
By background technology as can be known, big hole shape defective can be moved and be gathered into to the microdefect of metal level in the interconnection structure that prior art forms, and the metal layer stress that existing annealing process can cause is piled up, also can make the substrate-like camber that is formed with metal level, produce the warpage effect, can cause device to scrap equally when serious.
For this reason, the present inventor is through a large amount of experiment, and the annealing process to described metal level is optimized comprises: described metal level 240 is carried out annealing, process for cooling more than 3 times.Each concrete technology is: to described metal level 240 annealing, annealing temperature be 100 degree to 400 degree, annealing time is 10 seconds to 50 seconds, after annealing finishes described metal level is cooled to room temperature, be 15 seconds to 60 seconds cooling time.
Further experimental studies have found that through the inventor, described metal level 240 is carried out annealing, process for cooling more than 3 times, can effectively avoid in metal level 240, forming big hole shape defective, and can not form bigger stress in metal level 240 piles up, avoid being formed with the substrate-like camber of metal level, produce the warpage effect.
Through a large amount of experiment of the present inventor; find described described metal level to be carried out annealing, process for cooling more than 3 times; but the annealing number of times was smaller or equal to 20 o'clock; described annealing process can be taken into account practicality and production efficiency; certainly; the annealing of more times number also can realize avoiding forming big hole shape defective in metal level 240; and can not form bigger stress in metal level 240 piles up; and the effect of avoiding being formed with the substrate-like camber of metal level; produce the warpage effect; specially illustrate at this, should too not limit protection scope of the present invention.
Step S107 carries out chemico-mechanical polishing until exposing dielectric layer 210 to described metal level 240.
With reference to Figure 11, described CMP (Chemical Mechanical Polishing) process selects the glossing corresponding with described metal level 240 that described metal level 240 is carried out chemico-mechanical polishing.
In the present embodiment, described CMP (Chemical Mechanical Polishing) process is selected the glossing of selective removal copper for use, the concrete parameter of described CMP (Chemical Mechanical Polishing) process is: select for use silica as polishing particles, the pH value of polishing fluid is 10 to 11.5, the flow of polishing fluid is 200 milliliters of per minute to 400 milliliter per minutes, the rotating speed of grinding pad is 83 rpms to 103 rpms in the glossing, the rotating speed of grinding head is 77 rpms to 97 rpms, the pressure of glossing is 5500 handkerchief to 6500 handkerchiefs, until exposing dielectric layer 210.
The present invention carries out annealing, process for cooling more than 3 times by adopting to described metal level 240, can avoid in metal level 240, forming bigger stress effectively, thereby produce hole shape defective owing to stress is excessive in the metal level 240 that can avoid forming, improved the yield and the reliability of chip.In addition, the present invention can also avoid being formed with metal level 240 substrate after annealing process is finished and the warpage effect that produces.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. the formation method of an interconnection structure is characterized in that, comprising:
Substrate is provided;
Form dielectric layer at described substrate surface;
In described dielectric layer, form the contact hole that exposes substrate;
Form the barrier layer on described contact hole sidewall, bottom and dielectric layer surface;
Form the metal level of filling contact hole at described barrier layer surface;
Described metal level is carried out annealing, process for cooling more than 3 times;
Described metal level is carried out chemico-mechanical polishing until exposing dielectric layer.
2. the formation method of interconnection structure as claimed in claim 1 is characterized in that, described metal level is carried out the concrete number of times of annealing, process for cooling more than 3 times less than 20 times.
3. the formation method of interconnection structure as claimed in claim 1, it is characterized in that, described metal level carried out each concrete technology is in the annealing, process for cooling more than 3 times: to described metal level annealing, annealing temperature is that 100 degree are to 400 degree, annealing time is 10 seconds to 50 seconds, after annealing finishes described metal level is cooled to room temperature, be 15 seconds to 60 seconds cooling time.
4. the formation method of interconnection structure as claimed in claim 1 is characterized in that, the technology that described formation exposes the contact hole of substrate is plasma etch process.
5. the formation method of interconnection structure as claimed in claim 1 is characterized in that, the material on described barrier layer is tantalum, tantalum nitride, titanium or titanium nitride.
6. the formation method of interconnection structure as claimed in claim 1 is characterized in that, described barrier layer is single layer structure or multilayer overlaying structure.
7. the formation method of interconnection structure as claimed in claim 1 is characterized in that, also comprises before the metal level step of described barrier layer surface formation filling contact hole: the inculating crystal layer step that forms copper at described barrier layer surface.
8. the formation method of interconnection structure as claimed in claim 1 is characterized in that, the material of described metal level is a copper.
9. the formation method of interconnection structure as claimed in claim 8 is characterized in that, the technology of the metal level of described formation filling contact hole is electroplating technology.
10. the formation method of interconnection structure as claimed in claim 9 is characterized in that, the concrete parameter of described electroplating technology is: electroplate liquid is selected CuSO for use
4Solution, Cu
2+Concentration is 30g/L to 50g/L, and adding concentration is the inorganic additive of the chloride ion-containing of 40mg/L to 60mg/L in this solution, and the electric current of plating is 4.5 amperes to 45 amperes.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426751A (en) * | 2012-05-14 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
| CN104078340A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Copper layer graphical method and methods for forming copper plug, grid electrode and interconnection line |
| CN104934363A (en) * | 2014-03-17 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal structure in semiconductor device, and manufacturing method for interconnection layer |
| CN106558530A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor device |
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|---|---|---|---|---|
| US20030181032A1 (en) * | 2002-03-20 | 2003-09-25 | Masaya Kawano | Method of fabricating semiconductor device |
| US20040259376A1 (en) * | 2003-06-20 | 2004-12-23 | Chen-Ming Huang | Method of reducing stress migration in integrated circuits |
-
2009
- 2009-11-02 CN CN2009101981155A patent/CN102054750A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030181032A1 (en) * | 2002-03-20 | 2003-09-25 | Masaya Kawano | Method of fabricating semiconductor device |
| US20040259376A1 (en) * | 2003-06-20 | 2004-12-23 | Chen-Ming Huang | Method of reducing stress migration in integrated circuits |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426751A (en) * | 2012-05-14 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
| CN103426751B (en) * | 2012-05-14 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN104078340A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Copper layer graphical method and methods for forming copper plug, grid electrode and interconnection line |
| CN104934363A (en) * | 2014-03-17 | 2015-09-23 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal structure in semiconductor device, and manufacturing method for interconnection layer |
| CN104934363B (en) * | 2014-03-17 | 2018-09-18 | 中芯国际集成电路制造(上海)有限公司 | The production method for forming the method and interconnection layer of metal structure in the semiconductor device |
| CN106558530A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor device |
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