CN115513135A - Semiconductor processing method and semiconductor etching equipment - Google Patents
Semiconductor processing method and semiconductor etching equipment Download PDFInfo
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- CN115513135A CN115513135A CN202211438650.5A CN202211438650A CN115513135A CN 115513135 A CN115513135 A CN 115513135A CN 202211438650 A CN202211438650 A CN 202211438650A CN 115513135 A CN115513135 A CN 115513135A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
The semiconductor process method comprises the steps of depositing an intermetallic dielectric layer on the upper surface of a first metal layer, forming a target groove and a target through hole through photoetching and etching processes based on the intermetallic dielectric layer, cleaning etching residues corresponding to the photoetching and etching processes, depositing a metal barrier layer and a metal seed layer on the upper surfaces of the cleaned target groove, the cleaned target through hole and the intermetallic dielectric layer, electroplating a second metal layer on the upper surface of the metal seed layer to fill the target groove and the target through hole with metal, carrying out heat treatment on the second metal layer, carrying out chemical mechanical grinding treatment on the heat-treated second metal layer, depositing a dielectric protection layer on the upper surface of the chemically mechanical ground second metal layer, and carrying out heat treatment before carrying out chemical mechanical grinding treatment on the second metal layer, so that the growth efficiency of the whole crystal grain can be greatly improved.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a semiconductor process method and semiconductor etching equipment.
Background
As the technology node of the integrated circuit advances to 0.25 μm, the back-end-of-line interconnection of the integrated circuit becomes the bottleneck in improving the performance of the integrated circuit, i.e., the feature size is continuously reduced, and the rc delay generated by the interconnection metal is increased accordingly. In order to slow down the increase of the resistance-capacitance delay, the current technical means is to change the material of the back-end interconnection, on one hand, a low dielectric layer is adopted as an interconnection insulator to provide lower capacitance between adjacent metal lines; on the other hand, a metal with lower resistivity is used instead of conventional aluminum to reduce the resistance of the back-end interconnect.
For the fabrication of metal interconnects, the most mature process at present is the damascene process (single/dual damascene), which is characterized by etching trenches or vias first, followed by plating of the metal layer. Classical size effect theory states that the resistivity of metal films and wires increases as their critical dimensions (film thickness, wire width and height) approach or are smaller than the electron mean free path. Therefore, as the critical dimension of the interconnection metal layer is reduced, the resistivity of the metal layer is increased, and research shows that grain boundary scattering and surface scattering are the most main factors for increasing the resistivity of the interconnection metal layer, and meanwhile, compared with surface scattering, the grain boundary scattering effect is relatively larger, because the smaller the thickness of the metal layer, the smaller the grains are, the larger the proportion of the grain boundaries is, and the larger the scattering effect of the grain boundaries on free electrons is.
For an interconnection metal layer, in order to reduce the scattering effect of grain boundaries on free electrons to reduce the resistivity of the metal layer, a currently common technical method is to realize the growth of copper crystal grains through an annealing process.
However, the current annealing processes have certain limitations, such as the self-annealing process of electroplated copper takes a long time, and even several months are difficult to crystallize, i.e. it is difficult to achieve rapid growth of crystal grains.
Disclosure of Invention
In view of this, the present application provides a semiconductor process method and apparatus, which can rapidly realize the growth of metal grains, greatly reduce the scattering effect of grain boundaries in the interconnected metal layers on free electrons, and realize the reduction of the resistivity of the metal layers.
A semiconductor process method is applied to a semiconductor chip for completing a previous device process, the semiconductor chip comprises a semiconductor substrate provided with a first metal layer, and the semiconductor process method comprises the following steps:
depositing an inter-metal dielectric layer on the upper surface of the first metal layer;
forming a target groove and a target through hole through photoetching and etching processes based on the intermetallic dielectric layer;
cleaning etching residues corresponding to the photoetching and etching processes, and depositing a metal barrier layer and a metal seed layer on the upper surfaces of the cleaned target groove, the target through hole and the intermetallic dielectric layer;
electroplating a second metal layer on the upper surface of the metal seed layer to fill the target groove and the target through hole with metal;
carrying out heat treatment on the second metal layer;
and carrying out chemical mechanical polishing treatment on the second metal layer after the heat treatment, and depositing a medium protective layer on the upper surface of the second metal layer after the chemical mechanical polishing treatment.
In one embodiment, the temperature range of the heat treatment is 350 ℃ to 500 ℃.
In one embodiment, the temperature range of the heat treatment is 350 ℃ to 450 ℃.
In one embodiment, the temperature range of the heat treatment is 380 ℃ to 450 ℃.
In one embodiment, the time period for the heat treatment ranges from 3 min to 10min.
In one embodiment, a protective gas is introduced during the heat treatment of the second metal layer.
In one embodiment, the shielding gas is N 2 。
In one embodiment, the intermetal dielectric layer includes a dielectric barrier layer, a dielectric layer and an oxide layer, and the step of forming the target trench and the target via hole by photolithography and etching processes based on the intermetal dielectric layer includes:
arranging a first photoresist layer above the oxide layer based on a primary photoetching process, and forming a first photoetching pattern above the first photoresist layer;
opening the oxide layer according to the first photoetching pattern until part of the dielectric layer is removed to form a target groove;
setting a second photoresist layer in the target groove, and forming a second photoetching pattern above the second photoresist layer;
a target via is formed through the dielectric layer and the dielectric barrier layer according to a second lithographic pattern.
In one embodiment, the first metal layer and the second metal layer are both copper metal layers.
In addition, the semiconductor etching equipment comprises a processor and a memory, wherein the memory is used for storing a computer program, and the processor runs the computer program to enable the semiconductor etching equipment to execute the semiconductor processing method.
The semiconductor process method is applied to a semiconductor chip for completing a previous device process, the semiconductor chip comprises a semiconductor substrate provided with a first metal layer, the semiconductor process method comprises the steps of depositing an intermetallic dielectric layer on the upper surface of the first metal layer, forming a target groove and a target through hole through a photoetching and etching process based on the intermetallic dielectric layer, cleaning etching residues corresponding to the photoetching and etching process, depositing a metal barrier layer and a metal seed layer on the upper surfaces of the cleaned target groove, target through hole and intermetallic dielectric layer, electroplating a second metal layer on the upper surface of the metal seed layer to fill the target groove and target through hole with metal, carrying out heat treatment on the second metal layer, carrying out chemical mechanical grinding treatment on the second metal layer after heat treatment, depositing a dielectric protection layer on the upper surface of the second metal layer after chemical mechanical grinding treatment, effectively improving the effective thickness of the metal layer, further increasing the recrystallization capacity of the metal layer, improving the power of the follow-up whole grain, greatly reducing the scattering effect of grain boundaries in the interconnected metal layer on free electrons so as to realize the reduction of the growth of the metal layer, and further realizing the maximum growth delay of the grain growth of the metal layer, namely the growth of the whole grain.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a semiconductor processing method according to an embodiment of the present disclosure;
fig. 2 is a schematic view of a scanning electron microscope corresponding to a second metal layer not subjected to a thermal treatment in a semiconductor processing method according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a metallographic structure of a second metal layer after a heat treatment at 300 ℃ in a semiconductor processing method according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a metallographic structure corresponding to a second metal layer subjected to a heat treatment at a temperature of 400 ℃ in a semiconductor processing method according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a metallographic structure of a second metal layer after being subjected to a heat treatment at a temperature of 600 ℃ in a semiconductor processing method according to an embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional view illustrating a semiconductor chip in a semiconductor processing method according to an embodiment of the present disclosure;
fig. 7 is a flowchart illustrating a method for forming a target trench and a target via on a semiconductor chip according to an embodiment of the present disclosure;
FIG. 8 is a second cross-sectional view of a semiconductor chip in a semiconductor processing method according to an embodiment of the present application;
fig. 9 is a third schematic cross-sectional view of a semiconductor chip in a semiconductor processing method according to an embodiment of the present application;
fig. 10 is a fourth cross-sectional view of a semiconductor chip in a semiconductor processing method according to an embodiment of the present application;
fig. 11 is a schematic cross-sectional view illustrating a semiconductor chip in a semiconductor processing method according to an embodiment of the present disclosure;
fig. 12 is a schematic sixth cross-sectional view of a semiconductor chip in a semiconductor processing method according to an embodiment of the present application;
fig. 13 is a seventh cross-sectional view of a semiconductor chip in the semiconductor processing method according to the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In this application, where the context requires no explicit explanation, the use of directional words such as "upper" and "lower" in particular refers to the direction of the drawing in the figures. In addition, in the description of the present application, the term "including" means "including but not limited to".
Various embodiments of the invention may exist in a range of forms; it is to be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention; accordingly, the described range descriptions should be considered to have specifically disclosed all the possible sub-ranges as well as individual numerical values within that range. For example, it is contemplated that the description of a range from 1 to 6 has specifically disclosed sub-ranges such as, for example, from 1 to 2, from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 3, from 2 to 4, from 2 to 5, from 2 to 6, from 3 to 4, from 3 to 5, from 3 to 6, etc., as well as individual numbers within the stated range such as, for example, 1, 2, 3, 4, 5, and 6, regardless of the range. In addition, whenever a numerical range is indicated herein, it is meant to include any number (fractional or integer) recited within the range so indicated.
In the interconnection metal layer, to reduce scattering effect of grain boundaries on free electrons of the interconnection metal layer to reduce resistivity of the interconnection metal layer, the most common technical method at present is to realize growth of metal grains through an annealing process.
In fact the growth of the grains of the electroplated metal can be achieved by self-annealing at room temperature. However, self-annealing also has certain limitations: firstly, the self-annealing process has long time effect, and complete recrystallization is difficult to realize even after several months; secondly, the self-annealing is difficult to realize the dispersion of electroplating residual inclusion on the surface of the copper layer; thirdly, self-annealing is difficult to reduce scattering of free electrons by intragranular defects such as dislocations.
As shown in fig. 1, a semiconductor processing method is provided, which is applied to a semiconductor chip that is used for completing a previous device process, the semiconductor chip includes a semiconductor substrate provided with a first metal layer, and the semiconductor processing method includes:
step S110, depositing an inter-metal dielectric layer on the upper surface of the first metal layer.
The intermetal dielectric layer is two intermetal nonmetal layers, and the intermetal dielectric layer may include a plurality of dielectric layers, for example, at least two of a dielectric barrier layer, a dielectric layer, and an oxide layer.
The first metal layer may be aluminum or copper with excellent conductivity.
And step S120, forming a target groove and a target through hole through photoetching and etching processes based on the intermetallic dielectric layer.
And forming a target groove and a target through hole on the intermetallic dielectric layer by photoetching and etching processes.
In one embodiment, a target trench is formed on the intermetallic dielectric layer by a primary photolithography and etching process, and then a target via is further formed in the target trench region by a secondary photolithography and etching process, that is, etching of the target trench and the target via is completed by two photolithography and etching processes.
Step S130, cleaning the etching residues corresponding to the photoetching and etching processes, and depositing a metal barrier layer and a metal seed layer on the upper surfaces of the cleaned target groove, the target through hole and the intermetallic dielectric layer.
Etching residues are generated in the photoetching and etching processes, so that the etching residues need to be cleaned, and after the cleaning, a metal barrier layer and a metal seed layer are further deposited on the upper surfaces of the target groove, the target through hole and the intermetallic dielectric layer in sequence, wherein the metal seed layer is usually positioned on the upper surface of the metal barrier layer.
Step S140, a second metal layer is electroplated on the upper surface of the metal seed layer so as to fill the target groove and the target through hole with metal.
In one embodiment, the second metal layer is made of the same material as the first metal layer, and the second metal layer can be formed on the upper surface of the metal seed layer by performing a metal plating process, so that the target trench and the target via hole can be filled with metal.
Step S150, heat treatment is performed on the second metal layer.
Wherein, after obtaining the second metal level, accessible thermal treatment heats the second metal level, herein heat the second metal level before step S160, can effectual improvement metal level effective thickness, and then increase the recrystallization ability of metal level, promote the power that follow-up whole crystalline grain grows up, the reduction in order to realize the metal level resistivity of the scattering effect of grain boundary to free electron in the interconnection metal level that has significantly reduced, and then the growth of realization metal crystalline grain that can be quick, the growth efficiency of whole crystalline grain has been promoted greatly, the resistance-capacitance delay that furthest slowed down the interconnection metal level promptly.
Step S160, performing a chemical mechanical polishing process on the heat-treated second metal layer, and depositing a dielectric protection layer on the upper surface of the chemically mechanical polished second metal layer.
The semiconductor process method is applied to a semiconductor chip for completing the previous device process, the semiconductor chip comprises a semiconductor substrate provided with a first metal layer, the semiconductor process method comprises the steps of depositing an intermetallic dielectric layer on the upper surface of the first metal layer, forming a target groove and a target through hole through photoetching and etching processes based on the intermetallic dielectric layer, cleaning etching residues corresponding to the photoetching and etching processes, depositing a metal barrier layer and a metal seed layer on the upper surfaces of the cleaned target groove, target through hole and intermetallic dielectric layer, electroplating a second metal layer on the upper surface of the metal seed layer to fill the target groove and target through hole with metal, carrying out heat treatment on the second metal layer, and carrying out chemical mechanical grinding treatment on the second metal layer after the heat treatment, and a dielectric protection layer is deposited on the upper surface of the second metal layer after the chemical mechanical grinding treatment, and the second metal layer is treated before the chemical mechanical grinding treatment, compared with the conventional technology in which the heat treatment process is placed after the step S160, the semiconductor process method can effectively improve the effective thickness of the metal layer by heating the second metal layer before the step S160, thereby increasing the recrystallization capacity of the metal layer, improving the power of the subsequent growth of the whole crystal grain, greatly reducing the scattering effect of the crystal boundary in the interconnected metal layer on free electrons to realize the reduction of the resistivity of the metal layer, further quickly realizing the growth of the metal crystal grain, greatly improving the growth efficiency of the whole crystal grain, and reducing the resistance-capacitance delay of the interconnected metal layer to the maximum extent.
In one embodiment, the temperature range of the heat treatment is preferably 350 ℃ to 500 ℃.
In this embodiment, the heat treatment temperature is not too low, and for the ultra-fine metal grains or nano-metal grains, it is difficult to achieve complete recrystallization and rapid growth of the grains in the metal layer at a low temperature, the grain growth effect is poor, and even the grains may not be recrystallized completely, for example, for the copper metal film, complete recrystallization can be achieved only at a temperature of about 350 ℃, and in addition, the high temperature can also promote the dispersion of the plating residual inclusion on the surface of the metal layer, and weaken the barrier effect of the plating residual inclusion on the grain boundary migration inside the metal layer, so the heat treatment temperature is usually kept above 350 ℃.
Similarly, the temperature of the heat treatment should not be too high, and the temperature is too high, for example, when the temperature exceeds 500 ℃ in the above-mentioned whole semiconductor process using copper metal, although the rapid growth of crystal grains is favored, other processes of the semiconductor, such as affecting the distribution of front-end implanted ions and the structure of the low dielectric layer, are damaged.
In the embodiment, the heat treatment within the temperature range of 350-500 ℃ is adopted, so that the scattering effect of the intragranular defects is weakened or even eliminated to the maximum extent, and the whole grain size can be greatly increased through the heat treatment within the temperature range, and the grain size increasing efficiency is improved.
In one embodiment, the second metal layer is a copper metal film layer, and when the second metal layer is not subjected to a heat treatment, as shown in fig. 2, fig. 2 is a scanning electron microscope diagram corresponding to the case where the second metal layer is not subjected to a heat treatment, it can be seen that crystal grains are at an ultra-fine grain level before the heat treatment.
In one embodiment, the second metal layer is a metallic copper film layer, and is heat-treated at 300 ℃ for 10 minutes, as shown in fig. 3, and fig. 3 is a metallographic structure of ultra-fine pure copper with a size of 10 microns after the heat treatment, it is obvious that after the low-temperature heat treatment, although some grains grow up (for example, arrow a in fig. 3), a substantial part of the grains are in a recrystallized state, and no significant growth occurs.
In another embodiment, the second metal layer is a metallic copper film layer, and after heat treatment at 400 ℃, as shown in fig. 4, fig. 4 is a metallographic structure of ultra-fine grained pure copper with a size of 10 microns after the heat treatment in the process, the grains are significantly grown (for example, as indicated by arrows b in fig. 4).
In another embodiment, the second metal layer is a metallic copper film layer, and after 600 ℃ heat treatment, as shown in fig. 5, fig. 5 shows the metallographic structure of 50 micron ultra-fine pure copper after the heat treatment, and after the heat treatment at an excessively high temperature, grains grow further, but the high temperature may have a destructive effect on the low dielectric layer structure.
In one embodiment, the temperature range of the heat treatment is further preferably 350 ℃ to 450 ℃.
In this embodiment, the maximum temperature for the thermal treatment is further limited to 450 ℃, so as to further reduce the influence of the high temperature on the semiconductor process, such as the distribution of the ions implanted in the front channel and the structure of the low dielectric layer.
In one embodiment, the temperature range of the heat treatment is further preferably 380 ℃ to 450 ℃.
In this embodiment, the minimum temperature of the heat treatment is further increased to further reduce or even eliminate the scattering effect of the intragranular defects to the maximum extent, and keeping the minimum temperature of the heat treatment at 380 ℃ or higher helps to further promote the dispersion of the plating residual inclusions on the surface of the metal layer and weaken the effect of inhibiting the grain boundary migration in the metal layer.
In one embodiment, the time period of the heat treatment is preferably in the range of 3 min to 10min.
In the above-mentioned whole semiconductor process, the heat treatment time is also very critical, and the heat treatment time is too short, so that even if the temperature is high, it is difficult to accumulate enough heat in a short time, to reduce or eliminate the scattering effect of intragranular defects to the maximum extent, and to facilitate the rapid growth of the whole metal crystal grains, and therefore, the heat treatment time is usually not less than 3 minutes.
Similarly, in the heat treatment process, if the heat treatment time is too long, too much heat is easily generated, which is disadvantageous for the whole semiconductor process, therefore, the time is usually not more than 10 minutes.
In one embodiment, the heat treatment time is no more than 5 minutes.
In one embodiment, a protective gas is introduced during the heat treatment of the second metal layer.
In one embodiment, the shielding gas is preferably N 2 。
In one embodiment, as shown in fig. 6, the semiconductor chip is provided with a semiconductor substrate 10 of a first metal layer 20, an intermetal dielectric layer 30 is deposited on an upper surface of the first metal layer 20, the intermetal dielectric layer 30 includes a dielectric barrier layer 31, a dielectric layer 32 and an oxide layer 33, as shown in fig. 7, and step S120 includes:
step S122, a first photoresist layer is disposed on the oxide layer based on the first photolithography process, and a first photolithography pattern is formed on the first photoresist layer.
In step S124, the oxide layer is opened according to the first photolithography pattern until a portion of the dielectric layer is removed to form a target trench.
As shown in fig. 8, a first photoresist layer 40 is disposed on the oxide layer 33 based on the first photolithography process, a first photolithography pattern is formed on the first photoresist layer 40, and then the oxide layer 33 is opened based on the first photolithography pattern until a portion of the dielectric layer 32 is removed to form a target trench 50.
Step S126, a second photoresist layer is disposed in the target trench, and a second lithographic pattern is formed on the second photoresist layer.
In step S128, a target via is formed through the dielectric layer and the dielectric barrier layer according to a second lithographic pattern.
In step S126 and step S128, as shown in fig. 9, the second photoresist layer 60 is disposed in the target trench 50, a second photolithography pattern is formed on the second photoresist layer 60, and then the target via 70 is formed through the dielectric layer 32 and the dielectric barrier layer 31 according to the second photolithography pattern, as shown in fig. 10.
Further, based on step S130, the etching residues corresponding to the photolithography and etching processes are cleaned, and the metal barrier layer 80 and the metal seed layer 90 are deposited on the upper surfaces of the cleaned target trench 50, the target via 70 and the intermetal dielectric layer 30, as shown in fig. 11.
Further, based on step S140, a second metal layer 100 is electroplated on the upper surface of the metal seed layer 90 to perform metal filling on the target trench 50 and the target via 70, as shown in fig. 12.
Further, based on step S150, the second metal layer 100 is subjected to a thermal treatment, and then based on step S160, the second metal layer 100 after the thermal treatment is subjected to a chemical mechanical polishing treatment, and a dielectric protection layer 200 is deposited on the upper surface of the second metal layer 100 after the chemical mechanical polishing treatment, as shown in fig. 13.
As shown in fig. 6 and 8 to 13, the layer structure provided between the first metal layer 20 and the semiconductor substrate 10 is a dielectric barrier layer (not shown).
In one embodiment, the first metal layer and the second metal layer are both copper metal layers.
In addition, the semiconductor etching equipment comprises a processor and a memory, wherein the memory is used for storing a computer program, and the processor runs the computer program to enable the semiconductor etching equipment to execute the semiconductor processing method.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.
In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "for example" is used to mean "serving as an example, instance, or illustration". Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make and use the present application. In the foregoing description, various details have been set forth for the purpose of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (10)
1. A semiconductor process method is applied to a semiconductor chip for completing a previous device process, the semiconductor chip comprises a semiconductor substrate provided with a first metal layer, and the semiconductor process method comprises the following steps:
depositing an intermetallic dielectric layer on the upper surface of the first metal layer;
forming a target groove and a target through hole through photoetching and etching processes based on the intermetallic dielectric layer;
cleaning the etching residues corresponding to the photoetching and etching processes, and depositing a metal barrier layer and a metal seed layer on the upper surfaces of the cleaned target groove, the target through hole and the intermetallic dielectric layer;
electroplating a second metal layer on the upper surface of the metal seed layer to fill the target groove and the target through hole with metal;
performing heat treatment on the second metal layer;
and carrying out chemical mechanical polishing treatment on the second metal layer after the heat treatment, and depositing a medium protective layer on the upper surface of the second metal layer after the chemical mechanical polishing treatment.
2. The semiconductor processing method of claim 1, wherein the temperature of the heat treatment ranges from 350 ℃ to 500 ℃.
3. The semiconductor processing method of claim 2, wherein the temperature of the heat treatment ranges from 350 ℃ to 450 ℃.
4. The semiconductor processing method of claim 3, wherein the temperature range of the heat treatment is 380 ℃ to 450 ℃.
5. The semiconductor process method according to claim 1, wherein the time range of the heat treatment is 3 min to 10min.
6. The semiconductor processing method according to claim 1, wherein a protective gas is filled during the heat treatment of the second metal layer.
7. The semiconductor processing method of claim 6, wherein the protective gas is N 2 。
8. The semiconductor process method according to claim 1, wherein the inter-metal dielectric layer comprises a dielectric barrier layer, a dielectric layer and an oxide layer, and the step of forming the target trench and the target via hole by the photolithography and etching process based on the inter-metal dielectric layer comprises:
arranging a first photoresist layer above the oxide layer based on a primary photoetching process, and forming a first photoetching pattern above the first photoresist layer;
opening the oxide layer according to the first photoetching pattern until part of the dielectric layer is removed to form the target groove;
setting a second photoresist layer in the target groove, and forming a second photoetching pattern above the second photoresist layer;
penetrating the dielectric layer and the dielectric barrier layer according to the second lithographic pattern to form the target via.
9. The semiconductor processing method of claim 1, wherein the first metal layer and the second metal layer are both copper metal layers.
10. A semiconductor etching apparatus, comprising a processor and a memory, the memory storing a computer program, the processor executing the computer program to cause the semiconductor etching apparatus to perform the semiconductor processing method of any one of claims 1 to 9.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1449015A (en) * | 2002-04-01 | 2003-10-15 | 海力士半导体有限公司 | Method for forming metal interconnecting layers in semiconductor device |
| CN101996928A (en) * | 2009-08-14 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN102903666A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN105097648A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interconnection structure |
| US20190157144A1 (en) * | 2017-11-21 | 2019-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and forming method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1449015A (en) * | 2002-04-01 | 2003-10-15 | 海力士半导体有限公司 | Method for forming metal interconnecting layers in semiconductor device |
| CN101996928A (en) * | 2009-08-14 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN102903666A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN105097648A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interconnection structure |
| US20190157144A1 (en) * | 2017-11-21 | 2019-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and forming method thereof |
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