CN101996143B - Electronic device reset circuit - Google Patents
Electronic device reset circuit Download PDFInfo
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- CN101996143B CN101996143B CN 200910171042 CN200910171042A CN101996143B CN 101996143 B CN101996143 B CN 101996143B CN 200910171042 CN200910171042 CN 200910171042 CN 200910171042 A CN200910171042 A CN 200910171042A CN 101996143 B CN101996143 B CN 101996143B
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Abstract
The invention discloses an electronic device reset circuit and an electronic device reset method. The reset circuit comprises a reset switch, a reset signal generation unit, a delay unit and a processing unit; and when a user presses down the reset switch, the reset signal generation unit generates a first reset signal to inform the processing unit, while the delay unit delays the first reset signal to generate a second reset signal so as to carry out system reset, and the processing unit finishes or ends up the write procedure of a flash memory within the delay time set by the delay unit so as to avoid data loss.
Description
Technical field
The invention relates to a kind of reset circuit, and particularly relevant for a kind of reset circuit of avoiding the flash data in the electronic installation to run off.
Background technology
General computing machine all is provided with reset switch or replacement button, is used for carrying out the replacement of system, and when computer down or when making a mistake, the user can press reset switch starts shooting to recover normal condition system again.
Yet the flash memory in the system must write with the block mode usually, so when flash memory write data, if the user presses reset switch, the data that writing at present can run off because system resets.For addressing the above problem; Have the mode of employing to have following several kinds at present: (1) with in the reset signal import system, and then controls time of replacement by system, and this mode is directly to utilize the software of system itself to write; System judges whether the replacement button has action, and carries out user's demand.Utilize software control can reach user's demand easily, if but system has originally worked as machine, and then can cause the replacement button also and then to lose efficacy.(2) increase the replacement poster and on machine or instructions, inform the user; Reset the issuable risk in back to evade related responsibility; Instructing the user must carry out data backup often simultaneously handles; Though the responsibility that this mode can avoid responsibility to run off can cause user's use burden, responsibility is married again the user.
(3) when carrying out data when reading, by system's anergy replacement button, this mode need add the effect that some circuit are reached the replacement anergy; System is so long as not write the fashionable machine of working as in data; Can let the user reset freely,, lose efficacy but still have an opportunity to cause to reset so reduce the chance that to reset when machine because of system greatly; And anergy also is to inform the user when resetting, and the person of avoiding the use of thinks that it is invalid resetting.(4) but use the programmed logic integrated circuit to reach this purpose, but price is higher, and needs the labor intensive exploitation again, circuit neither pure hardware designs.(5) not in comprehending, whether like the product of design low order or do not have significant data and can preserve comparatively, not comprehending data has and loses, and such way price is the most cheap, but the user understands relatively poor to product and label impression.
Summary of the invention
The present invention provides a kind of reset circuit, resets after can reset signal being postponed a period of time again, and utilizes time of this delay to accomplish the data access program of flash memory, avoids the problem of resetting and causing data to run off because of system.
Hold above-mentionedly, the present invention proposes a kind of reset circuit, is suitable for an electronic installation, and above-mentioned electronic installation has a flash memory, and above-mentioned reset circuit comprises a reset switch, a reset signal generation unit, a delay cell, a processing unit.Wherein, reset switch is in order to the above-mentioned electronic installation of resetting; The reset signal generation unit is coupled to reset switch, when reset switch enables, produces first reset signal.Delay cell is coupled to the reset signal generation unit, in order to postpone first reset signal, one Preset Time to produce one second reset signal.Processing unit couples between reset signal generation unit, delay cell and the flash memory.When first reset signal enabled, processing unit detected flash memory according to first reset signal and whether is carrying out write-in program.If flash memory carrying out write-in program, then processing unit is accomplished in Preset Time or the write-in program of the flash memory that terminates, and carries out system's replacement according to second reset signal then.
In an embodiment of the present invention, above-mentioned replacement letter signal generation unit comprises a voltage source, one first electric capacity, one first resistance, one first NPN transistor, a PMOS transistor, one the 3rd resistance and one second electric capacity.Voltage source is coupled to first end of above-mentioned reset switch; First electric capacity is coupled between one second end and an earth terminal of above-mentioned reset switch; First resistance is coupled between above-mentioned second end and one second resistance of above-mentioned reset switch, and the other end of above-mentioned second resistance is coupled to above-mentioned earth terminal.The base stage of first NPN transistor is coupled to the shared node of above-mentioned first resistance and above-mentioned second resistance, and the emitter of above-mentioned first NPN transistor is coupled to above-mentioned earth terminal; The transistorized grid of above-mentioned PMOS couples the collector of above-mentioned first NPN transistor, and above-mentioned PMOS transistor drain is coupled to above-mentioned voltage source, and the transistorized source electrode of above-mentioned PMOS is exported above-mentioned first reset signal; The 3rd resistance is coupled between above-mentioned voltage source and the transistorized grid of above-mentioned PMOS; Second electric capacity is coupled between transistorized source electrode of above-mentioned PMOS and the above-mentioned earth terminal.
In an embodiment of the present invention, above-mentioned delay cell comprises one the 3rd electric capacity, one the 4th resistance, a replacement integrated circuit, one the 5th resistance and one the 6th resistance.One end of the 3rd electric capacity is coupled to an earth terminal.One termination of the 4th resistance is received above-mentioned first reset signal, and the other end of above-mentioned the 4th resistance couples the other end of above-mentioned the 3rd electric capacity and forms shared node.One input end of above-mentioned replacement integrated circuit receives above-mentioned first reset signal; One output terminal of above-mentioned replacement integrated circuit is coupled to the shared node of above-mentioned the 4th resistance and above-mentioned the 3rd electric capacity, and above-mentioned replacement integrated circuit is in order to postpone above-mentioned first reset signal and above-mentioned first reset signal after the above-mentioned output terminal output delay of above-mentioned replacement integrated circuit.The 5th resistance is coupled between the base stage of shared node and one second NPN transistor of above-mentioned the 4th resistance and above-mentioned the 3rd electric capacity, and the emitter of above-mentioned second NPN transistor is coupled to above-mentioned earth terminal; The 6th resistance is coupled between the collector of above-mentioned voltage source and above-mentioned second NPN transistor, and the collector of wherein above-mentioned second NPN transistor is exported above-mentioned second reset signal.
Wherein above-mentioned delay cell more comprises one the 4th electric capacity and one the 5th electric capacity.The 4th electric capacity and the 5th electric capacity coupled in parallel are in above-mentioned delay cell, and above-mentioned replacement integrated circuit determines the length of above-mentioned Preset Time according to the capacitance of the 4th electric capacity and above-mentioned the 5th electric capacity.
In an embodiment of the present invention, above-mentioned electronic installation is computing machine, notebook or mobile phone, and above-mentioned flash memory is Sheffer stroke gate flash memory (NAND flash).
From another perspective, the present invention proposes a kind of remapping method of electronic installation in addition, and above-mentioned electronic installation has a flash memory and a reset switch, and remapping method comprises the following steps: at first, when reset switch enables, produces one first reset signal; Then, postpone first reset signal to produce one second reset signal; Detect above-mentioned flash memory according to above-mentioned first reset signal and whether carrying out write-in program; If above-mentioned flash memory carrying out write-in program, then accomplish or the write-in program of the above-mentioned flash memory that terminates via a processing unit; Next, behind the write-in program of the completion or the above-mentioned flash memory that terminates, carry out system according to above-mentioned second reset signal and reset.
Based on above-mentioned, the present invention utilizes and postpones the mode of action of resetting, and lets system before resetting, accomplish the data write activity of flash memory earlier, and then carries out system and reset.By this, avoid the problem that data run off taking place because of system's replacement.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Fig. 1 is the reset circuit calcspar according to first embodiment of the invention.
Fig. 2 is the hardware circuit diagram according to the reset circuit of first embodiment of the invention.
Fig. 3 is the signal waveforms according to first embodiment of the invention.
Fig. 4 is the remapping method process flow diagram according to the electronic installation of second embodiment of the invention.
Embodiment
Set forth embodiments of the invention in detail below with reference to accompanying drawing, the for example clear example embodiment of the present invention of accompanying drawing, the wherein same or similar element of same numeral indication.
First embodiment
Please with reference to Fig. 1; Fig. 1 is the reset circuit calcspar according to first embodiment of the invention; Reset circuit 100 comprises reset switch 110, reset signal generation unit 120, delay cell 130 and processing unit 140; Reset signal generation unit 120 is coupled between reset switch 110 and the delay cell 130, and processing unit 140 is coupled between delay cell 130 and the flash memory 150.Reset circuit 100 can be arranged in the electronic installation, and is used for electronic installation is carried out system's replacement.
Because delay cell 130 can postpone just enable the second reset signal RET2 behind the first reset signal RET1, one Preset Time, so processing unit 140 can accomplish the write-in program of flash memory 150 in this Preset Time, avoids the data loss.Processing unit 140 can increase operating frequency with the acceleration write-in program, or the write-in program of termination flash memory 150 runs off to avoid data.In the present embodiment; The mode of accomplishing flash memory 150 write-in programs is not limited; Mainly be that reset circuit 100 can postpone reset signal RET1 earlier, let the processing unit 140 free write-in programs of accomplishing flash memories 150, and then carry out the replacement of system according to the second reset signal RET2.In other words, processing unit 140 is to carry out system according to the second reset signal RET2 to reset, and carries out the data processing of flash memory 150 according to the first reset signal RET1.The write-in program of so-called completion or termination flash memory 150 representes that system can suspend present write-in program earlier and write down the present data that write.Then, when accomplishing to reset, system writes the action of data when also activating again more again.
Formerly in the technology, after the user pressed the replacement button, system just can carry out system at once to be reset, the notifier processes of can't going ahead of the rest unit 140 and set aside some time and let system carry out data processing.Therefore, compared to the present invention, the present invention has the data losing issue that improvement is formerly reset and produced because of system in the technology.
Next, further specify the thin portion circuit diagram of reset signal generation unit 120 and delay cell 130, please with reference to Fig. 2, Fig. 2 is the hardware circuit diagram according to the reset circuit of first embodiment of the invention.Replacement button (Reset botton) on the for example general computer housing of reset switch 110, when the user pressed the replacement button, reset switch 110 can conducting.
Reset signal generation unit 120 comprises first capacitor C 1, second capacitor C 2, first resistance R 1, second resistance R 2 and the 3rd resistance R 3, PMOS transistor (P channel metal oxide semiconductor transistor; Be called for short PMOS) M1 and NPN transistor (NPN bipolar junction transistor is called for short BJT)) Q1.First end of reset switch 110 is coupled to voltage source V DD, and first capacitor C 1 is coupled between second end and earth terminal GND of reset switch 110.First resistance R 1 is coupled between second end and second resistance R 2 of reset switch 110, and the other end of second resistance R 2 is coupled to earth terminal GND.The base stage of the first NPN transistor Q1 is coupled to the shared node of first resistance R 1 and second resistance R 2, and the emitter of the first NPN transistor Q1 is coupled to earth terminal GND.The grid of PMOS transistor M1 couples the collector of the first NPN transistor Q1, and the source electrode of PMOS transistor M1 is coupled to voltage source V DD, and the first reset signal RET1 is then exported in drain electrode.The 3rd resistance R 3 is coupled between the grid of voltage source V DD and PMOS transistor M1.Second capacitor C 2 is coupled between the drain electrode and earth terminal GND of PMOS transistor M1.
When reset switch 100 enables because of the user presses; Capacitor C 1 can begin charging; The first NPN transistor Q1 conducting thereupon then; Make PMOS transistor M1 conducting then, the first reset signal RET1 that the drain electrode of PMOS transistor M1 at this moment can be exported noble potential presses reset switch 100 with the expression user.
The 5th resistance R 5 is coupled between the base stage of shared node and the second NPN transistor Q2 of the 4th resistance R 4 and the 3rd capacitor C 3, and the emitter of the second NPN transistor Q2 is coupled to earth terminal GND.The 5th resistance R 5 is coupled between the collector of the voltage source V DD and the second NPN transistor Q2, and wherein the collector of the second NPN transistor Q2 is exported the second reset signal RET2.
Replacement integrated circuit U1 ready-made delay chip capable of using realizes that main function is to postpone the first reset signal RET1, then via the first reset signal RET1 after its output terminal VOUT output delay.Can determine by capacitor C 4, C5 (being coupled to the pin TC of replacement integrated circuit U1) time delay of replacement integrated circuit U1; Different chips has different delay time circuit and peripheral cell set-up mode; Fig. 2 is merely one embodiment of the invention, does not add at this and gives unnecessary details.Replacement integrated circuit U1 is after the first reset signal RET1 enables, and its output terminal VOUT is with the conducting second NPN transistor Q2 in the time of can postponing to enable behind the Preset Time again.The output voltage that collector produced of the second NPN transistor Q2 is the second reset signal RET2; The second reset signal RET2 can be an electronegative potential because of the second NPN transistor Q2 conducting transition, and transition is a noble potential when the first reset signal RET1 reduces to electronegative potential then.When the first reset signal RET1 reduces to electronegative potential, the replacement integrated circuit U1 power supply of can losing the job, its output terminal VOUT can reduce to electronegative potential and the second NPN transistor Q2 is ended.
Next, further specify the change in voltage of each circuit node among above-mentioned Fig. 2, please with reference to Fig. 3, Fig. 3 is the signal waveforms according to first embodiment of the invention.When the user presses reset switch 110; Reset switch 110 can conductings, the bias voltage VC1 of the capacitor C 1 of winning is drawn high be noble potential, after the user decontrols; Bias voltage VC1 can discharge because of first capacitor C 1 and descend, wherein during D1 time of pressing reset switch 110 for the user.In time T 1; The first NPN transistor Q1 can be because of bias voltage VC1 rising conducting; Its collector voltage VQ1 can descend because of conducting, and a PMOS transistor M1 then can be because of the collector voltage VQ1 decline conducting of the first NPN transistor Q1, at this moment; The first reset signal RET1 enables, i.e. transition is a noble potential.Replacement integrated circuit U1 makes the first reset signal RET1 postpone to enable behind the Preset Time D2 voltage of its output terminal VOUT, and when the first reset signal RET1 transition is electronegative potential, the voltage of its output terminal VOUT also thereupon transition be electronegative potential.This is because replacement integrated circuit U1 is caused as WV with the first reset signal RET1.
The output terminal VOUT voltage meeting conducting second NPN transistor Q2 of replacement integrated circuit U1; Make the second reset signal RET2 along with the output terminal VOUT voltage of replacement integrated circuit U1 rises and rises, and along with the output terminal VOUT voltage of replacement integrated circuit U1 descends and descends.The time D 3 that enables of the second reset signal RET2 is the time that main system is reset.Can know by Fig. 3; When the user presses reset switch 110; The first reset signal RET1 can enable (noble potential) thereupon and press reset switch 110 to inform processing unit 140 users; After postponing a Preset Time D2 then, the second reset signal RET2 just can enable (electronegative potential) thereupon makes system begin to reset.Processing unit 140 can be accomplished in Preset Time D2 or the write-in program of the present ongoing flash memory 150 that terminates runs off to avoid data.
Second embodiment
The explanation of comprehensive the foregoing description, the present invention can summarize a kind of remapping method of electronic installation, and please with reference to Fig. 1 and Fig. 4, Fig. 4 is the remapping method process flow diagram according to the electronic installation of second embodiment of the invention.Wherein electronic installation has a flash memory 150 and a reset switch 110; Remapping method comprises the following steps: at first; When reset switch 110 enables, produce the first reset signal RET1 (step S410), postpone the first reset signal RET1 then to produce one second reset signal RET2 (step S420).Next, detect flash memory 150 according to the first reset signal RET1 and whether carrying out write-in program (step S430),, then accomplish or the write-in program (step S440) of termination flash memory 150 via processing unit 140 if flash memory 150 is carrying out write-in program.Then, behind the write-in program of completion or termination flash memory 150, carry out system according to the second reset signal RET2 and reset.Wherein, if flash memory 150 is not carrying out write-in program, processing unit 140 can just carry out system equally and reset when the second reset signal RET2 enables.All the other details of operations of this remapping method please with reference to the explanation of above-mentioned first embodiment, do not add tired stating at this
Comprehensively above-mentioned, the present invention utilizes pure hardware circuit design replacement integrated circuit, and the system that exports to again after reset signal is postponed is resetting, and apprizing system is prepared to reset in advance.System can accomplish the write-in program of flash memory in advance in the timing period of reset signal, avoid the problem that reset switch causes data to run off of pressing because of user's burst type.
Though the present invention discloses as above with embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when doing a little change and retouching, so protection scope of the present invention is when being as the criterion with what claim defined.
Claims (6)
1. a reset circuit is suitable for an electronic installation, and this electronic installation has a flash memory, and this reset circuit comprises;
One reset switch is in order to this electronic installation of resetting;
One reset signal generation unit is coupled to this reset switch, when this reset switch enables, produces one first reset signal;
One delay cell is coupled to this reset signal generation unit, in order to postpone this first reset signal, one Preset Time to produce one second reset signal; And
One processing unit; Couple between this reset signal generation unit, this delay cell and this flash memory; Wherein when this first reset signal enabled, this processing unit detected this flash memory according to this first reset signal and whether is carrying out write-in program, if this flash memory is carrying out write-in program; Then this processing unit is accomplished in this Preset Time or the write-in program of this flash memory that terminates, and carries out system according to this second reset signal then and resets;
Wherein this reset signal generation unit comprises:
One voltage source is coupled to one first end of this reset switch;
One first electric capacity is coupled between one second end and an earth terminal of this reset switch;
One first resistance is coupled between this second end and one second resistance of this reset switch, and the other end of this second resistance is coupled to this earth terminal;
One first NPN transistor, the base stage of this first NPN transistor are coupled to the shared node of this first resistance and this second resistance, and the emitter of this first NPN transistor is coupled to this earth terminal;
One PMOS transistor, the transistorized grid of this PMOS couples the collector of this first NPN transistor, and the transistorized source electrode of this PMOS is coupled to this voltage source, this this first reset signal of PMOS transistor drain output;
One the 3rd resistance is coupled between this voltage source and the transistorized grid of this PMOS; And
One second electric capacity is coupled between this PMOS transistor drain and this earth terminal.
2. reset circuit as claimed in claim 1 is characterized in that, this delay cell comprises:
One the 3rd electric capacity, an end of the 3rd electric capacity is coupled to an earth terminal;
One the 4th resistance, a termination of the 4th resistance is received this first reset signal, and the other end of the 4th resistance couples the other end of the 3rd electric capacity and forms shared node;
One replacement integrated circuit; One input end of this replacement integrated circuit receives this first reset signal; One output terminal of this replacement integrated circuit is coupled to the shared node of the 4th resistance and the 3rd electric capacity, and this replacement integrated circuit is in order to postpone this first reset signal and this first reset signal after this output terminal output delay of this replacement integrated circuit;
One the 5th resistance is coupled between the base stage of shared node and one second NPN transistor of the 4th resistance and the 3rd electric capacity, and the emitter of this second NPN transistor is coupled to this earth terminal; And
One the 6th resistance is coupled between the collector of this voltage source and this second NPN transistor, wherein this second reset signal of the collector of this second NPN transistor output.
3. reset circuit as claimed in claim 2 is characterized in that, this delay cell more comprises:
One the 4th electric capacity is coupled to this replacement integrated circuit; And
One the 5th electric capacity, the 5th electric capacity is parallelly connected with the 4th electric capacity;
Wherein, this replacement integrated circuit is according to the length of this Preset Time of capacitance decision of the 4th electric capacity and the 5th electric capacity.
4. reset circuit as claimed in claim 1 is characterized in that, this electronic installation is computing machine, notebook or mobile phone.
5. reset circuit as claimed in claim 1 is characterized in that, this flash memory is the Sheffer stroke gate flash memory.
6. reset circuit as claimed in claim 1 is characterized in that, this processing unit is a central processing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910171042 CN101996143B (en) | 2009-08-26 | 2009-08-26 | Electronic device reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910171042 CN101996143B (en) | 2009-08-26 | 2009-08-26 | Electronic device reset circuit |
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| Publication Number | Publication Date |
|---|---|
| CN101996143A CN101996143A (en) | 2011-03-30 |
| CN101996143B true CN101996143B (en) | 2012-12-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910171042 Expired - Fee Related CN101996143B (en) | 2009-08-26 | 2009-08-26 | Electronic device reset circuit |
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| CN (1) | CN101996143B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109658963B (en) * | 2017-10-11 | 2020-11-17 | 华邦电子股份有限公司 | Operation method of resistive memory storage device |
| CN108054912B (en) * | 2017-12-28 | 2020-01-17 | 深圳市华星光电半导体显示技术有限公司 | PMIC starting time sequence circuit and PMIC starting time sequence determining method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030062070A (en) * | 2002-01-16 | 2003-07-23 | 한국전자통신연구원 | Apparatus and method for controlling an access of a flash memory |
| CN1881135A (en) * | 2005-06-17 | 2006-12-20 | 鸿富锦精密工业（深圳）有限公司 | External reset switch and rest circuit |
| JP3998452B2 (en) * | 2001-10-19 | 2007-10-24 | 三洋電機株式会社 | Nonvolatile memory control circuit |
-
2009
- 2009-08-26 CN CN 200910171042 patent/CN101996143B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3998452B2 (en) * | 2001-10-19 | 2007-10-24 | 三洋電機株式会社 | Nonvolatile memory control circuit |
| KR20030062070A (en) * | 2002-01-16 | 2003-07-23 | 한국전자통신연구원 | Apparatus and method for controlling an access of a flash memory |
| CN1881135A (en) * | 2005-06-17 | 2006-12-20 | 鸿富锦精密工业（深圳）有限公司 | External reset switch and rest circuit |
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| CN101996143A (en) | 2011-03-30 |
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