CN114137881A - Chip awakening device, method and medium thereof - Google Patents
Chip awakening device, method and medium thereof Download PDFInfo
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- CN114137881A CN114137881A CN202111450321.8A CN202111450321A CN114137881A CN 114137881 A CN114137881 A CN 114137881A CN 202111450321 A CN202111450321 A CN 202111450321A CN 114137881 A CN114137881 A CN 114137881A
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- G—PHYSICS
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Abstract
The application discloses a chip awakening device, a method and a medium, which aims at the problem of GPIO resource waste caused by the fact that a latch is used for realizing multi-awakening source awakening of a chip at present, and provides the chip awakening device, which comprises: the device comprises a controller, an external wake-up source, a level holding circuit, a wake-up circuit and a detection circuit; the level holding circuit is connected with an external wake-up source and used for holding a level signal; the wake-up circuit is connected with the level holding circuits and the wake-up end of the controller, and a level signal input by an external wake-up source can be input to the wake-up end through the wake-up circuit to wake up the controller; the detection circuit is connected with the corresponding level holding circuit, the enabling end of the controller and the corresponding detection end, and is used for detecting when the controller is awakened and the enabling end is in a permitted state so as to determine an external awakening source of the awakening controller, so that the circuit can be controlled only by one enabling end, and GPIO resources of a chip are saved.
Description
Technical Field
The present disclosure relates to the field of wake-up of low power chips, and more particularly, to a device, a method and a medium for wake-up of a chip.
Background
At present, in the development of application products of the internet of things, there are multiple wake-up requirements, for example, multiple cases or multiple external interrupt triggers are used as external wake-up sources, but because there is only one General Purpose Input/Output (GPIO) port that can directly provide a wake-up function due to limited bottom resources of a low-power chip that needs to be used by the internet of things, and other GPIOs are connected to GPIOs that can directly wake up a chip, and indirectly provide a wake-up function, and the number of GPIOs is limited and is not enough to support too many external wake-up sources, at present, each external wake-up source is usually connected to a GPIO that can support a wake-up function, the state of the GPIO is stored by a latch, and the chip is woken up after being woken up, and then is processed to identify the chip that is woken up by that external wake-up source.
The prior latch commonly used saves the GPIO state so as to identify which external wake-up source wakes up the chip when the chip is woken up, thereby realizing the function of waking up the chip by multiple wake-up sources.
Therefore, those skilled in the art need a chip wake-up apparatus to solve the problem of GPIO resource waste caused by the current implementation of multiple external wake-up sources using latches.
Disclosure of Invention
The application aims to provide a chip awakening device, a chip awakening method and a chip awakening medium, and the problem of GPIO resource waste caused by the fact that a plurality of external awakening sources are awakened by using a latch at present is solved.
In order to solve the above technical problem, the present application provides a chip wake-up apparatus, including: the device comprises a controller, an external wake-up source, a level holding circuit, a wake-up circuit and a detection circuit; the level holding circuit is connected with the external awakening source and used for holding the level signal when the external awakening source inputs the level signal, wherein each external awakening source corresponds to one level holding circuit; the wake-up circuit is connected with the level holding circuits and the wake-up end of the controller, and when an external wake-up source inputs a level signal, the level signal is input to the wake-up end through the wake-up circuit to wake up the controller; the detection circuit is connected with the corresponding level holding circuit, the enabling end of the controller and the corresponding detection end, and is used for detecting to determine an external wake-up source for waking up the controller when the controller is awakened and the enabling end is in an allowable state.
Preferably, the external wake-up source is a key switch, and the level holding circuit includes: the circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a first transistor; the first end of the first resistor is connected with the positive electrode of the power supply and the first end of the first transistor, and the second end of the first resistor is connected with the first end of the first capacitor, the second end of the first transistor and the first end of the key switch; the second end of the first capacitor is connected with the second end of the key switch, the second end of the second capacitor and the second end of the third resistor, and is grounded; the first end of the second resistor is connected with the third end of the first transistor, and the second end of the second resistor is connected with the first end of the second capacitor and the first end of the third resistor.
Preferably, the wake-up circuit comprises: a fourth resistor, a third capacitor and a diode; the first end of the fourth resistor is connected with the positive electrode of the power supply, and the second end of the fourth resistor is connected with the first end of the third capacitor and the awakening end; the second end of the third capacitor is grounded; the key switches are connected with the awakening end through diodes, each key switch corresponds to one diode, the first end of each key switch is connected with the cathode of the corresponding diode, and the anode of each diode is connected with the awakening end.
Preferably, the detection circuit comprises: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second transistor, and a third transistor; a first end of a fifth resistor is connected with a first end of the second transistor and a first end of a third resistor in the level holding circuit, and a second end of the fifth resistor is connected with a second end of the second transistor and a first end of a sixth resistor; the second end of the sixth resistor is connected with the third end of the third transistor; the third end of the second transistor is connected with the first end of the seventh resistor; a second end of the seventh resistor is connected with a first end of the third transistor, a second end of the eighth resistor and a second end of the third resistor of the level holding circuit; a first end of the eighth resistor is connected with a second end of the third transistor and a second end of the ninth resistor; the first end of the ninth resistor is connected with the enable end.
Preferably, the first transistor is a field effect transistor.
Preferably, the second transistor and the third transistor are triodes.
In order to solve the above technical problem, the present application further provides a chip wake-up method, which is applied to the above chip wake-up apparatus, and includes: when receiving the wake-up signal, setting the enabling end to be in a blocking state; when detecting that the APP runs, setting the enabling end to be in an allowable state; and detecting through a detection circuit to determine the external awakening source.
In order to solve the above technical problem, the present application further provides a chip wake-up apparatus, including: the blocking module is used for setting the enabling end to be in a blocking state when the wake-up signal is received; the permission module is used for setting the enabling end into a permission state when the APP operation is detected; and the detection module is used for detecting through the detection circuit and determining the current external awakening source.
In order to solve the above technical problem, the present application further provides a chip wake-up apparatus, including: a memory for storing a computer program; the processor is used for implementing the steps of the chip wake-up method when executing the computer program.
In order to solve the above technical problem, the present application further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the chip wake-up method as described above.
The application provides a chip awakening device, realize the keeping of the level signal of outside source input of awakening up through holding circuit, after the chip is awakened up by awakening circuit, can detect the level signal that is kept through detection circuitry, because every outside source of awakening up and holding circuit, the sense terminal one-to-one of detection circuitry and controller, so the controller can detect out this outside source of awakening up, because control detection circuitry only needs an enable end, also only occupy a GPIO and be used for controlling external circuit, the GPIO resource of chip has been saved, make the GPIO who saves be used for more outside source detection of awakening up, make under the unchangeable condition of total GPIO resource of chip, can external more outside source of awakening up and realize the detection of outside source of awakening up.
The chip awakening method, the chip awakening device and the computer readable storage medium correspond to the device and have the same effects.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a structural diagram of a chip wake-up apparatus provided in the present invention;
FIG. 2 is a circuit diagram of a level hold circuit and a detection circuit provided in the present invention;
FIG. 3 is a circuit diagram of a wake-up circuit according to the present invention;
FIG. 4 is a block diagram of another wake-up apparatus for a chip according to the present invention;
fig. 5 is a structural diagram of another chip wake-up apparatus provided in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
The core of the application is to provide a chip awakening device, a chip awakening method and a chip awakening medium.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.
In the actual part of application scenes, the time for the chip to continuously work has higher requirements, so that the chip with lower power consumption needs to be selected, meanwhile, the chip also needs to be in a dormant state when not working, the power consumption is reduced to the maximum extent, and the chip can be awakened in time when needing to be controlled. The low power consumption chip meeting the above requirements usually has only one wake-up end due to the limitation of bottom resources, and only one external wake-up source 12 is connected to meet the multi-wake-up requirement, and when the external wake-up source 12 inputs a wake-up signal, it cannot be determined that the external wake-up source 12 wakes up, and also does not meet the multi-wake-up requirement, so at present, an external latch is usually used to store the level signal for wake-up input by the external wake-up source 12, and after the chip is woken up, the external wake-up source 12 of the chip can be known by detecting which GPIO of the external wake-up source 12 has the level signal. However, no matter what type and model of latch is used, besides the necessary connection at the only wake-up end of the chip, at least two GPIOs are needed to realize the control of the latch by the chip, which wastes the GPIO resource that is not abundant, so the application provides a chip wake-up device, as shown in fig. 1, including: a controller 11, an external wake-up source 12, a level holding circuit 13, a wake-up circuit 14 and a detection circuit 15;
the level holding circuit 13 is connected with the external wake-up source 12 and used for holding a level signal when the external wake-up source 12 inputs the level signal, wherein each external wake-up source 12 corresponds to one level holding circuit 13; the wake-up circuit 14 is connected to the level holding circuits 13 and the wake-up end of the controller 11, and when the external wake-up source 12 inputs a level signal, the level signal is input to the wake-up end through the wake-up circuit 14 to wake up the controller 11; the detection circuit 15 is connected to the corresponding level holding circuit 13 and the enable terminal of the controller 11 and the corresponding detection terminal, and is configured to perform detection to determine the external wake-up source 12 waking up the controller 11 when the enable terminal is in an enable state after the controller 11 is woken up.
It should be noted that, in the present application, there is no limitation on the type and number of the external wake-up sources 12, and the external wake-up sources 12 may be the key switch S1, or may be an external interrupt trigger, and may be one or more, but it should be noted that the external wake-up sources 12 correspond to the holding circuit and the detection end of the controller 11 one to one, so when determining the number of the external wake-up sources 12, it needs to be considered comprehensively in combination with the wake-up requirement of multiple wake-up sources and the number of other GPIOs of the controller 11 except the wake-up end.
To further illustrate how the chip wake-up apparatus provided in the present application performs the detection, the following examples are provided for a detailed description.
A low-power chip has 4 GPIOs, GPIO1, GPIO2, GPIO3 and GPIO4 respectively, wherein, the only GPIO with wake-up function is GPIO1, so the wake-up end in the above-mentioned device is GPIO 1; the enable terminal can be arbitrarily selected from the remaining three GPIOs, which is assumed to be GPIO2 in this example, so that the remaining GPIOs 3 and GPIOs 4 serve as two detection terminals and respectively correspond to the two external wake-up sources 12, the GPIO3 corresponds to the external wake-up source a, the GPIO4 corresponds to the external wake-up source B, and each external wake-up source 12 is connected to the GPIO through the independent level holding circuit 13 and the detection circuit 15; when one of the two external wake-up sources 12 inputs a level signal, the wake-up terminal receives the wake-up signal, the chip is woken up, the enable terminal is in a blocking state at this time, after the chip detects that an application program (APP) starts to run, the enable terminal is set to be in an allowing state, and the chip which is woken up by the external wake-up source a or the external wake-up source B can be known by detecting whether the GPIO3 or GPIO4 has a level signal input.
It will be readily appreciated that when it is desired to extend the external wake-up source 12, the holding circuit and detection circuit 15 may be added and may share a single wake-up circuit 14.
To further explain the chip wake-up apparatus provided in the present application, the present embodiment will explain a specific implementation form of the level holding circuit 13 in detail, as shown in fig. 2, the external wake-up source 12 is a key switch S1, and the level holding circuit 13 includes: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2 and a first transistor Q1;
a first end of the first resistor R1 is connected with a power supply positive electrode (VCC) and a first end of the first transistor Q1, and a second end of the first resistor R1 is connected with a first end of the first capacitor C1, a second end of the first transistor Q1 and a first end of the key switch S1; the second end of the first capacitor C1 is connected with the second end of the key switch S1, the second end of the second capacitor C2 and the second end of the third resistor R3, and is Grounded (GND); a first terminal of the second resistor R2 is connected to the third terminal of the first transistor Q1, and a second terminal of the second resistor R2 is connected to the first terminal of the second capacitor C2 and the first terminal of the third resistor R3.
It should be noted that the network KEY1 in fig. 2 is connected to the wake-up circuit 14, and the embodiment is not limited to the specific form of the first transistor Q1, which may be a fet, a thyristor or a transistor, but provides a preferred embodiment: the first transistor Q1 is a field effect transistor.
The advantage of the preferred first transistor Q1 being a field effect transistor is that: the field effect transistor has the advantages of small noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, wide safe working area and the like.
Correspondingly, when the first transistor Q1 is a fet, the first terminal of the first transistor Q1 is a source of the fet, the second terminal of the first transistor Q1 is a gate of the fet, and the third terminal of the first transistor Q1 is a drain of the fet.
It is easy to understand that the level holding circuit 13 provided in the present embodiment is only the level holding circuit 13 corresponding to one external wake-up source 12, and the level holding circuits 13 corresponding to other external wake-up sources 12 are not obviously different from those of the present embodiment, so that the detailed description thereof is omitted herein.
To further explain the chip wake-up apparatus provided in the present application, the embodiment further describes in detail a specific implementation form of the wake-up circuit 14, as shown in fig. 3, the wake-up circuit 14 includes: a fourth resistor R4, a third capacitor C3 and a diode;
a first end of the fourth resistor R4 is connected with the positive electrode of the power supply, and a second end of the fourth resistor R4 is connected with a first end and a wake-up end of the third capacitor C3; the second end of the third capacitor C3 is grounded; the key switches S1 are connected to the wake-up terminal through diodes, wherein each key switch S1 corresponds to a diode, the first terminal of the key switch S1 is connected to the cathode of the corresponding diode, and the anode of each diode is connected to the wake-up terminal.
It should be noted that, the network reference INT PIN in fig. 3 indicates connection with the wake-up terminal of the controller 11, the network reference KEY1 indicates connection with the above-mentioned level holding circuit 13, and the KEY2 indicates connection with another level holding circuit 13, the circuit diagram of the wake-up circuit 14 shown in fig. 3 is only externally connected with two level holding circuits 13, that is, the corresponding implementation background is two external wake-up sources 12, so that there are two corresponding diodes, namely the first diode D1 and the second diode D2, and if a new external wake-up source 12 needs to be additionally added, it is only necessary to extend the corresponding level holding circuit 13 and adopt the same connection relationship as above.
In addition, the embodiment also does not limit the specific form of the second transistor Q2, which may be a field effect transistor, a thyristor or a triode, but provides a preferred embodiment: the second transistor Q2 is a triode.
Correspondingly, when the second transistor Q2 is a triode, the first terminal of the second transistor Q2 is an emitter of the triode, the second terminal of the second transistor Q2 is a base of the triode, and the third terminal of the second transistor Q2 is a collector of the triode.
To further explain the chip wake-up apparatus provided in the present application, this embodiment further describes in detail a specific implementation form of the detection circuit 15, as shown in fig. 2, the detection circuit 15 includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a second transistor Q2 and a third transistor Q3;
a first end of the fifth resistor R5 is connected to a first end of the second transistor Q2 and a first end of a third resistor R3 in the level holding circuit 13, and a second end of the fifth resistor R5 is connected to a second end of the second transistor Q2 and a first end of a sixth resistor R6; a second end of the sixth resistor R6 is connected to a third end of the third transistor Q3; the third end of the second transistor Q2 is connected with the first end of a seventh resistor R7; a second terminal of the seventh resistor R7 is connected to the first terminal of the third transistor Q3, the second terminal of the eighth resistor R8, and the second terminal of the third resistor R3 of the level hold circuit 13; a first terminal of the eighth resistor R8 is connected to a second terminal of the third transistor Q3 and a second terminal of the ninth resistor R9; a first terminal of the ninth resistor R9 is connected to the enable terminal.
It should be noted that the network reference KEY1 PIN in fig. 2 indicates connection to the detection terminal corresponding to the detection circuit 15, and the network reference CTRL indicates connection to the enable terminal of the controller 11.
The advantage of the preferred second transistor Q2 and third transistor Q3 being triodes is that: the triode has high switching speed and low cost, and can improve the efficiency of the circuit.
Therefore, the chip awakening device provided by the application corresponds to one external awakening source 12 through each detection end, the level holding circuit 13 can hold the level signal input by the external awakening source 12, when the chip is awakened, the external awakening source 12 of the chip awakening this time can be judged by detecting whether the level signal exists at all the detection ends, and therefore awakening of the multiple external awakening sources 12 of the chip at the single awakening end is achieved, meanwhile, the control detection circuit 15 only needs one enabling end to control, so compared with a latch method used at present, GPIO resources of the chip are further saved, and on the premise that GPIO resources of the chip are limited, the chip is awakened by more external awakening sources 12.
In the above embodiment, a detailed description is given to a chip wake-up apparatus, and the present application further provides a chip wake-up method applied to the chip wake-up apparatus, including:
s101: when receiving the wake-up signal, the enabling terminal is set to be in a blocking state.
S102: when detecting the APP operation, the enabling end is set to be in an allowing state.
S103: the detection circuit 15 detects the external wake-up source 12, and determines the current time.
In an embedded operating system, when a chip is just woken up from a sleep mode, a boot loader (BootLoader) is required to initialize hardware devices and establish a memory space mapping map, so that the software and hardware environment of the system is brought to a proper state to prepare a correct environment for finally calling an operating system kernel, but because the level fluctuation exists during the boot loader, a certain influence is generated on circuits connected with the level fluctuation, so that when the chip is just woken up, an enable end is set to be a blocking state, circuits such as a detection circuit 15 and the like cannot be influenced by the BootLoader, and when the chip starts to run and is applied, the BootLoader is indicated to be finished, and the enable end is set to be an allowing state, so that the chip can determine an external wake-up source 12 for waking up the chip this time through the detection circuit 15.
The chip awakening method provided by the embodiment corresponds to the chip awakening device, and besides the beneficial effects corresponding to the device, the influence of level fluctuation generated when the chip is in a BootLoader state on a circuit can be avoided, and the stability and reliability of the chip awakening device are further improved.
Similarly, the present application also provides an embodiment of a chip wake-up apparatus corresponding to the above method. It should be noted that the present application describes the embodiments of the apparatus portion from two perspectives, one from the perspective of the function module and the other from the perspective of the hardware.
Based on the functional module, as shown in fig. 4, the present application provides a chip wake-up apparatus, including:
and the blocking module 21 is configured to set the enabling terminal to be in a blocking state when receiving the wake-up signal.
And an enabling module 22, configured to set the enabling terminal to an enabled state when detecting that the APP is running.
And the detection module 23 is configured to perform detection through the detection circuit 15 to determine the current external wake-up source 12.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
Fig. 5 is a structural diagram of a chip wake-up apparatus according to another embodiment of the present application, and as shown in fig. 5, the chip wake-up apparatus includes: a memory 30 for storing a computer program;
the processor 31 is configured to implement the steps of the chip wake-up method according to the above embodiment when executing the computer program.
The chip wake-up device provided by this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.
The processor 31 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 31 may be implemented in at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 31 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 31 may be integrated with a Graphics Processing Unit (GPU) which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 31 may further include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.
Memory 30 may include one or more computer-readable storage media, which may be non-transitory. Memory 30 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 30 is at least used for storing the following computer program 301, wherein after being loaded and executed by the processor 31, the computer program can implement the relevant steps of a chip wake-up method disclosed in any of the foregoing embodiments. In addition, the resources stored by the memory 30 may also include an operating system 302, data 303, and the like, and the storage may be transient storage or permanent storage. Operating system 302 may include Windows, Unix, Linux, etc. Data 303 may include, but is not limited to, a chip wake up method, etc.
In some embodiments, a chip wake-up apparatus may further include a display screen 32, an input/output interface 33, a communication interface 34, a power source 35, and a communication bus 36.
Those skilled in the art will appreciate that the configuration shown in fig. 5 is not intended to be limiting of a chip wake-up unit and may include more or fewer components than those shown.
The chip wake-up device provided by the embodiment of the application comprises a memory and a processor, wherein when the processor executes a program stored in the memory, the following method can be realized: a chip wake-up method.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps as set forth in the above-mentioned method embodiments.
It is to be understood that if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above detailed description is provided for a chip wake-up apparatus, method and medium thereof. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A chip wake-up apparatus, comprising: the device comprises a controller, an external wake-up source, a level holding circuit, a wake-up circuit and a detection circuit;
the level holding circuit is connected with the external wake-up sources and used for holding the level signals when the external wake-up sources input the level signals, wherein each external wake-up source corresponds to one level holding circuit; the wake-up circuit is connected with the level holding circuits and the wake-up end of the controller, and when the level signal is input by the external wake-up source, the level signal is input to the wake-up end through the wake-up circuit to wake up the controller; the detection circuit is connected with the corresponding level holding circuit, the enabling end of the controller and the corresponding detection end, and is used for detecting to confirm the external awakening source awakening the controller when the controller is awakened and the enabling end is in an allowable state.
2. The chip wake-up device according to claim 1, wherein the external wake-up source is a key switch, and the level holding circuit comprises: the circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a first transistor;
a first end of the first resistor is connected with a positive electrode of a power supply and a first end of the first transistor, and a second end of the first resistor is connected with a first end of the first capacitor, a second end of the first transistor and a first end of the key switch; the second end of the first capacitor is connected with the second end of the key switch, the second end of the second capacitor and the second end of the third resistor, and is grounded; and the first end of the second resistor is connected with the third end of the first transistor, and the second end of the second resistor is connected with the first end of the second capacitor and the first end of the third resistor.
3. The chip wake-up device according to claim 2, wherein the wake-up circuit comprises: a fourth resistor, a third capacitor and a diode;
the first end of the fourth resistor is connected with the positive electrode of a power supply, and the second end of the fourth resistor is connected with the first end of the third capacitor and the awakening end; the second end of the third capacitor is grounded; the key switches are connected with the awakening end through the diodes, each key switch corresponds to one diode, the first end of each key switch is connected with the cathode of the corresponding diode, and the anode of each diode is connected with the awakening end.
4. The chip wake-up device according to claim 3, wherein the detection circuit comprises: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second transistor, and a third transistor;
a first end of the fifth resistor is connected with a first end of the second transistor and a first end of the third resistor in the level holding circuit, and a second end of the fifth resistor is connected with a second end of the second transistor and a first end of the sixth resistor; a second end of the sixth resistor is connected with a third end of the third transistor; the third end of the second transistor is connected with the first end of the seventh resistor; a second terminal of the seventh resistor is connected to a first terminal of the third transistor, a second terminal of the eighth resistor, and a second terminal of the third resistor of the level hold circuit; a first end of the eighth resistor is connected with a second end of the third transistor and a second end of the ninth resistor; and the first end of the ninth resistor is connected with the enabling end.
5. The chip wake-up device according to claim 2, wherein the first transistor is a field effect transistor.
6. The chip wake-up device according to claim 4, wherein the second transistor and the third transistor are triodes.
7. A chip wake-up method applied to the chip wake-up device of any one of claims 1 to 6, comprising:
when receiving the wake-up signal, setting the enabling end to be in a blocking state;
when detecting that the APP runs, setting the enabling end to be in an allowable state;
and detecting through a detection circuit to determine the external awakening source.
8. A chip wake-up apparatus, comprising:
the blocking module is used for setting the enabling end to be in a blocking state when the wake-up signal is received;
the permission module is used for setting the enabling end to be in a permission state when the APP operation is detected;
and the detection module is used for detecting through the detection circuit and determining the current external awakening source.
9. A chip wake-up apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the chip wake-up method as claimed in claim 7 when executing said computer program.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the chip wake-up method as claimed in claim 7.
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| CN115459784A (en) * | 2022-10-18 | 2022-12-09 | 广芯微电子(苏州)有限公司 | Key awakening circuit and electronic equipment |
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