CN101989847A - Numerical value judging device - Google Patents
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- CN101989847A CN101989847A CN2009101655194A CN200910165519A CN101989847A CN 101989847 A CN101989847 A CN 101989847A CN 2009101655194 A CN2009101655194 A CN 2009101655194A CN 200910165519 A CN200910165519 A CN 200910165519A CN 101989847 A CN101989847 A CN 101989847A
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Abstract
The invention discloses a numerical value judging device, which is used for judging a value of a specific order in a plurality of numerical values. The numerical value judging device comprises a plurality of receiving ends, a plurality of multiplexing modules, a comparison module, a decoding module, a driving module and an output unit, wherein the plurality of multiplexing modules are used for outputting a numerical value received by a receiving end or a preset value according to a decoding result respectively; the comparison module is used for comparing output signals of the plurality of multiplexing modules so as to generate a plurality of comparison results, and judging an extreme value; the decoding module is used for generating plurality of decoding results according to the plurality of comparison results; the driving module is used for controlling the plurality of multiplexing modules, the comparison module and the decoding module to operate for preset times according to the specific order, wherein the preset times corresponds to the specific order; and the output unit is used for outputting the judged extreme value after the comparison module operates for the preset times so as to judge the value of the specific order.
Description
Technical field
The present invention relates to a kind of numerical value judgment means, relate in particular to a kind of any numerical value judgment means in a plurality of numerical value of judging with particular value of cis-position implication.
Background technology
Median filter (Median Filter) is a kind of electronic component that is usually used in data processing, in order to judge the median of a sequence numerical value.In known technology, the implementation of median filter gets by comparison operation and logical operation, and its complexity increases along with the quantity of this sequence numerical value.
For instance, please refer to Fig. 1, Fig. 1 is the schematic diagram of a known median filter 10.Median filter 10 is 7 median filter for number of samples, and it can be by judging median VL_med among numerical value VL_1～VL_7.Median filter 10 mainly is made up of a comparison module 100, a logic module 102 and a multiplex module 104.Comparison module 100 includes 21 comparator C MP, and each comparator C MP is used for the numerical value at comparison "+", "-" two ends.If the value of "+" end more than or equal to the value of "-" end, is then exported " 1 " (or high level square wave); Otherwise, then export " 0 " (or low level square wave).Logic module 102 includes logical block LGC_2～LGC_7, corresponds respectively to numerical value VL_2～VL_7.Each logical block comprises 6 inputs and 1 output, and also comprises inverter before the part input, is used for the signal counter-rotating, with the magnitude relationship of the corresponding numerical value of correct judgement.Because the median among numerical value VL_1～VL_7 must be simultaneously greater than (or equaling) 3 numerical value and less than 3 numerical value, therefore logical block LGC_2～LGC_7 is 1 o'clock in 3 input signals, output " 1 ", otherwise whether output " 0 " is median VL_med to judge corresponding numerical value.Multiplex module 104 includes multiplexer MUX_2～MUX_7, and each multiplexer comprises input I1, I2, is used for when the counterlogic unit is output as " 1 ", selects the signal of I/O I2.For example, if logical block LGC_2 is output as " 1 ", then multiplexer MUX_2 can select to export the signal of its input I2.
Therefore, by comparison module 100, logic module 102 and multiplex module 104, median filter 10 can be judged the median VL_med among numerical value VL_1～VL_7.Yet as shown in Figure 1, the comparator C MP number in the comparison module 100 is relevant with number of samples.Suppose that number of samples is n, then the number NM of comparator C MP is:
Hence one can see that, and number NM and number of samples n square are directly proportional, in other words, required cost also with square being directly proportional of number of samples n.Except the cost problem, another shortcoming of median filter 10 is that median filter 10 only can be used for judging median, and can't judge the numerical value of a certain size, as the third-largest or the 3rd little.
Therefore, at the cost problem of known median filter and the restriction of range of application thereof, improved necessity is arranged in fact.
Summary of the invention
Therefore, main purpose of the present invention promptly is to provide a kind of numerical value judgment means.
The present invention discloses a kind of numerical value judgment means, is used for judging the value of a specific cis-position in a plurality of numerical value, and this numerical value judgment means includes a plurality of receiving terminals, is used for receiving these a plurality of numerical value; A plurality of multiplex module, each multiplex module are coupled to a receiving terminal of these a plurality of receiving terminals, are used for a decoded result according to a plurality of decoded results, export a numerical value or a preset value that this receiving terminal receives; One comparison module is coupled to this a plurality of multiplex module, is used for relatively a plurality of output signals of these a plurality of multiplex module, producing a plurality of comparative results, and judges an extreme value of these a plurality of output signals; One decoder module is coupled between this comparison module and this a plurality of multiplex module, is used for producing this a plurality of decoded results according to these a plurality of comparative results; One driver module, be coupled to these a plurality of multiplex module, this comparison module and this decoder module, be used for controlling these a plurality of multiplex module, this comparison module and this decoder module and operating a preset times according to this specific cis-position, this preset times is corresponding to this specific cis-position; And an output unit, be coupled to this comparison module and this driver module, be used for exporting this comparison module and operate this extreme value of being judged after this preset times, to judge the value of this specific cis-position.
Description of drawings
Fig. 1 is the schematic diagram of a known median filter.
Fig. 2 is the schematic diagram of the embodiment of the invention one numerical value judgment means.
Fig. 3 A is the embodiment schematic diagram of a multiplex module among Fig. 2.
Fig. 3 B is the embodiment schematic diagram of a multiplex module among Fig. 2.
Fig. 3 C is the embodiment schematic diagram of a multiplex module among Fig. 2.
Fig. 4 A is the embodiment schematic diagram of a comparison module among Fig. 2.
Fig. 4 B is the schematic diagram of a comparing unit among Fig. 4 A.
The embodiment schematic diagram of Fig. 4 C comparison module when number of samples is 7.
Fig. 5 A is the embodiment schematic diagram of a decoder module among Fig. 2.
The embodiment schematic diagram of Fig. 5 B decoder module when number of samples is 7.
[main element symbol description]
10 median filters
100 comparison modules
102 logic modules
104 multiplex module
VL_1～VL_7 numerical value
The VL_med median
The CMP comparator
LGC_2～LGC_7 logical block
MUX_2～MUX_7 multiplexer
I1, I2 input
20 numerical value judgment means
A (1)～A (n) numerical value
R (1)～R (n) receiving terminal
The d0 preset value
Y (1)～y (n) decoded result
B (1)～B (n) output signal
The Bm extreme value
X (1)～X (n-1) comparative result
MUX_M (1)～MUX_M (n) multiplex module
200 comparison modules
202 decoder modules
204 driver modules
206 output units
A_exp numerical value
MUX_M (x) multiplex module
A (x) numerical value
R (x) receiving terminal
Y (x), Y (y), Y (z) decoded result
B (x), B (y), B (z) output signal
S (x), S (y), S (z) memory cell
MUX1_ (x) first multiplexer
MUX2_ (x) second multiplexer
MUX (y), MUX (z) multiplexer
INV (y), INV (z) inverter
Am (y) amplifier
LA (y) level adjustment unit
NOR (z) NOR gate
CTRL_1 first control signal
CTRL_2 second control signal
CMP (1)～CMP (n-1) comparing unit
M (1)～M (f) submodule
IN1 (x), IN2 (x) receiving terminal
CU (x) comparator
MUX_CMP (x) multiplexer
OUT (x) output
AND (1)～AND (n) and door
Embodiment
With regard to numerical value comparatively speaking, include in the ordered series of numbers of a plurality of numerical value one, if arrange from large to small, then the numerical value of first cis-position is the maximum in all numerical value, the numerical value of second cis-position is the maximum except that the numerical value of first cis-position, by that analogy, the numerical value of m cis-position is the maximum except that the numerical value of first cis-position to the (m-1) cis-position.In other words, if judge the numerical value of m cis-position, can repeat the maximum deterministic process, that is judge earlier and have a peaked numerical value (i.e. first cis-position) in the ordered series of numbers, this numerical value is replaced with a minimum value, judge to have peaked another numerical value (i.e. second cis-position) this moment again, repeat the numerical value that this process can hunt out the m cis-position.Above-mentioned explanation is that the cis-position with from large to small the time is an example, otherwise for also can same concept judging by little cis-position when big.
From the above, in will judging an ordered series of numbers, during the numerical value of specific cis-position, can obtain the numerical value of this specific cis-position by the extreme value deterministic process that repeats.Notion according to this, any particular value with cis-position implication as median, all can be searched in this way.In this case, the invention provides a numerical value judgment means, in order to realize this notion.
Please refer to Fig. 2, Fig. 2 is the schematic diagram of the embodiment of the invention one numerical value judgment means 20.Numerical value judgment means 20 is used for judging the numerical value A_exp of a specific cis-position among numerical value A (1)～A (n), and it includes receiving terminal R (1)～R (n), multiplex module MUX_M (1)～MUX_M (n), a comparison module 200, a decoder module 202, a driver module 204 and an output unit 206.Driver module 204 is controlled the running number of times of each element according to required cis-position.At first, multiplex module MUX_M (1)～MUX_M (n) is by receiving terminal R (1)～R (n), receive numerical value A (1)～A (n), and decoded result Y (the 1)～Y (n) that is exported according to decoder module 202, the numerical value or the preset value d0 that select output to be received are to produce output signal B (1)～B (n) and to export comparison module 200 to.Comparison module 200 can compare the size of output signal B (1)～B (n), with generation comparative result X (1)～X (n-1), and the extreme value Bm among judgement output signal B (1)～B (n).Decoder module 202 is used for according to comparative result X (1)～X (n-1), produces decoded result Y (1)～Y (n) and exports multiplex module MUX_M (1)～MUX_M (n) to.Wherein, each decoded result is used to refer to whether corresponding its output signal that is produced of multiplex module is extreme value Bm; If then next operates circulation time, multiplex module will replace output signal originally with preset value d0, be described in detail as follows.
At first, when opening when running beginning, arbitrary multiplex module MUX_M (x) is sent to comparison module 200 with numerical value A (x), i.e. B (x)=A (x).If output signal B (x) is the extreme value among output signal B (1)～B (n), then decoder module 202 can be according to comparative result X (1)～X (n-1), judge that output signal B (x) is an extreme value, and the decoded result Y (x) of correspondence is made as a particular value, expression numerical value A (x) is first cis-position among numerical value A (1)～A (n).Then, at next running circulation time, multiplex module MUX_M (x) can judge that numerical value A (x) is the extreme value of numerical value A (1)～A (n), and preset value d0 is sent to comparison module 200, be i.e. B (x)=d0 according to decoded result Y (x).In this case, because output signal B (x) is set to d0, make comparison module 200 can compare the numerical value of second cis-position.By that analogy,, repeat the deterministic process of extreme value, can judge required numerical value A_exp according to required cis-position.
Be noted that preset value d0 should cooperate the arrangement mode of required cis-position and set, similarly, aforesaid extreme value (as Bm) also should cooperate the arrangement mode of required cis-position and be set at very big or minimum.That is to say that a cis-position that if numerical value A_exp is numerical value A (1)～A (n) under arranging from large to small, then preset value d0 should be set at the minimum value in the probable value of numerical value A (1)～A (n), and extreme value Bm should be set at maximum; Simultaneously, after a running, can draw required result.Otherwise if numerical value A_exp is numerical value A (1)～A (n) by little b cis-position to big the arrangement, then preset value d0 should be set at the maximum in the probable value of numerical value A (1)～A (n), and extreme value Bm should be set at minimum value; In this case, after b running, can draw required result.
Numerical value judgment means 20 shown in Figure 2 is one embodiment of the invention, and those skilled in the art to utilize the extreme value deterministic process that repeats, obtain the numerical value of specific cis-position when doing different modifications according to this.For instance, please refer to Fig. 3 A, Fig. 3 A is the embodiment schematic diagram of arbitrary multiplex module MUX_M (x) among Fig. 2.As shown in Figure 3A, multiplex module MUX_M (x) includes a memory cell S (x), one first multiplexer MUX1_ (x) and one second multiplexer MUX2_ (x).Memory cell S (x) is used for storing one first multiplex output signals that the first multiplexer MUX1_ (x) is exported, and, export first multiplex output signals to comparison module 200 and the second multiplexer MUX2_ (x) according to the one first control signal CTRL_1 that driver module 204 is exported.The first multiplexer MUX1_ (x) can be according to the driver module 204 one second control signal CTRL_2 that exports, and one second multiplex output signals that the selection output numerical value A (x) or the second multiplexer MUX2_ (x) are exported is to memory cell S (x).The second multiplexer MUX2_ (x) selects to export signal or preset value d0 to the first multiplexer MUX1_ (x) that memory cell S (x) is stored then according to decoded result Y (x).Wherein, the first control signal CTRL_1 is relevant to the running circulation of numerical value judgment means 20, and promptly it is used for the data that control store cell S (x) output is in good time stored; And the second control signal CTRL_2 whether be used to refer to be initial startup, give memory cell S (x) with correct generation first multiplex output signals.In simple terms, when numerical value judgment means 20 was initial startup, the second control signal CTRL_2 equaled a particular value (as 1), made the first multiplexer MUX1_ (x) select output numerical value A (x) to give memory cell S (x).When numerical value judgment means 20 non-initial startup, the second multiplexer MUX2_ (x) can select the output signal B (x) or output preset value d0 to the first multiplexer MUX1_ (x) of the last running circulation of output according to decoded result Y (x); At this moment, the second control signal CTRL_2 equals another particular value (as 0), makes the first multiplexer MUX1_ (x) select that the output second multiplexer MUX2_'s (x) output signal to memory cell S (x).
In simple terms, by the multiplex module MUX_M (x) shown in Fig. 3 A, if the cis-position of the leading numerical value A_exp of the cis-position of numerical value A (x), then before judging numerical value A_exp, output signal B (x) can be substituted by preset value d0; Otherwise if the cis-position of numerical value A (x) falls behind the cis-position of numerical value A_exp, then output signal B (x) equals numerical value A (x) all the time.Because multiplex module MUX_M (1)～MUX_M (n) replaces the extreme value of last running circulation with preset value d0, therefore as long as according to required cis-position, operate suitable period after, can judge numerical value A_exp.
On the other hand, please refer to Fig. 3 B, Fig. 3 B is the embodiment schematic diagram of arbitrary multiplex module MUX_M (y) among Fig. 2.Shown in Fig. 3 B, multiplex module MUX_M (y) includes a memory cell S (y), a multiplexer MUX (y), an amplifier Am (y), an inverter INV (y) and a level adjustment unit LA (y).Inverter INV (y) is coupled to decoder module 202, is used for producing the anti-phase result of decoded result Y (y) to amplifier Am (y).Amplifier Am (y) preferably is a unity gain amplifier, can be according to the anti-phase result of decoded result Y (y), and whether control is sent to multiplexer MUX (y) with output signal B (y).Level adjustment unit LA (y) is used for amplifier Am (y) when decommissioning, and adjusts signal level (drag down or draw high), to multiplexer MUX (y), avoids the output of amplifier Am (y) to be in floating with output preset value d0.Multiplexer MUX (y) can be according to the driver module 204 second control signal CTRL_2 that exports, and that selects output numerical value A (y) or amplifier Am (y) and level adjustment unit LA (y) outputs signal to memory cell S (y).Memory cell S (y) is used for storing the multiplex output signals that multiplexer MUX (y) is exported, and according to the first control signal CTRL_1 that driver module 204 is exported, exports multiplex output signals to comparison module 200 and amplifier Am (y).In simple terms, when numerical value judgment means 20 was initial startup, the second control signal CTRL_2 equaled a particular value (as 1), made multiplexer MUX (y) select output numerical value A (y) to give memory cell S (y).When numerical value judgment means 20 non-initial startup, the second control signal CTRL_2 equals another particular value (as 0), and the output signal B (y) that makes the last running circulation of multiplexer MUX (y) output is to memory cell S (y).In this case, if output signal B (y) is the extreme value of last circulation, then according to decoded result Y (y), at next circulation time, amplifier Am (y) can decommission, and the result of output level adjustment unit LA (y), i.e. preset value d0.
Be noted that in Fig. 3 B, level adjustment unit LA (y) should cooperate the arrangement mode of required cis-position and set signal level is drawn high or dragged down, that is preset value d0 should cooperate the arrangement mode of required cis-position and sets.That is to say, the a cis-position that if numerical value A_exp is numerical value A (1)～A (n) under arranging from large to small, then preset value d0 should be set at the minimum value in the probable value of numerical value A (1)～A (n), and promptly level adjustment unit LA (y) drags down signal level, and extreme value Bm should be set at maximum; Simultaneously, after a running, can draw required result.Otherwise, if numerical value A_exp is that numerical value A (1)～A (n) is by little b cis-position to big the arrangement, then preset value d0 should be set at the maximum in the probable value of numerical value A (1)～A (n), and promptly level adjustment unit LA (y) draws high signal level, and extreme value Bm should be set at minimum value; In this case, after b running, can draw required result.
In simple terms, by the multiplex module MUX_M (y) shown in Fig. 3 B, if the cis-position of the leading numerical value A_exp of the cis-position of numerical value A (y), then before judging numerical value A_exp, output signal B (y) can be substituted by preset value d0; Otherwise if the cis-position of numerical value A (y) falls behind the cis-position of numerical value A_exp, then output signal B (y) equals numerical value A (y) all the time.Because multiplex module MUX_M (1)～MUX_M (n) replaces the extreme value of last running circulation with preset value d0, therefore as long as according to required cis-position, operate suitable period after, can judge numerical value A_exp.
In addition, the mode that produces preset value d0 is not limited to the example of Fig. 3 A or Fig. 3 B, also can produce by the logical operation mode.For instance, please refer to Fig. 3 C, Fig. 3 C is the embodiment schematic diagram of arbitrary multiplex module MUX_M (z) among Fig. 2.Shown in Fig. 3 C, multiplex module MUX_M (z) includes a memory cell S (z), a multiplexer MUX (z), an inverter INV (z) and a NOR gate NOR (z).Memory cell S (y) and multiplexer MUX (y) are identical among the function mode of memory cell S (z) and multiplexer MUX (z) and Fig. 3 B, so do not give unnecessary details.Inverter INV (y) is coupled to memory cell S (z), is used for producing the anti-phase result of output signal B (z) to NOR gate NOR (z).NOR gate NOR (z) is used for the anti-phase result of output signal B (z) and decoded result Y (z) are carried out the NOR gate computing, and exports operation result to multiplexer MUX (z).As is known to the person skilled in the art, in the NOR gate computing, arbitrary input signal is 1 o'clock, operation result must be 0, therefore, if output signal B (z) is the extreme value of last circulation, then according to decoded result Y (z), at next circulation time, the operation result of NOR gate NOR (z) must be 0, i.e. preset value d0.
Certainly, in Fig. 3 C, NOR gate NOR (z) only is an example, and those skilled in the art are when setting correct logical operation according to the arrangement mode of required cis-position.
Further, please refer to Fig. 4 A, Fig. 4 A is an embodiment schematic diagram of comparison module 200 among Fig. 2.Comparison module 200 is made up of comparing unit CMP (1)～CMP (n-1), can be further divided into submodule M (the 1)～M (f) of f level.Please also refer to Fig. 4 B, Fig. 4 B is the schematic diagram of arbitrary comparing unit CMP (x) among Fig. 4 A.Comparing unit CMP (x) includes a comparator C U (x) and a multiplexer MUX_CMP (x), it can pass through the output signal that receiving terminal IN1 (x), IN2 (x) receive previous stage, after the comparison of comparator C U (x), output comparative result X (x) is to decoder module 202 and multiplexer MUX_CMP (x).Simultaneously, multiplexer MUX_CMP (x) selects the signal of output receiving terminal IN1 (x) or IN2 (x) according to comparative result X (x), and exports next stage to by an output OUT (x).Be noted that the comparing unit CMP (x) of Fig. 4 B is in order to show the content of arbitrary comparing unit, its connected mode should be decided on place submodule and related setting.For example, comparing unit CMP (x) is arranged in submodule M (1), and then receiving terminal IN1 (x), IN2 (x) should be coupled to two multiplex module among multiplex module MUX_M (1)～MUX_M (n), and output OUT (x) should be coupled to the comparing unit of next stage.In addition, the progression f of submodule M (1)～M (f) system decides in response to the quantity n of numerical value A (1)～A (n).That is to say that if by relatively judging n the maximum in the numerical value in twos, then f should meet following formula:
2
f≥n，
After getting log, can get
log2
f≥log?n，
f≥log
2n。
Be noted that the example shown in Fig. 4 A and Fig. 4 B is in order to the embodiment of explanation comparison module 200.Those skilled in the art work as can do different modifications according to this, and is not limited thereto, and the input of particularly arbitrary comparing unit CMP (x) and output connected mode should cooperate the quantity n of numerical value A (1)～A (n) and decide.For instance, when n=7, the comparison module of realizing with Fig. 4 A and Fig. 4 B 200 is promptly shown in Fig. 4 C.In addition, the Compare Logic of arbitrary comparing unit CMP (x) also should cooperate the arrangement mode of required cis-position and set.For example, if a certain cis-position that numerical value A_exp is numerical value A (1)～A (n) under arranging from large to small, then the comparative result X (1) of comparing unit CMP (1) shows that whether output signal B (1) is greater than output signal B (2); Otherwise if numerical value A_exp is numerical value A (1)～A (n) by little to the big a certain cis-position down of arranging, then the comparative result X (1) of comparing unit CMP (1) is whether demonstration output signal B (2) is greater than output signal B (1).
On the other hand, decoder module 202 also should cooperate the design of comparison module 200 and decide.For instance, please refer to Fig. 5 A, Fig. 5 A is an embodiment schematic diagram of decoder module 202.In Fig. 5 A, decoder module 202 is by being formed with door AND (1)～AND (n), and including inverter before part and door input.Specifically, whether arbitrary and door are the maximum in the running circulation corresponding to a numerical value in order to judge this numerical value.Please also refer to Fig. 4 A and Fig. 5 A as can be known, with door AND (1) be example, its input signal be comparative result X (1), X (s+1) ..., X (n-1), all promptly relevant comparative results with output signal B (1).When all comparative results relevant with output signal B (1) are all 1, be illustrated in this running circulation, output signal B (1) is a maximum.In this case, accordingly, with the decoded result Y (1) of door AND (1) also be 1, then multiplex module MUX_M (1) according to this (at next running circulation time) judge that numerical value A (1) is maximum in this running circulation.In addition, for for door AND (2), because comparative result X (1) represents that output signal B (1) whether greater than output signal B (2), therefore needs through anti-phase processing, relevant way should be well known to those skilled in the art.
Fig. 5 A is to realize decoder module 202 with door, and in fact, those skilled in the art also can adopt other logical block, with according to all comparative results corresponding to an output signal, judge whether it is extreme value.Simultaneously, should cooperate decoder module 202 with the input of door AND (1)～AND (n) and output connected mode and decide.For instance, when n=7, and cooperate the comparison module 200 shown in Fig. 4 C, then the implementation of decoder module 202 is shown in Fig. 5 B.
Running by multiplex module MUX_M (1)～MUX_M (n), comparison module 200 and decoder module 202, the present invention can judge the extreme value Bm of each running circulation, and output unit 206 preferably can be kept in the extreme value Bm of each running circulation, driver module 204 is then according to required cis-position, be in due course, control output unit 206 output extreme value Bm, this is required numerical value A_exp.That is to say that driver module 204 is controlled the running number of times of multiplex module MUX_M (1)～MUX_M (n), comparison module 200 and decoder module 202 according to required cis-position.After reaching the running number of times that sets, then control output unit 206 output extreme value Bm, promptly judge required numerical value A_exp.
By repeating the extreme value deterministic process, numerical value judgment means 20 can be judged the value of any specific cis-position, the more important thing is, shown in Fig. 4 A, numerical value judgment means 20 required number of comparators are directly proportional with the first power of n, can reduce cost.Therefore, the comparison module 200 of the known technology of comparison diagram 1 and Fig. 4 C as can be known, when number of samples was all 7, the required comparator number of known technology and n square were directly proportional, the present invention then is directly proportional with the first power of n.Apparently, single with regard to obtaining median, the present invention can effectively reduce required cost, the more important thing is, the invention is not restricted to judge median, also can be used for judging any particular value with cis-position implication.
In sum, by the extreme value deterministic process that repeats, the present invention can judge any particular value with cis-position implication in a plurality of numerical value, and required cost is lower.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (31)
1. numerical value judgment means is used for judging the value of a specific cis-position in a plurality of numerical value, and this numerical value judgment means includes:
A plurality of receiving terminals are used for receiving these a plurality of numerical value;
A plurality of multiplex module, each multiplex module are coupled to a receiving terminal of these a plurality of receiving terminals, are used for a decoded result according to a plurality of decoded results, export a numerical value or a preset value that this receiving terminal receives;
One comparison module is coupled to this a plurality of multiplex module, is used for relatively a plurality of output signals of these a plurality of multiplex module, producing a plurality of comparative results, and judges an extreme value of these a plurality of output signals;
One decoder module is coupled between this comparison module and this a plurality of multiplex module, is used for producing this a plurality of decoded results according to these a plurality of comparative results;
One driver module, be coupled to these a plurality of multiplex module, this comparison module and this decoder module, be used for controlling these a plurality of multiplex module, this comparison module and this decoder module and operating a preset times according to this specific cis-position, this preset times is corresponding to this specific cis-position; And
One output unit is coupled to this comparison module and this driver module, is used for exporting this comparison module and operates this extreme value of being judged after this preset times, to judge the value of this specific cis-position.
2. numerical value judgment means as claimed in claim 1, wherein each multiplex module of these a plurality of multiplex module is exported this preset value when the decoded result of a correspondence shows that an output signal of being exported is this extreme value of these a plurality of output signals.
3. numerical value judgment means as claimed in claim 1, wherein each multiplex module of these a plurality of multiplex module includes:
One memory cell is used for storing one first multiplex output signals, and according to one first control signal, exports this first multiplex output signals to this comparison module;
One first multiplexer is used for receiving the numerical value and one second multiplex output signals of this sequence numerical value, and according to one second control signal, selects this numerical value of output or this second multiplex output signals, to export this first multiplex output signals to this memory cell; And
One second multiplexer, be used for receiving this first multiplex output signals and this preset value that this memory cell is exported, and, select this first multiplex output signals of output or this preset value, to export this second multiplex output signals to this first multiplexer according to a decoded result of these a plurality of decoded results.
4. numerical value judgment means as claimed in claim 3, wherein this driver module also is used for exporting this first control signal and this second control signal, operates this preset times to control each multiplex module.
5. numerical value judgment means as claimed in claim 3, wherein this first multiplexer is selected this numerical value of output, to export this first multiplex output signals to this memory cell when this secondary signal of this driver module indicates this numerical value judgment means to be initial operation.
6. numerical value judgment means as claimed in claim 3, wherein this first multiplexer is when this secondary signal of this driver module indicates this numerical value judgment means to be non-initial operation, select this second multiplex output signals of output, to export this first multiplex output signals to this memory cell.
7. numerical value judgment means as claimed in claim 3, wherein this second multiplexer is when this decoded result shows this memory cell this extreme value that to export this first multiplex output signals of this comparison module to be these a plurality of output signals, select this preset value of output, to export this second multiplex output signals to this first multiplexer.
8. numerical value judgment means as claimed in claim 3, wherein this second multiplexer is when this decoded result shows that this memory cell exports this extreme value of non-these a plurality of output signals of this first multiplex output signals of this comparison module to, select this first multiplex output signals of output, to export this second multiplex output signals to this first multiplexer.
9. numerical value judgment means as claimed in claim 1, wherein each multiplex module of these a plurality of multiplex module includes:
One amplifier is used for anti-phase result according to a decoded result of this a plurality of decoded results, exports a multiplex output signals, to produce an amplification result;
One level adjustment unit is used for adjusting this amplification result's level;
One memory cell is used for storing this multiplex output signals, and according to one first control signal, exports this multiplex output signals to this comparison module and this amplifier; And
One multiplexer is used for receiving a numerical value and this amplification result of this sequence numerical value, and according to one second control signal, selects this numerical value of output maybe should amplify the result, to export this multiplex output signals to this memory cell.
10. numerical value judgment means as claimed in claim 9, wherein this amplifier is a unity gain amplifier.
11. numerical value judgment means as claimed in claim 9, wherein this amplifier is when this decoded result shows this memory cell this extreme value that to export this multiplex output signals of this comparison module to be these a plurality of output signals, stop to export this multiplex output signals, to produce this amplification result.
12. numerical value judgment means as claimed in claim 11, wherein when this extreme value was a maximum, the level that this level adjustment unit will amplify the result was turned down and is this preset value.
13. numerical value judgment means as claimed in claim 11, wherein when this extreme value was a minimum value, the level that this level adjustment unit will amplify the result was heightened and is this preset value.
14. numerical value judgment means as claimed in claim 9, wherein this driver module also is used for exporting this first control signal and this second control signal, operates this preset times to control each multiplex module.
15. numerical value judgment means as claimed in claim 9, wherein this multiplexer is selected this numerical value of output, to export this multiplex output signals to this memory cell when this secondary signal of this driver module indicates this numerical value judgment means to be initial operation.
16. numerical value judgment means as claimed in claim 9, wherein this multiplexer is when this secondary signal of this driver module indicates this numerical value judgment means to be non-initial operation, and this amplifies the result to select output, to export this multiplex output signals to this memory cell.
17. numerical value judgment means as claimed in claim 9, it also comprises an inverter, is used for producing the anti-phase result of this decoded result.
18. numerical value judgment means as claimed in claim 1, wherein each multiplex module of these a plurality of multiplex module includes:
One memory cell is used for storing a multiplex output signals, and according to one first control signal, exports this multiplex output signals to this comparison module;
One multiplexer is used for receiving the numerical value and a NOR gate operation result of this sequence numerical value, and according to one second control signal, selects this numerical value of output or this NOR gate operation result, to export this multiplex output signals to this memory cell;
One inverter is used for producing the anti-phase result of this multiplex output signals; And
One NOR gate is used for the anti-phase result of this multiplex output signals and a decoded result of these a plurality of decoded results are carried out a NOR gate computing, gives this multiplexer to produce this NOR gate operation result.
19. numerical value judgment means as claimed in claim 18, wherein this driver module also is used for exporting this first control signal and this second control signal, operates this preset times to control each multiplex module.
20. numerical value judgment means as claimed in claim 18, wherein this multiplexer is selected this numerical value of output, to export this multiplex output signals to this memory cell when this secondary signal of this driver module indicates this numerical value judgment means to be initial operation.
21. numerical value judgment means as claimed in claim 18, wherein this multiplexer is when this secondary signal of this driver module indicates this numerical value judgment means to be non-initial operation, select this NOR gate operation result of output, to export this multiplex output signals to this memory cell.
22. numerical value judgment means as claimed in claim 1, wherein this comparison module includes a plurality of grades of submodules, is serially connected with a sequence, and each grade submodule comprises at least one comparing unit, be used for the size of two output signals in the output signal of comparison previous stage, to export a comparative result.
23. numerical value judgment means as claimed in claim 22, wherein the previous stage submodule of these a plurality of grades of submodules is coupled to this a plurality of multiplex module, the afterbody submodule is coupled to this output unit, is used for exporting this extreme value of these a plurality of output signals of these a plurality of multiplex module.
24. numerical value judgment means as claimed in claim 22, wherein a comparing unit of this at least one comparing unit includes:
One comparator is used for the size of one first output signal and one second output signal in the output signal of comparison previous stage, to export a comparative result; And
One multiplexer is used for according to this comparative result, selects this first output signal of output or this second to output signal to the next stage submodule.
25. numerical value judgment means as claimed in claim 1, wherein this decoder module comprises a plurality of logical blocks, correspond respectively to this a plurality of numerical value, each logical block be used for according in these a plurality of comparative results corresponding to the comparative result of a numerical value, whether generation is corresponding to a decoded result of this numerical value, be extreme value in these a plurality of numerical value to indicate this numerical value.
26. numerical value judgment means as claimed in claim 1, wherein this specific cis-position is the cis-position after these a plurality of numerical value are arranged from large to small.
27. numerical value judgment means as claimed in claim 26, wherein this extreme value is a maximum, and this preset times equals this specific cis-position.
28. numerical value judgment means as claimed in claim 26, wherein this extreme value is a minimum value, and the quantity that this preset times equals these a plurality of numerical value is poor with this specific cis-position.
29. numerical value judgment means as claimed in claim 1, wherein this specific cis-position is that these a plurality of numerical value are by little cis-position to big the arrangement.
30. numerical value judgment means as claimed in claim 29, wherein this extreme value is a minimum value, and this preset times equals this specific cis-position.
31. numerical value judgment means as claimed in claim 29, wherein this extreme value is a maximum, and the quantity that this preset times equals these a plurality of numerical value is poor with this specific cis-position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101655194A CN101989847A (en) | 2009-07-29 | 2009-07-29 | Numerical value judging device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101655194A CN101989847A (en) | 2009-07-29 | 2009-07-29 | Numerical value judging device |
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|---|---|
| CN101989847A true CN101989847A (en) | 2011-03-23 |
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| CN2009101655194A Pending CN101989847A (en) | 2009-07-29 | 2009-07-29 | Numerical value judging device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107492924A (en) * | 2017-08-04 | 2017-12-19 | 杰华特微电子（杭州）有限公司 | Battery equalizing circuit and control method |
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| US6427159B1 (en) * | 1999-08-03 | 2002-07-30 | Koninklijke Philips Electronics N.V. | Arithmetic unit, digital signal processor, method of scheduling multiplication in an arithmetic unit, method of selectively delaying adding and method of selectively adding during a first or second clock cycle |
| CN1975661A (en) * | 2006-12-20 | 2007-06-06 | 北京中星微电子有限公司 | Data operating method and apparatus in integrated circuit |
| CN1987771A (en) * | 2005-12-23 | 2007-06-27 | 中兴通讯股份有限公司 | Hardware circuit for realizing data sequencing and method |
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| US6427159B1 (en) * | 1999-08-03 | 2002-07-30 | Koninklijke Philips Electronics N.V. | Arithmetic unit, digital signal processor, method of scheduling multiplication in an arithmetic unit, method of selectively delaying adding and method of selectively adding during a first or second clock cycle |
| CN1987771A (en) * | 2005-12-23 | 2007-06-27 | 中兴通讯股份有限公司 | Hardware circuit for realizing data sequencing and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107492924A (en) * | 2017-08-04 | 2017-12-19 | 杰华特微电子（杭州）有限公司 | Battery equalizing circuit and control method |
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Application publication date: 20110323 |