CN101984567B - HS-DSCH interleaving method and device for high-order modulation - Google Patents
HS-DSCH interleaving method and device for high-order modulation Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 38
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Abstract
The invention discloses a HS-DSCH interleaving method for high-order modulation, comprising the following steps: combining a plurality of inter-column permutation sequences into one inter-column permutation sequence, performing inter-column permutation on an input sequence matrix with the combined inter-column permutation sequence, and obtaining an output sequence by directly output according to an output rule, so that separation of the input sequence and combination of the output sequence are omitted, simultaneously, a constellation rearrangement rule is integrated in an output rule under a 16QAM modulation mode, bit operations are simplified, and execution efficiency of algorithms is improved; the invention further discloses a device corresponding to the interleaving method, of which an inter-column permutation sequence conversion module is used for combining the inter-column permutation sequences, and performing inter-column permutation on the input sequence matrix with the combined inter-column permutation sequence, and an output module also can output the matrix according to the constellation rearrangement rule, the method and the device of the invention are used cooperatively, so that the HS-DSCH interleaving of the high-order modulation can be implemented.
Description
Technical field
The present invention relates to technical field of data transmission, particularly a kind of HS-DSCH deinterleaving method and device of high order modulation.
Background technology
Interweave is that a sequence is rearranged into the technology of exporting after another sequence.Data are upset original order through interweaving at transmitting terminal, and when being subject to the continuous mistake of bursty interference appearance in transmission course, because receiving terminal will carry out deinterleaving, mistake will be broken up continuously, is conducive to channel coding module and carries out error correction.
HS-DSCH (High-Speed Downlink Shared Channel) is the meaning of high speed descending sharing channel, is used for the user data of carrying HSDPA.HSDPA (High Speed Downlink Packet Access, the high speed downlink packet access) is a kind of enhanced scheme that 3GPP Release 5 proposes, main purpose is the high speed support that realizes Packet data service, and obtaining lower time delay, higher throughput of system and stronger QoS (Quality of Service, network service quality) guarantees.
In the standard, the HSDPA technology of TD-SCDMA system is only supported two kinds of modulation system QPSK and 16QAM at present.The HS-DSCH deinterleaving method of QPSK modulation system is identical with non-high speed business, and for 16QAM and the modulation system of high-order (such as 64QAM and 256QAM) more, its deinterleaving method is that the basis of the deinterleaving method under the QPSK modulation system has increased the operating procedure that list entries bit separation and output sequence bit merge.
As everyone knows, the carrier that communications field algorithm is realized is generally FPGA or DSP, and in the implementation procedure of algorithm, the time that the operation such as the independent displacement of bit or conversion consumes is longer, and controls loaded down with trivial detailsly, often will realize by the code of two or three row.Deinterleaving method for 3GPP agreement regulation, take the 16QAM modulation system as example, as seen from Figure 1, the deinterleaving method basis of its deinterleaving method under the QPSK modulation system increased the operating procedure of list entries bit separation and the merging of output sequence bit, namely list entries is divided into two subsequences, in two interleave depths are 30 interleaving block, interweave respectively, again an output sequence is merged in the output of two interleaving blocks.This kind method has inevitably increased a large amount of bit displacement and conversion operations, the modulation system of getting over high-order, and the subsequence of separation is more, and the time of consumption is also just longer.Too much algorithm consumes the time and will be unfavorable for satisfying demand to Packet data service is supported at a high speed, the shorter business hours postpones and higher throughput of system etc. strengthens day by day.
Summary of the invention
The present invention proposes a kind of HS-DSCH deinterleaving method and device of high order modulation, reducing the bit operating in the existing interleaving technology, thereby saving-algorithm is consuming time.
The HS-DSCH deinterleaving method of high order modulation of the present invention comprises step:
Read modulation system, determine interleave depth n*30 according to described modulation system, wherein, the value of n is (bit number that modulation symbol takies)/2;
With constant series p2 ' between the constant series p2 row that to merge into 1 number of elements be n*30 between n row;
List entries write matrix line by line and fill the vacant locations of described matrix with dummy bits, described matrix column number is n*30;
Adopt between described row and replace between the described matrix column of constant series p2 ' execution;
Divide the matrix after the displacement between described row equally for n group by row;
Export successively from left to right element of respectively organizing in the matrix after the displacement between described row, export from top to bottom from left to right continuous two elements for every group at every turn.
Preferably, described step with between n row between the constant series p2 row that to merge into 1 number of elements be n*30 constant series p2 ' specifically comprise:
According to list entries bit separation rule, derive the sequence number of subsequence after separating and the corresponding relation of list entries sequence number;
The row sequence number among the constant series p2 between n row is converted to the sequence number of corresponding list entries according to described corresponding relation;
Be linked in sequence between the composition row constant series p2 ' of constant series p2 between n after conversion row by its corresponding subsequence.
Preferably, described step with between n row between the constant series p2 row that to merge into 1 interleave depth be n*30 constant series P2 ' specifically comprise:
Set up n sequence q0, q1 ... q (n-1), described n sequence q0, q1 ... q (n-1) forms by tactic 30 elements of 0-29;
To described n sequence q0, q1 ... q (n-1) cross arrangement obtains sequence q, and the order of described cross arrangement is from q0 to q (n-1), is spaced apart continuous two elements;
According to row between constant series p2 respectively to the q0 after the cross arrangement, q1 ... between q (n-1) is listed as the displacement obtain cross arrangement q0 ', q1 ' ... q (n-1) ' is replaced into the displacement between the sequence number of sequence q corresponding to element between row herein;
With described sequence q0 ', q1 ' ... q (n-1) ' successively connection obtains constant series p2 ' between row.
Preferably, described step writes list entries line by line in matrix and fills the vacant locations of described matrix and later step specifically comprises with dummy bits:
Set up virtual matrix, the number of elements of described virtual matrix and list entries bit number adapt, and columns is n*30;
The sequence number m1 of the list entries that each element of described virtual matrix was corresponding when calculating was inputted list entries line by line;
The sequence number m2 of the output sequence that each element was corresponding when the element in the described virtual matrix was exported in calculating;
Whether judge the m1 value less than the list entries number of elements, if not then with this m1 value and corresponding m2 value deletion thereof, if then the data of the list entries that m1 is corresponding are put into the corresponding position of output sequence m2,
The output rule of described output sequence is:
Adopt between the row of the described virtual matrix of constant series p2 ' execution between described row and replace, it is that n organizes and counting that described virtual matrix after the displacement between row is divided equally by row, the rule of counting is: the n group is counting from left to right, count from top to bottom from left to right two elements for every group, the count value of each element is the sequence number m2 of its corresponding output sequence at every turn.
Preferably, judge also after reading described modulation system whether described debud mode is 16QAM, then carry out if not described step and determine interleave depth according to described modulation system, if then read constellation version number and carry out described step and determine interleave depth according to described modulation system, described step is exported element of respectively organizing in the matrix after the displacement between described row from left to right successively, exports from top to bottom from left to right continuous two elements for every group at every turn and specifically comprises:
Judge the described constellation version read number,
If described constellation version number is 0, export successively from left to right two group elements in the matrix after the displacement between described row, every group of continuous two elements of each output from top to bottom from left to right;
If described constellation version number is 1, export successively two group elements in the matrix after the displacement between described row from right-to-left, every group of continuous two elements of each output from top to bottom from left to right;
If constellation version number is 2, number be that 0 o'clock the way of output is exported according to constellation version again after the second group element fetch logic of the matrix after the displacement between described row is anti-;
If constellation version number is 3, number be that 1 o'clock the way of output is exported according to constellation version again after the first group element fetch logic of the matrix after the displacement between described row is anti-.
The HS-DSCH deinterleaving method of high order modulation of the present invention, according to the bit separation rule constant series between a plurality of row are merged into constant series between row, thereby need not bit separation and both can reach the interweave effect same with bit separation, saved simultaneously the process that bit merges, simplify interleaving process, saved the time that interweaves.
The HS-DSCH interlaced device of high order modulation of the present invention comprises:
The interleave depth determination module is used for reading modulation system, determines interleave depth n*30 according to described modulation system, and wherein, the value of n is (bit number that modulation symbol takies)/2;
Constant series modular converter between row, constant series p2 ' between the constant series p2 row that to merge into 1 number of elements be n*30 between being used for n be listed as;
Matrix is set up module, is used for that list entries write matrix line by line and fills the vacant locations of described matrix with dummy bits, and described matrix column number is n*30;
Replacement module between row is used for adopting between described row replacing between the described matrix column of constant series p2 ' execution;
Output module is used for the matrix after replacing between described row is divided equally for n organizes by row, exports successively from left to right the element of each group in the matrix after replacing between described row, exports from top to bottom from left to right continuous two elements for every group at every turn.
Preferably, the constant series modular converter comprises between described row:
The corresponding relation derivation module is used for going out to separate the sequence number of rear subsequence and the corresponding relation of list entries sequence number according to list entries bit separation rule induction;
The sequence number modular converter is for the sequence number that the row sequence number of constant series p2 between n row is converted to corresponding list entries according to described corresponding relation;
Constant series composite module between row, constant series p2 is by the constant series p2 ' between the composition row that is linked in sequence of its corresponding subsequence between n row after being used for changing.
Preferably, the constant series modular converter comprises between described row:
Sequence is set up module, be used for setting up n sequence q0, q1 ... q (n-1), described n sequence q0, q1 ... q (n-1) forms by tactic 30 elements of 0-29;
The cross arrangement module, be used for to described n sequence q0, q1 ... q (n-1) cross arrangement obtains sequence q, and the order of described cross arrangement is from q0 to q (n-1), is spaced apart continuous two elements;
The sequence number replacement module, be used for according to constant series p2 between row respectively to the q0 after the cross arrangement, q1 ... between q (n-1) is listed as the displacement obtain cross arrangement q0 ', q1 ' ... q (n-1) ' is replaced into the displacement between the sequence number of sequence q corresponding to element between row herein;
Link block, be used for described sequence q0 ', q1 ' ... q (n-1) ' successively connection obtains constant series p2 ' between row.
Preferably, the matrix that described matrix is set up module foundation is virtual matrix, and the columns of described virtual matrix is n*30, and line number is the smallest positive integral more than or equal to (list entries number of elements)/(n*30);
Also comprise corresponding sequence number computing module, the sequence number m1 of the list entries that each element of described virtual matrix is corresponding when for calculating list entries being inputted line by line, the sequence number m2 of the output sequence that each element was corresponding when calculating was exported the element in the described virtual matrix according to the output rule;
Described output module also is used for whether judging the m1 value less than the list entries bit number, if not then with this m1 value and corresponding m2 value deletion thereof, if then the data of the list entries that m1 is corresponding are put into the corresponding position of output sequence m2;
The output rule that described corresponding sequence number computing module adopts when calculating m2 is: described virtual matrix is exported according to the output intent of described output module after processing through replacement module between described row.
Preferably, described interleave depth determination module also is used for judging whether described debud mode is 16QAM after reading described modulation system, then determine interleave depth according to described modulation system if not, if then read constellation version number and determine interleave depth according to described modulation system, the matrix of described output module after with displacement between described row pressed row and divided equally for also number selecting the different way of outputs according to constellation version after the n group:
Described output module also be used for to be judged constellation version number,
If described constellation version number is 0, export successively from left to right two group elements in the matrix after the displacement between described row, every group of continuous two elements of each output from top to bottom from left to right;
If described constellation version number is 1, export successively two group elements in the matrix after the displacement between described row from right-to-left, every group of continuous two elements of each output from top to bottom from left to right;
If constellation version number is 2, number be that 0 o'clock the way of output is exported according to constellation version again after the second group element fetch logic of the matrix after the displacement between described row is anti-;
If constellation version number is 3, number be that 1 o'clock the way of output is exported according to constellation version again after the first group element fetch logic of the matrix after the displacement between described row is anti-.
The HS-DSCH interlaced device of high order modulation of the present invention, the constant series modular converter is merged into constant series between row with constant series between a plurality of row between row owing to adopting, thereby interweave separately after needn't again list entries being separated into a plurality of subsequences, also need not the merging of output subsequence both can directly be obtained final output sequence, therefore, this device is by avoiding the method that list entries separates and output sequence merges to reduce the bit shifting function, save the time that interweaves, improved the efficient that interweaves.
Description of drawings
Fig. 1 is HS-DSCH weaving diagram under the prior art 16QAM modulation system;
Fig. 2 is the schematic flow sheet of the HS-DSCH deinterleaving method embodiment one of high order modulation of the present invention;
Fig. 3 is the schematic diagram that obtains constant series p2 ' between row among the HS-DSCH deinterleaving method embodiment two of high order modulation of the present invention;
Fig. 4 is the schematic diagram that obtains constant series p2 ' between row among the HS-DSCH deinterleaving method embodiment three of high order modulation of the present invention;
Fig. 5 is the structural representation of the HS-DSCH interlaced device embodiment one of high order modulation of the present invention;
Fig. 6 is the structural representation of the HS-DSCH interlaced device embodiment two of high order modulation of the present invention;
Fig. 7 is the relation between HS-DSCH constellation rearrangement method and the constellation version number under the 16QAM modulation system.
Embodiment
It is consuming time since bit operating is complicated, the present invention is just from reducing or avoiding the angle of bit operating to start with, a kind of new deinterleaving method has been proposed, and the fundamental difference of prior art is constant series between a plurality of row are merged into constant series between row, owing to constant series between row can be finished the work of constant series between a plurality of row, therefore, list entries interweaves after no longer needing to separate separately, but make the as a whole matrix that writes, directly output after displacement between row, save simultaneously the step that bit merges, explained in detail the HS-DSCH deinterleaving method of high order modulation of the present invention below in conjunction with the drawings and specific embodiments.
Embodiment one:
The HS-DSCH deinterleaving method of high order modulation of the present invention as shown in Figure 2, comprises step:
Replace between the described matrix column of constant series p2 ' execution between step 104, the described row of employing;
As shown in Figure 1, the bit separation rule of list entries is in the prior art: list entries evenly is separated into n subsequence take two bits as unit, n herein is identical with n meaning in the present embodiment, be that each modulation symbol takies bit number under this modulation system 1/2, n subsequence is admitted to respectively n block interleaver (Block Interleaver), subsequence is write matrix line by line in block interleaver, which kind of modulation system no matter, the interleave depth of block interleaver is 30, interleave depth has determined the matrix column number, be that the matrix column sequence number is 0,1,2,29 (sequence number that relates among the present invention all is to count from 0), matrix in each block interleaver is according to displacement between constant series p2 is listed as between same row, the element of p2 is by the matrix column sequence number after upsetting, it is the numeral in Fig. 3 grid, the outer numeral of grid is the sequence number of grid, also represent simultaneously the matrix column sequence number, be 20 such as the row sequence number in second grid, the outer row sequence number of its corresponding grid is 1, looks like to be listed as for the element with matrix the 20th row is placed on the 1st.So, after finishing between row displacement according to p2, subfamily matrix between block interleaver will be listed as after the displacement is by row output, obtain n output subsequence, n output subsequence remerges and is final output sequence, the rule that merges is: continuous two elements of the each output of each subsequence matrix, n sub-sequence matrix carried out according to first order to last, same subsequence entry of a matrix element is carried out according to the most front dibit to the order of last dibit, jump to first subsequence matrix when carrying out to last subsequence matrix, circulation is until all merged outputs of subsequence matrix all elements successively.
List entries no longer is separated into subsequence in the present embodiment, but do as a wholely to be interweaved by single block interleaver, namely write line by line a matrix, thus, the sequence number of the list entries that the row sequence number of the every row of matrix and this row the first row element are corresponding in the step 103 is identical, and then the present embodiment represents constant series p2 ' between this matrix column with the sequence number of list entries.As mentioned above, row sequence number between being listed as in the prior art among the constant series p2 is with subsequence matrix column sequence number behind the subsequence input matrix, in order to obtain p2 ', the present embodiment calculates first the sequence number of the corresponding list entries of prior art subsequence matrix the first row element, the row sequence number that replaces again its column with this sequence number, thereby, each subsequence obtains constant series between new row that represent with the list entries sequence number, it is identical adopting between p2 and these new row the constant series antithetical phrase sequence matrix result who obtains that interweaves, constant series are according to the constant series p2 ' between the row that both obtain this deinterleaving method that is linked in sequence of its corresponding subsequence between the row that n is new, its number of elements is n*30, the interleave depth that is the present embodiment is n*30, when step 103 writes matrix line by line with list entries, if the number of elements of list entries or bit number are not the integral multiples of n*30, then the line number of matrix is more than or equal to the smallest positive integral of list entries bit number divided by n*30 institute value, therefore, matrix last column may be had vacant position, at this moment, with dummy bits filled matrix vacant locations, dummy bits can be the character such as 0 or 1, and it is carried out mark in order to when step 106 is exported dummy bits is deleted.In step 104, matrix between with p2 ' matrix of step 103 being listed as after the displacement is equivalent in the prior art to carry out the matrix after according to the subsequence order columns stack of correspondence of the subsequence matrix after the displacement between row with p2, for identical with the output sequence of prior art, the present embodiment will be divided into through the matrix after the displacement between step 104 row the identical n group of columns first, the way of output of this n group submatrix is identical with the way of output of n sub-sequence matrix, two elements of every group of each output, these two elements are this group continuous two elements from top to bottom from left to right, export two elements for first group from left to right, export again two elements for second group, until last group, export follow-up two elements for first group, successively circulation, all elements connects together and has both formed output sequence, if but certain element is that dummy bits is then with its deletion.
Need to prove, list entries is the sequence that forms of bit one by one, the process that interweaves is also carried out take bit as object, reaches above that the element in the constant series and matrix all refers to a bit between the list entries hereinafter mentioned, output sequence, subsequence, row.
Embodiment two:
The difference of the present embodiment and embodiment one is, the present embodiment has been explained the implementation procedure of embodiment one step 102 in detail, and detailed step is as follows:
Step 201, regular according to the list entries bit separation is derived the sequence number of subsequence after separating and the corresponding relation of list entries sequence number;
Step 202, according to described corresponding relation the row sequence number among the constant series p2 between n row is converted to the sequence number of corresponding list entries;
Constant series p2 is according to the constant series p2 ' between the composition row that is linked in sequence of its corresponding subsequence between step 203, n row after will changing.
Take the 16QAM modulation system as example, list entries is S
0, S
1... S
R-1, existing deinterleaving method is divided into two subsequences with list entries: first subsequence T:T
0, T
1, T
2, T
3... T
R/2-2, T
R/2-1Second subsequence U:U
0, U
1, U
2, U
3... U
R/2-2, U
R/2-1, the element of subsequence T is the element of corresponding list entries respectively: S
0, S
1, S
4, S
5... S
R-4, S
R-3The element of subsequence U is the element of corresponding list entries respectively: S
2, S
3, S
6, S
7... S
R-2, S
R-1
Summary can get, and the pass under the identity element between the subscript of list entries and affiliated subsequence is:
(1). for sequence T, if element T
iSubscript i be odd number, then the subscript of its corresponding list entries S is that sequence number is 2i-1, if element T
iSubscript i be even number, then the sequence number of its corresponding list entries S is 2i;
(2). for sequence U, if element U
iSubscript i be odd number, then the subscript of its corresponding list entries S is that sequence number is 2i+1, if element U
iSubscript i be even number, then the sequence number of its corresponding list entries S is 2i+2.
Constant series p2 as shown in Figure 3 between row, numeral in the grid namely is the row sequence number of constant series between row, after sequence T, U are write matrix line by line, the matrix column sequence number is identical with the sequence number of the first row element, therefore, above-mentioned relation (1), (2) are equally applicable to the row sequence number of p2 and the relation between the list entries sequence number, and as shown in Figure 3, relation (1), (2) represent to be with p2 (i), p3 (i), p4 (i):
(3). when p2 (i) is odd number, p3 (i)=p2 (i) * 2-1, p4 (i)=p2 (i) * 2+1;
(4). when p2 (i) is even number, p3 (i)=p2 (i) * 2, p4 (i)=p2 (i) * 2+2.
P2 (i), p3 (i), p4 (i) represents respectively constant series p2 between row, p3, numeral in the p4 grid, obtain relation (1) and (2) or (3) and (4) and just finished step 201, next carry out step 202,203, use relation (1) and (2) or (3) and (4) with subsequence T, constant series p2 represents both to obtain constant series p3 between row with the list entries sequence number between the row of U, p4, p3 is applicable to constant series between the row of first subsequence of list entries under the prior art 16QAM modulation system, p4 is applicable to constant series between the row of second subsequence of list entries under the prior art 16QAM modulation system, with p3, p4 links together and both forms constant series p2 ' between the row that are applicable to list entries under the present embodiment 16QAM modulation system.
The other technologies feature of the present embodiment is identical with embodiment one, does not repeat them here.
Embodiment three
The difference of the present embodiment and embodiment two is, the present embodiment is realized the step 102 of embodiment one with another kind of method, and detailed step is as follows.
Step 301, set up n sequence q0, q1 ... q (n-1), described n sequence q0, q1 ... q (n-1) forms by tactic 30 elements of 0-29;
Step 302, to described n sequence q0, q1 ... q (n-1) cross arrangement obtains sequence q, and the order of described cross arrangement is from q0 to q (n-1), is spaced apart continuous two elements;
Step 303, according to row between constant series p2 respectively to the q0 after the cross arrangement, q1 ... between q (n-1) is listed as the displacement obtain cross arrangement q0 ', q1 ' ... q (n-1) ' is replaced into the displacement between the sequence number of sequence q corresponding to element between row herein;
Step 304, with described sequence q0 ', q1 ' ... q (n-1) ' successively connection obtains constant series p2 ' between row.
The present embodiment still describes as an example of the 16QAM modulation system example, because the bit number that 16QAM modulation system modulated symbol takies is 4, therefore the value of n is 2 in the above-mentioned steps, as shown in Figure 4, set up two sequence p3 that comprise respectively 30 elements, p4, p3,30 elements of p4 all are 30 numerals of 0-29, the sequence number that is equivalent to subsequence matrix the first row element, two sequences are intersected every two elements, the first two element of p3 comes the foremost, it then is the first two element of p4, the 3rd of p3 again, four elements, circulation obtains sequence q after the intersection successively, be the sequence number of each element such as the numeral on the sequence q grid among Fig. 4, this sequence number is equivalent to the sequence number of list entries.Execution in step 303, displacement between according to p2 the p3 among the sequence q, p4 being listed as respectively, but the content of displacement is the sequence number on the grid, as, the element of p3 the 20th row should be put into the 1st row according to p2, because the sequence number of the sequence q that p3 the 20th row are corresponding is 40, so with 40 first rows of putting into p3, so, sequence p3 ' and p4 ' between obtaining being listed as after the displacement, p3 ' and p4 ' are coupled together, and p3 ' is front, and that obtain is exactly p2 '.
The other technologies feature of the present embodiment is identical with embodiment two, does not repeat them here.
Embodiment four
Embodiment one to three writes matrix line by line with list entries, again output after the displacement between row, in order further to simplify the step that interweaves, the present embodiment no longer writes matrix with list entries, but calculate the sequence number corresponding relation of list entries and output sequence, rearrangement obtains output sequence to list entries according to corresponding relation, and detailed step is as follows.
Step 401, set up virtual matrix, the columns of described virtual matrix is n*30, and line number is the smallest positive integral more than or equal to (list entries bit number)/(n*30);
Step 402, calculate the sequence number m1 of the list entries that each element of described virtual matrix was corresponding when list entries inputted line by line, when not having list entries sequence number and element at once, the m1 value is continued to add 1;
Step 403, calculate the sequence number m2 of the output sequence that each element was corresponding when the element in the described virtual matrix exported;
Step 404, whether judge the m1 value less than the list entries number of elements, then this m1 value and corresponding m2 value thereof are deleted if not, if then the data of the list entries that m1 is corresponding are put into the corresponding position of output sequence m2,
The output rule of described output sequence is:
Adopt between the row of the described virtual matrix of constant series p2 ' execution between described row and replace, it is that n organizes and counting that described virtual matrix after the displacement between row is divided equally by row, the rule of counting is: the n group is counting from left to right, count from top to bottom from left to right two elements for every group, the count value of each element is the sequence number m2 of its corresponding output sequence at every turn.
The present embodiment model virtual matrix, the writing and exporting of analog input sequence, element in the virtual matrix is any character, corresponding two sequence numbers of each element: the sequence number m1 of list entries and the sequence number m2 of output sequence, be that m1 is corresponding one by one with m2, be that the element of the list entries of m1 rearranges according to the sequence number of the m2 corresponding with it and then obtains final output sequence with sequence number, under the 16QAM modulation system, if list entries is inputted virtual matrix line by line, then (number of supposing list entries is 120 to the element of virtual matrix the 1st row the 5th row just, after writing matrix, row sequence number and row sequence number are all counted from 0) sequence number of corresponding list entries is m1=65, if virtual matrix is replaced between being listed as according to p2 ', then the 5th row are displaced to the 3rd row of virtual matrix, virtual matrix is divided into two parts by row, export first two elements of first row, the sequence number of corresponding output sequence is 0,1, export again two elements of the 30th row, the sequence number of corresponding output sequence is 2,3, then export two elements of the 1st row, the sequence number of corresponding output sequence is 4,5, export the element of the 3rd row, the sequence number of corresponding output sequence is 12,13, therefore, the sequence number of the corresponding output sequence of element of front the 1st row of displacement the 5th row is m2=13 between row, judge and learn that the m1 value is less than list entries number of elements 120, therefore directly the 65th element of list entries is put into the 13rd position, like this each element of list entries is rearranged what obtain according to its corresponding m2 value is exactly output sequence.When the number of elements of list entries is not the integral multiple of n*30, the value of m1 may be greater than the number of elements of list entries, therefore, and when list entries is resequenced, judge that first the m1 value is whether less than the number of elements of list entries, if more than or equal to then that this m1 value is corresponding with it m2 value deletion.
The other technologies feature of the present embodiment is identical with embodiment three, does not repeat them here.
Embodiment five
When modulation system is 16QAM, output sequence also needs number to rearrange and calculate according to constellation version, therefore, carry out again displacement and conversion between bit, the present embodiment is in order further to reduce the operation between bit, constellation rearrangement rules is incorporated the output rule, the sequence that makes output directly is exactly the sequence behind the constellation rearrangement, again saved algorithm consuming time, it is the relation between HS-DSCH constellation rearrangement method and the constellation version number under the 16QAM modulation system shown in the form of Fig. 7, its k mod4=1 means and divides per 4 bits of output sequence into a unit, and per unit is designated as v
kv
K+1v
K+2v
K+3, form as shown in Figure 7, the different different operations of constellation version correspondence, below explain in detail the present embodiment.
After step 101 has read modulation system, judge whether debud mode is 16QAM, then continue to carry out if not the step of back, if then read constellation version number, under the 16QAM modulation system, matrix between step 105 will be listed as after the displacement is divided equally for two groups by row, and namely first group and second group, step 106 is realized by following steps.
Judge the constellation version read number,
If described constellation version number is 0, as shown in Figure 7, respective operations is not for processing, two group elements in the output matrix successively from left to right, every group of continuous two elements of each output from top to bottom from left to right;
If described constellation version number is 1, as shown in Figure 7, respective operations is with the first two bit of output sequence per unit and latter two bit exchange, because the first two bit of output sequence per unit is comprised of first group element of replacing rear matrix between row, latter two bit of output sequence per unit is comprised of second group element of replacing rear matrix between row, in order to make output sequence both be the sequence behind the constellation rearrangement, export first second group element and export again first group element, every group of when output be still according to from top to bottom continuous two elements of the each output of order from left to right, and the output sequence that so obtains is the sequence of carrying out after constellation version number 1 respective operations;
If constellation version number is 2, as shown in Figure 7, respective operations is that latter two bit fetch logic of output sequence per unit is anti-, the way of output and the constellation version of this moment number is that 0 o'clock the way of output is identical, just that latter two bit fetch logic of output sequence per unit is anti-, perhaps before output, the element of second group in the matrix after the displacement between row is shifted to an earlier date fetch logic anti-;
If constellation version number is 3, as shown in Figure 7, respective operations is with the first two bit of output sequence per unit and latter two bit exchange, the first two bit fetch logic before again latter two bit after the exchange namely being exchanged is anti-, therefore, the way of output and the constellation version of this moment number is that 1 o'clock the way of output is identical, just that latter two bit fetch logic of output sequence per unit is anti-, the element fetch logic that the matrix between perhaps will be listed as after the displacement is first group number is that 1 o'clock the way of output is exported according to constellation version again after instead.
The HS-DSCH interlaced device of high order modulation of the present invention is the device corresponding with the HS-DSCH deinterleaving method of high order modulation of the present invention, explains in detail the present invention below in conjunction with embodiment and accompanying drawing.
Embodiment one
The HS-DSCH interlaced device of high order modulation of the present invention as shown in Figure 5, comprising:
The interleave depth determination module is used for reading modulation system, determines interleave depth n*30 according to described modulation system, and wherein, the value of n is (bit number that modulation symbol takies)/2;
Constant series modular converter between row, constant series p2 ' between the constant series p2 row that to merge into 1 number of elements be n*30 between being used for n be listed as;
Matrix is set up module, is used for that list entries write matrix line by line and fills the vacant locations of described matrix with dummy bits, and described matrix column number is n*30;
Replacement module between row is used for adopting between described row replacing between the described matrix column of constant series p2 ' execution;
Output module, be used for dividing the matrix after the displacement between described row equally for n group by row, export successively from left to right element of respectively organizing in the matrix after the displacement between described row, export from top to bottom from left to right continuous two elements for every group at every turn, and with described virtual matrix deletion.
As shown in Figure 5, the interleave depth determination module, constant series modular converter between row, replacement module and matrix are set up module and are linked to be a circle between row, replacement module links to each other with output module again between row, the interleave depth determination module sends to respectively between row constant series modular converter and matrix with its n that determines according to modulation system and sets up module, the constant series modular converter sends to replacement module between row with its p2 ' that is converted between row, matrix is set up module the matrix of its foundation is sent to replacement module between row, replacement module sends to output module with the matrix after replacing between its row between row, and output module is exported the element in the matrix.
Embodiment two
The difference of the present embodiment and embodiment one is, the constant series modular converter is by realizing with lower module between the row of embodiment one:
The corresponding relation derivation module is used for going out to separate the sequence number of rear subsequence and the corresponding relation of list entries sequence number according to list entries bit separation rule induction;
The sequence number modular converter is for the sequence number that the row sequence number of constant series p2 between n row is converted to corresponding list entries according to described corresponding relation;
Constant series composite module between row, constant series p2 is by the constant series p2 ' between the composition row that is linked in sequence of its corresponding subsequence between n row after being used for changing.
By Fig. 6 and above description as can be known, above-mentioned three modules link to each other successively, the sequence number modular converter links to each other with the interleave depth determination module, between row the constant series composite module with row between replacement module link to each other, the interleave depth of interleave depth determination module has been determined, the number of the required p2 of sequence number modular converter is also just definite, and replacement module is replaced between the list entries matrix is listed as with constant series p2 ' between the row of constant series composite module combination between row between row.
The other technologies feature of the present embodiment is identical with embodiment one, does not repeat them here.
Embodiment three
The difference of the present embodiment and embodiment two is, the constant series modular converter comprises between the row of the present embodiment:
Sequence is set up module, be used for setting up n sequence q0, q1 ... q (n-1), described n sequence q0, q1 ... q (n-1) forms by tactic 30 elements of 0-29;
The cross arrangement module, be used for to described n sequence q0, q1 ... q (n-1) cross arrangement obtains sequence q, and the order of described cross arrangement is from q0 to q (n-1), is spaced apart continuous two elements;
The sequence number replacement module, be used for according to constant series p2 between row respectively to the q0 after the cross arrangement, q1 ... between q (n-1) is listed as the displacement obtain cross arrangement q0 ', q1 ' ... q (n-1) ' is replaced into the displacement between the sequence number of sequence q corresponding to element between row herein;
The sequence link block, be used for q0 ', q1 ' ... q (n-1) ' is connected in turn and obtains constant series p2 ' between row.
Four modules of the present embodiment link to each other successively, and sequence number is set up module and linked to each other with the interleave depth determination module, the sequence link block be listed as between replacement module link to each other.
The other technologies feature of the present embodiment is identical with embodiment two, does not repeat them here.
Embodiment four
The present embodiment and embodiment two, three difference be, what the matrix in the present embodiment set up that module sets up is virtual matrix, and also comprises corresponding sequence number computing module.
The matrix that matrix is set up module foundation is virtual matrix, and the columns of virtual matrix is n*30, and line number is the smallest positive integral more than or equal to (list entries number of elements)/(n*30);
Also comprise corresponding sequence number computing module, the sequence number m1 of the list entries that each element of described virtual matrix is corresponding when for calculating list entries being inputted line by line, when not having list entries sequence number and element at once, the m1 value is continued to add 1, the sequence number m2 of the output sequence that each element was corresponding when the element in the described virtual matrix was exported in calculating;
Also for whether judging the m1 value greater than the list entries bit number, if then with this m1 value and corresponding m2 value deletion thereof, then the data of the list entries that m1 is corresponding are put into the corresponding position of output sequence m2 to described output module if not;
The output rule of described corresponding sequence number computing module output sequence that adopts when calculating m2 is: described virtual matrix is exported according to the output intent of described output module after processing through replacement module between described row.
The other technologies feature of the present embodiment is identical with embodiment three, does not repeat them here.
Embodiment five
The difference of the present embodiment and embodiment four is, the output module of the present embodiment has increased the function of exporting in conjunction with constellation rearrangement under the 16QAM modulation system, the interleave depth determination module judges also whether this debud mode is 16QAM after having read modulation system, then determine interleave depth according to described modulation system if not, if then read constellation version number and constellation version number be sent to output module, the matrix between output module will be listed as after the displacement press row divide equally be two groups namely first group with second group after number select the different way of outputs according to constellation version:
Output module judges that constellation version number is 0,1,2, or 3,
If described constellation version number is 0, as shown in Figure 7, respective operations is not for processing, two group elements in the output matrix successively from left to right, every group of continuous two elements of each output from top to bottom from left to right;
If described constellation version number is 1, as shown in Figure 7, respective operations is with the first two bit of output sequence per unit and latter two bit exchange, because the first two bit of output sequence per unit is comprised of first group element of replacing rear matrix between row, latter two bit of output sequence per unit is comprised of second group element of replacing rear matrix between row, in order to make output sequence both be the sequence behind the constellation rearrangement, export first second group element and export again first group element, every group of when output be still according to from top to bottom continuous two elements of the each output of order from left to right, and the output sequence that so obtains is the sequence of carrying out after constellation version number 1 respective operations;
If constellation version number is 2, as shown in Figure 7, respective operations is that latter two bit fetch logic of output sequence per unit is anti-, the way of output and the constellation version of this moment number is that 0 o'clock the way of output is identical, just that latter two bit fetch logic of output sequence per unit is anti-, perhaps before output, the element of second group in the matrix after the displacement between row is shifted to an earlier date fetch logic anti-;
If constellation version number is 3, as shown in Figure 7, respective operations is with the first two bit of output sequence per unit and latter two bit exchange, the first two bit fetch logic before again latter two bit after the exchange namely being exchanged is anti-, therefore, the way of output and the constellation version of this moment number is that 1 o'clock the way of output is identical, just that latter two bit fetch logic of output sequence per unit is anti-, the element fetch logic that the matrix between perhaps will be listed as after the displacement is first group number is that 1 o'clock the way of output is exported according to constellation version again after instead
The other technologies feature of the present embodiment is identical with embodiment four, does not repeat them here.
HS-DSCH deinterleaving method and the device of high order modulation of the present invention are combined use, and the HS-DSCH that both can finish high order modulation in the HSDPA technology interweaves.
Above-described embodiment of the present invention does not consist of the restriction to protection range of the present invention.Any modification of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within the claim protection range of the present invention.
Claims (6)
1. the HS-DSCH deinterleaving method of a high order modulation is characterized in that, comprises step:
Read modulation system, determine interleave depth n*30 according to described modulation system, wherein, the value of n is (bit number that modulation symbol takies)/2;
With constant series p2 ' between the constant series p2 row that to merge into 1 number of elements be n*30 between n row;
List entries write matrix line by line and fill the vacant locations of described matrix with dummy bits, described matrix column number is n*30;
Adopt between described row and replace between the described matrix column of constant series p2 ' execution;
Divide the matrix after the displacement between described row equally for n group by row;
Export successively from left to right element of respectively organizing in the matrix after the displacement between described row, export from top to bottom from left to right continuous two elements for every group at every turn, and with described dummy bits deletion;
Described step with between n row between the constant series p2 row that to merge into 1 number of elements be n*30 constant series p2 ' be specially:
According to list entries bit separation rule, derive the sequence number of each subsequence after separating and the corresponding relation of list entries sequence number; Be converted to the sequence number of corresponding list entries according to the row sequence number among the constant series p2 between the described corresponding relation row that each subsequence is corresponding; Be linked in sequence between the composition row constant series p2 ' of constant series p2 between the row after the conversion by its corresponding subsequence;
Or
Set up n sequence q0, q1 ... q (n-1), described n sequence q0, q1 ... q (n-1) forms by tactic 30 elements of 0-29; To described n sequence q0, q1 ... q (n-1) cross arrangement obtains sequence q, and the order of described cross arrangement is from q0 to q (n-1), is spaced apart continuous two elements; According to row between constant series p2 respectively to the q0 after the cross arrangement, q1 ... between q (n-1) is listed as the displacement obtain n sequence q0 ', q1 ' ... q (n-1) ' is replaced into the displacement between the sequence number of sequence q corresponding to element between row herein; With described sequence q0 ', q1 ' ... q (n-1) ' successively connection obtains constant series p2 ' between row.
2. the HS-DSCH deinterleaving method of high order modulation according to claim 1 is characterized in that, described step writes list entries line by line in matrix and fills the vacant locations of described matrix and later step specifically comprises with dummy bits:
Set up virtual matrix, the columns of described virtual matrix is n*30, and line number is the smallest positive integral more than or equal to (list entries number of elements)/(n*30);
The sequence number m1 of the list entries that each element of described virtual matrix was corresponding when calculating was inputted list entries line by line when not having list entries sequence number and element at once, continues to add 1 with the m1 value;
The sequence number m2 of the output sequence that each element was corresponding when calculating was exported the element in the described virtual matrix according to the output rule;
Whether judge the m1 value less than the list entries number of elements, if not then with this m1 value and corresponding m2 value deletion thereof, if then the data of the list entries that m1 is corresponding are put into the corresponding position of output sequence m2,
The output rule of described output sequence is:
Adopt between the row of the described virtual matrix of constant series p2 ' execution between described row and replace, it is that n organizes and counting that described virtual matrix after the displacement between row is divided equally by row, the rule of counting is: the n group is counting from left to right, count from top to bottom from left to right two elements for every group, the count value of each element is the sequence number m2 of its corresponding output sequence at every turn.
3. the HS-DSCH deinterleaving method of high order modulation according to claim 1, it is characterized in that, judge also after reading described modulation system whether described modulation system is 16QAM, then carry out if not described step and determine interleave depth according to described modulation system, if then read constellation version number and carry out described step and determine interleave depth according to described modulation system, described step is exported element of respectively organizing in the matrix after the displacement between described row from left to right successively, exports from top to bottom from left to right continuous two elements for every group at every turn and specifically comprises:
Judge the described constellation version read number,
If described constellation version number is 0, export successively from left to right two group elements in the matrix after the displacement between described row, every group of continuous two elements of each output from top to bottom from left to right;
If described constellation version number is 1, export successively two group elements in the matrix after the displacement between described row from right-to-left, every group of continuous two elements of each output from top to bottom from left to right;
If constellation version number is 2, number be that 0 o'clock the way of output is exported according to constellation version again after the second group element fetch logic of the matrix after the displacement between described row is anti-;
If constellation version number is 3, number be that 1 o'clock the way of output is exported according to constellation version again after the first group element fetch logic of the matrix after the displacement between described row is anti-.
4. the HS-DSCH interlaced device of a high order modulation is characterized in that, comprising:
The interleave depth determination module is used for reading modulation system, determines interleave depth n*30 according to described modulation system, and wherein, the value of n is (bit number that modulation symbol takies)/2;
Constant series modular converter between row, constant series p2 ' between the constant series p2 row that to merge into 1 number of elements be n*30 between being used for n be listed as;
Matrix is set up module, is used for that list entries write matrix line by line and fills the vacant locations of described matrix with dummy bits, and described matrix column number is n*30;
Replacement module between row is used for adopting between described row replacing between the described matrix column of constant series p2 ' execution;
Output module, be used for dividing the matrix after the displacement between described row equally for n group by row, export successively from left to right element of respectively organizing in the matrix after the displacement between described row, export from top to bottom from left to right continuous two elements for every group at every turn, and with described dummy bits deletion;
The constant series modular converter comprises between described row:
The corresponding relation derivation module is used for going out to separate the sequence number of rear each subsequence and the corresponding relation of list entries sequence number according to list entries bit separation rule induction; The sequence number modular converter is used for being converted to according to the row sequence number of constant series p2 between the described corresponding relation row that each subsequence is corresponding the sequence number of corresponding list entries; Constant series composite module between row, constant series p2 is by the constant series p2 ' between the composition row that is linked in sequence of its corresponding subsequence between the row after being used for changing;
Or
Sequence is set up module, be used for setting up n sequence q0, q1 ... q (n-1), described n sequence q0, q1 ... q (n-1) forms by tactic 30 elements of 0-29; The cross arrangement module, be used for to described n sequence q0, q1 ... q (n-1) cross arrangement obtains sequence q, and the order of described cross arrangement is from q0 to q (n-1), is spaced apart continuous two elements; The sequence number replacement module, be used for according to constant series p2 between row respectively to the q0 after the cross arrangement, q1 ... between q (n-1) is listed as the displacement obtain cross arrangement q0 ', q1 ' ... q (n-1) ' is replaced into the displacement between the sequence number of sequence q corresponding to element between row herein; Link block, be used for described sequence q0 ', q1 ' ... q (n-1) ' successively connection obtains constant series p2 ' between row.
5. the HS-DSCH interlaced device of high order modulation according to claim 4 is characterized in that,
The matrix that described matrix is set up module foundation is virtual matrix, and the columns of described virtual matrix is n*30, and line number is the smallest positive integral more than or equal to (list entries number of elements)/(n*30);
Also comprise corresponding sequence number computing module, the sequence number m1 of the list entries that each element of described virtual matrix is corresponding when for calculating list entries being inputted line by line, when not having list entries sequence number and element at once, the m1 value is continued to add 1, the sequence number m2 of the output sequence that each element was corresponding when calculating was exported the element in the described virtual matrix according to the output rule;
Described output module also is used for whether judging the m1 value less than the list entries bit number, if not then with this m1 value and corresponding m2 value deletion thereof, if then the data of the list entries that m1 is corresponding are put into the corresponding position of output sequence m2;
Described corresponding sequence number computing module adopts the output rule to be when calculating m2: described virtual matrix is exported according to the output intent of described output module after processing through replacement module between described row.
6. the HS-DSCH interlaced device of high order modulation according to claim 4, it is characterized in that, described interleave depth determination module also is used for judging whether described modulation system is 16QAM after reading described modulation system, then determine interleave depth according to described modulation system if not, if then read constellation version number and determine that according to described modulation system interleave depth is 60, the matrix of described output module after with displacement between described row pressed row and divided equally and also number select the different way of outputs according to constellation version after being two groups:
Described output module also be used for to be judged constellation version number,
If described constellation version number is 0, export successively from left to right two group elements in the matrix after the displacement between described row, every group of continuous two elements of each output from top to bottom from left to right;
If described constellation version number is 1, export successively two group elements in the matrix after the displacement between described row from right-to-left, every group of continuous two elements of each output from top to bottom from left to right;
If constellation version number is 2, number be that 0 o'clock the way of output is exported according to constellation version again after the second group element fetch logic of the matrix after the displacement between described row is anti-;
If constellation version number is 3, number be that 1 o'clock the way of output is exported according to constellation version again after the first group element fetch logic of the matrix after the displacement between described row is anti-.
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| CN101237440A (en) * | 2007-02-02 | 2008-08-06 | 华为技术有限公司 | A data interweaving method and device |
| EP2040407A2 (en) * | 2007-07-23 | 2009-03-25 | Samsung Electronics Co., Ltd | Methods and apparatus for rate matching to improve hybrid ARQ operations |
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| CN101557272A (en) * | 2008-04-09 | 2009-10-14 | 展讯通信（上海）有限公司 | Method and device for interleaving high-order modulated HS-DSCH in TD-SCDMA system HSOPA |
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| CN101237440A (en) * | 2007-02-02 | 2008-08-06 | 华为技术有限公司 | A data interweaving method and device |
| EP2040407A2 (en) * | 2007-07-23 | 2009-03-25 | Samsung Electronics Co., Ltd | Methods and apparatus for rate matching to improve hybrid ARQ operations |
| CN101453292A (en) * | 2007-11-30 | 2009-06-10 | 大唐移动通信设备有限公司 | Method and apparatus for channel interleaving |
| CN101557272A (en) * | 2008-04-09 | 2009-10-14 | 展讯通信（上海）有限公司 | Method and device for interleaving high-order modulated HS-DSCH in TD-SCDMA system HSOPA |
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