CN105577325B - A kind of parallel processing interleaver applied to orthogonal frequency division multiplex transmission system - Google Patents
A kind of parallel processing interleaver applied to orthogonal frequency division multiplex transmission system Download PDFInfo
- Publication number
- CN105577325B CN105577325B CN201511009122.8A CN201511009122A CN105577325B CN 105577325 B CN105577325 B CN 105577325B CN 201511009122 A CN201511009122 A CN 201511009122A CN 105577325 B CN105577325 B CN 105577325B
- Authority
- CN
- China
- Prior art keywords
- data
- ping
- interleaver
- ram
- parallel processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012545 processing Methods 0.000 title claims abstract description 43
- 230000005540 biological transmission Effects 0.000 title claims abstract description 28
- 230000015654 memory Effects 0.000 claims abstract description 27
- 230000008520 organization Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 7
- 238000013507 mapping Methods 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 2
- 238000013500 data storage Methods 0.000 claims description 2
- 238000009940 knitting Methods 0.000 claims 1
- 235000013350 formula milk Nutrition 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 13
- 238000004891 communication Methods 0.000 description 11
- 239000011159 matrix material Substances 0.000 description 10
- 230000009466 transformation Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 241001269238 Data Species 0.000 description 5
- 238000006073 displacement reaction Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000010295 mobile communication Methods 0.000 description 2
- 101100325756 Arabidopsis thaliana BAM5 gene Proteins 0.000 description 1
- 101150046378 RAM1 gene Proteins 0.000 description 1
- 101100476489 Rattus norvegicus Slc20a2 gene Proteins 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000013501 data transformation Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
The present invention discloses a kind of parallel processing interleaver applied to orthogonal frequency division multiplex transmission system, orthogonal frequency division multiplex transmission system includes a transmitter, transmitter handles coded data using parallel interleaver, parallel processing interleaver includes: one, three-level interleaving treatment module, ping-pong ram memory cell, the unit is write data into and is carried out simultaneously with reading by ping-pong operation；In ping-pong ram memory cell, each Pingpang Memory includes two groups, and every group of storage organization for having 6 RAM；One, three-level interleaving treatment module includes: data address generation unit, for generating read/write address；Second level interleaving treatment module, for being interleaved processing to qam mode；Second level interleaving treatment module changes the order of the data of input according to counter controls；Total control module is connect with data address generation unit, ping-pong ram memory cell, second level interleaving treatment module, and data address generation module is also connect with ping-pong ram memory module.
Description
Technical field
The present invention relates to communication code field, more particularly, to a kind of applied to orthogonal frequency division multiplex transmission system
Parallel processing interleaver.
Background technique
With the development of the communication technology and Digital Signal Processing, orthogonal frequency division multiplexing (OFDM, Orthogonal
Frequency Division Multiplexing) mainstream technology of the technology as mobile communication, present forth generation mobile network
What the network communication technology (4G) and WLAN (WLAN, Wireless Local Area Network) were applied is all OFDM skill
Art.The demand of intelligent mobile terminal gradually popularized with bandwidth applications such as online HD video broadcastings, people are to wireless communication
Data rate requirement it is higher and higher, therefore the communication technology needs continue to develop.Currently, wireless communication technique IEEE 802.11
Series is main standard, mainly there is IEEE 802.11, IEEE 802.11b/a/g/n and IEEE 802.11h/i.It is newest
802.11ac the maximum data transmission rate is up to 6.93Gbps.In mobile communication technology, newest LTE-A the maximum data transmission
Rate reaches 600Mbps.The communication standard of these high data transmission rates sends in physical layer at it and generally requires reliable high speed
Interleaver encoded.
So-called intertexture is that a kind of technology of data processing use is carried out in communication system, is substantially exactly to change information bit
A kind of mode of content of the data structure of string without changing data.Mobile radio telecommunications can be in variable-parameter channel on land, transmission
Data are that mistake often occurs in a cluster, this is because continuing the bit that longer deep fade valley point influences whether adjacent a string
Data.When channel decoding, a string of loss data converts can not can only be detected and are corrected single mistake or less
Long mistake.It solves this problem and needs interleaving technology.Interleaving technology is exactly the bit data string by a frame or a symbol
Combination is rearranged according to certain formula, is that adjacent bit data string is become non-conterminous, sequence originally is upset,
Even if losing one in transmission to go here and there greatly, these mistakes can also be become to single or very short Bit String mistake.Again by entangling
Wrong function is restored to original information.
The development of the communication technology be greatly improved data transmission throughput, data throughput from 2Mbps to 54Mbps to
300Mbps, even up to 6.93Gbps；This all proposes higher requirement to Base-Band Processing data, and interleaver is its in base band
In a module, coordinates data transmit throughput under, it is contemplated that the parameters such as actual performance, power consumption, delay, area, serially
The realization of interleaver requires data processing rate excessive, will cause that overall power is excessively high, however the property of the interleaver of parallel processing
Energy can be especially prominent, and the interleaver for designing parallel processing is most important.
There are two types of methods in hardware realization for traditional interleaver, are look-up table and address method of formation respectively, look-up table is
The address that displacement is finished writing on preparatory ROM writes data into RAM by reading address on ROM, then sequentially reads number
According to.This hardware implementation method is simple, but cost is that a large amount of ROM resources are depleted, and it is larger to integrate area.But it is most of at present to hand over
It knits device and all uses address method of formation, be exactly according to formula, intelligence generates required address, however is much using address method of formation
Serial input Serial output, can not be according to input and output the characteristics of, parallel output or Serial output, and in high data throughput
Under rate, higher operation clock is needed.This is often very unfavorable to low power dissipation design.
Summary of the invention
In order to overcome above-mentioned disadvantage, needs to propose a kind of new method for interweaving in communication data coding, utilize friendship
The rule knitted, intelligently according to the demand of input and output or Serial output or parallel output.The purpose of the present invention is to provide one
Kind is applied to the parallel processing interleaver of orthogonal frequency division multiplex transmission system, and the interleaver is using parallel processing and has complexity
Lower feature is for handling coded data in orthogonal frequency division multiplexing (OFDM) Transmission system, its main feature is that allowing parallel
Parallel output is inputted, is interleaved by parallel, faster than serial process, power consumption is lower.
In order to achieve the above objectives, The technical solution adopted by the invention is as follows:
A kind of parallel processing interleaver applied to orthogonal frequency division multiplex transmission system, wherein orthogonal frequency division multiplexing transmission system
System includes a transmitter, and transmitter handles coded data using parallel interleaver, and the parallel processing interleaver includes one, three
Grade interleaving treatment module, second level interleaving treatment module and total control module；
Described one, three-level interleaving treatment module interweaves and three-level intertexture for handling level-one, wherein at one, three-level intertexture
Managing module includes data address generation unit and ping-pong ram memory cell；
Data address generation unit, for the unit for generating read/write address, main read/write address, which generates, uses 3 parameters
(the respectively columns of the length of symbol, intertexture, intertexture line number) controls；The functions such as control row write column reading respectively.
Ping-pong ram memory cell, the ping-pong ram memory cell by ping-pong operation, write data into read simultaneously into
Row；In the ping-pong ram memory cell, each Pingpang Memory includes two groups again, every group of storage organization for having 6 RAM, described
Ping-pong ram memory cell, ping-pong ram is controlled by the address that above-mentioned data address generation unit generates, i.e. control is specific
For some RAM in RAM group for being written which table tennis data, the interleaving data output only need to control, which organizes RAM to export
6 data.
The second level interleaving treatment module, for being interleaved processing to qam mode；The second level interleaving treatment mould
Block changes the order of the data of input according to counter controls；
Total control module is connect with data address generation unit, ping-pong ram memory cell, second level interleaving treatment module, on
Data address generation module is stated also to connect with ping-pong ram memory module.
Preferably, for the total control module according to the index value of transmission, controlling each of parallel processing interleaver can
Variable element, maximum value each subcarrier the included number of coded bits N relevant to modulation system including individual count deviceBPCPS。
Preferably, need to carry out convolutional encoding and puncturing process, data warp before the orthogonal frequency division multiplex transmission system
It is exported more by the convolutional encoding of parallel processing with punctured after crossing convolutional encoding and puncturing process by serially switching to parallel, or again
The parallel data of position；
Parallel data is input to parallel processing interleaver, then parallel output gives modulation mapping；
Parallel data is input to parallel processing interleaver, and enable signal is opened, with high position data storage a to ping-pong ram
In upper one group of RAM, low data is stored to next group of RAM in a ping-pong ram, and according to modulation system, every group of RAM is opened
How many a RAM；When output, generates address and control every group of RAM circulation output.
It is described to utilize ping-pong structure, realize continuous pile line operation.
Compared with prior art, the interleaver advantage of the invention is: on the one hand can carry out once reading and writing and complete
Interweave, greatly reduces the expense of RAM multi-pass operation；And the interleaver can breakpoint handle data, on the other hand, parallel
Amount of interleaver can have more high bandwidth to handle data, meet the needs of high speed operation, can also be intelligently according to modulation system
Output digit is controlled, meets the modulation system of OFDM.The interleaver can be realized that work time delay is small, and dynamic power consumption is low, hardware
Complexity is low, and performance is more excellent in WLAN.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the single fisherman's knot composition of the interleaver of parallel processing of the present invention.
Fig. 2 is the level-one interleaving principle figure of the interleaver of parallel processing of the present invention.
Fig. 3 is the second level interleaving principle figure of the interleaver of parallel processing of the present invention.
Fig. 4 is the Launching Model schematic diagram for the OFDM transmission machine that the interleaver of parallel processing of the present invention is applicable in.
Fig. 5 is the exemplary diagram of the input bit data flow of the interleaver of parallel processing of the present invention.
Fig. 6 is storage organization example and intertexture operating method in the level-one interleaving block of the interleaver of parallel processing of the present invention
Exemplary diagram.
Fig. 7 is that the level-one interleaving block read/write address of the interleaver of parallel processing of the present invention generates schematic diagram.
Fig. 8 is the intertexture operation side of 64QAM modulation system in the second level interleaving block of the interleaver of parallel processing of the present invention
Method schematic diagram, (a) are the first transformation of 64QAM, are (b) second of transformation of 64QAM.
Specific embodiment
It is right below in conjunction with attached drawing 1~8 and embodiment in order to be more clear the objectives, technical solutions, and advantages of the present invention
The present invention is further described from principle and structure.It is worth noting that, specific example discussed below is only used for solving
Summary of the invention is released, is not intended to limit the present invention.
By taking the regular interleaver of 802.11a/g/n/ac series as an example, the principle is as follows:
In 802.11a/g/n/ac transmission, transmission data can divide multiple OFDM symbols, and each OFDM symbol passes through
Cross identical coded treatment；According to different modulation systems, OFDM symbol amount of bits also there are many, specifically, being by effective
The quantity and single sub-carrier number of coded bits (N of data subcarrierBPCPS, it is related to modulation, for example, by using 64QAM modulation system
When be " 6 ") be multiplied obtain.And the interleave depth of an OFDM symbol is equivalent to the bit number of an OFDM symbol in intertexture.
According to agreement, in a spatial flow, BPSK, QPSK need to only carry out first order interleaved transforms, 16QAM, 64QAM, 256QAM etc.
It needs to carry out second level interleaved transforms.If the quantity of spatial flow is more than 1, need to carry out third level interleaved transforms.
Its principle formula of the interleaver of parallel processing in the present invention is defined according to 802.11a/g/n/ac, and such as first
Grade, effect are to guarantee that adjacent coded-bit is mapped on non-conterminous subcarrier, and specific transformation for mula is as follows:
Wherein NCOLFor intertexture columns, NCBPSFor the bit coded number of each OFDM symbol, NROWFor intertexture line number, k=0,
1.....,NCBPS-1。
It is as shown in Table 1 below:
1 interleave parameter of table
| NCOL | NROW | NORT | |
| 802.11a 20MHz | 16 | 3×NBPSCB | 0 |
| 802.11n 20MHz | 13 | 4×NBPSCB | 11 |
| 802.11n 40MHz | 18 | 6×NBPSCB | 29 |
| 802.11ac 80MHz | 26 | 9×NBPSCB | 58 |
Note: parameter is all based on spatial flow, less than equal to 4.
2 N of tableBPCPSParameter
| BPSK | QPSK | 16QAM | 64QAM | |
| NBPCPS | 1 | 2 | 4 | 6 |
Second level interleaved transforms are the high significance bit and low order for so that adjacent bit is alternately mapped to constellation, to keep away
Exempt from the presence of continuous low reliability bits；It is only carried out in 16QAM and 64QAM, specific transformation for mula are as follows:
Wherein
Third time displacement is known as frequency conversion, for reducing the correlation between multiple antennas adjacent encoder data stream bits,
Specific transformation for mula are as follows:
Wherein 1≤iss≤NSS, NSSFor spatial flow quantity, NROTFor twiddle factor.
Above formula is 802.11a/g/n agreement defined interleaved transforms rule, no matter how hardware is realized, transformation
As a result must be consistent, the interleaver of parallel processing of the present invention is designed according to above-mentioned formula, specific to design module frame chart such as Fig. 1 institute
Show；Implementation of the invention will be described below:
Shown in level-one interleaved transforms principle such as formula (1), it can be described as the Block Interleaver of a matrix, line number
For NROW, columns NCOL, it is illustrated in figure 2 the matrix diagram of level-one interleaving procedure, actual effect is according to certain
Rule compositor separates adjacent bit data；Top shown in Fig. 2 is divided into the data for the preceding input matrix sequence that interweaves, middle part
It is divided into the matrix of interleaving procedure, lower part is divided into the data of output matrix sequence after intertexture.S in figurenBit data is represented, and
N represents the serial number at place before intertexture.Such as S34Indicate that position of the data where before intertexture is the 34th.(the sequence in Fig. 2
It is from left to right, from top to bottom).
In conjunction with above-mentioned, according to table 1, the quantity of the coded-bit data of each OFDM symbol meets NROW×NCOLMatrix
Format.Shown in Fig. 2, by taking 802.11n 40M 16QAM modulation system as an example, the wherein N of matrixROWAnd NCOLRespectively 24 and 18,
Compare level-one interleaved transforms before and after Data Position variation, it can be considered that level-one interleaved transforms rule be by row write by column,
Similarly, other modulation systems are same；Fig. 3 and formula (2) show second level interleaving principle, only in qam mode
Middle ability is useful, Fig. 2 show 16QAM modulation system example (top of same Fig. 2 be divided into second level interweave before matrix sequence
Data, lower part is divided into the data of the matrix sequence after second level interweaves), transposed matrix after being interweaved according to above-mentioned level-one come into
Row transformation, one has total NCOLIt goes, bit data position remains unchanged in odd-numbered line, per adjacent two bit datas in even number line
Position swaps；The second level interleaving principle of another 64QAM modulation system is with first in one group, one group of every 3 behavior
Row remains unchanged, and per adjacent 3 bit datas, circulation is moved to the left one in the second row, and per adjacent 3 bits in the third line
Circulation moves right one；The second level interleaved transforms of 64QAM are so accomplished analogously.
It is provided according to the agreement of 802.11n and 802.11ac, if the quantity of spatial flow is greater than 1, needs to carry out third
Grade interleaved transforms that is to say that frequency rotates, and according to agreement and formula (3), entire OFDM symbol bit data carries out cyclic shift.
Specific value is as shown in table 3 below, and the 40MHz displacement numerical value in 802.11n is listed in table.
Table 3
Fig. 4, which is shown, is adapted for carrying out OFDM transmission machine transmitting terminal model of the invention, it shall be noted that be the OFDM
Conveyer transmitting terminal model may further include more modules.The conveyer transmitting terminal at least should include before interleaver
Punctured module and convolutional encoder module are operated by punctured module and convolutional encoder module, are conveyed to the ratio that interleaver is 2
Special data.It is digital modulation module after the interleaver, according to different modulating in modulation module, the bit of multidigit will be inputted
Data (BPSK:1, QPSK:2,16QAM:4,64QAM:6) are converted into 16 signed number evidences, are allowed to be mapped to
On the subcarrier of effect.After the completion of the OFDM symbol modulation, it is inserted into pilot tone, then carry out inverse fast Fourier transform (IFFT), with
Just the signal of frequency domain is converted to the signal of time domain.By resulting time-domain signal insertion protection interval and windowing process is carried out, most
Data are sent out by antenna by digital-to-analogue conversion DAC and RF module afterwards.Parallel processing interleaver of the invention is in OFDM transmission
The advantage that machine transmitting terminal is embodied is, relative to serial process interleaver, can omit de-interleaver module front and rear end and goes here and there
Conversion is operated with serioparallel exchange.
It is currently preferred interleaver designs module shown in Fig. 1, this two big module is mainly connected to by total control module,
One, three-level interleaving treatment module and second level interleaving treatment module；Wherein one, raw comprising data address in three-level interleaving treatment module
At unit, ping-pong ram unit；Specific data flow is bit data by entering total control module, and total control module is data
The writing address and bit data of location generation unit are transmitted to ping-pong ram unit, and ping-pong ram unit is stored according to the present situation
In RAM (RAM0, RAM1), after the bit data of an OFDM symbol is filled with, the address read is generated at once and by bit number
It is transmitted to second level interleaving block according to reading, in second level interleaving block, after bit data transformation, number is exported from total control module
According to.
Parallel processing interleaver of the invention, by taking 802.11n 40MHz as an example, random access memory (RAM) organizes structure such as
Shown in Fig. 1, upper part with lower part be it is the same, designed using table tennis, double RAM blocked operations carry out the biography of seamless data
It is defeated, meet the requirement of high-throughput.Each Pingpang Memory device is divided into two groups again, and every group includes 6 and individually deposit at random
Reservoir, wherein the length of each memory be 64 (actually using is 54, its length be according to used standard determine
).Specifically, as shown in fig. 6, being the structure of each Pingpang Memory device, upper one group is the height for storing two bit datas of input
Position, next group is the low level for storing two bit datas of input.6 memories inside each memory group are not necessarily
It is all turned on write-in, but according to NBPCPSValue determine to open how many a memories, when constellation is modulated to 64QAM,
NBPCPSValue be then 6, indicate that 6 memories need to be written but be only sequentially written one by one；Only when needing to read,
6 memories can just work at the same time.
Fig. 5 is the sequence of parallel 2 input bit data, and wherein S is data value, the current row of input of lower target digital representation
Sequence ordinal number.The input bit data are come in structure as shown in Figure 5.The parallel bit data of input enter such as Fig. 6 institute
The accidental memory structure shown is sequentially written according to provided address.All random access memory of Fig. 6 share a writing address,
As shown in fig. 7, in addition there are one RAM counters 703 writes to control by which RAM.Specifically, the writing address of generation is to work as
Preceding counter 701 6 times (be to move to left two values for itself and add to move to left one value in hardware realization, displacement realizes 6 times,
Exempt multiplier) along with the value of another counter 702, the upper limit value of counter 701 is NCOLHalf (input
Bit data is 2), and the upper limit value of counter 702 is 6.The two counter cycle counts are primary, can be generated 54 and write
Enter address.In addition control address also needs the value of RAM counter 703, in 802.11n 40MHz, whenever counter 701 is equal to
When 9, count is incremented for RAM counter 703, whenever the value that counter 701 is equal to 9 and RAM counter 703 is equal to previous OFDM symbol
NBPCPSWhen value, count is incremented for counter 702.Therefore 6 × 9 × 2 × N is written altogetherBPCPSA bit data, meets 802.11n
The number of coded bits of the standard OFDM symbol of 40MHz.Actually write operation can briefly, in NBPCPSWhen greater than 1, often
9 data are written and go to next RAM, until data write.
In parallel processor of the invention, when every data for having stored an OFDM symbol, read operation is carried out at once, specifically
Ground, read address generate it is similar with write address, as shown in part under Fig. 7,6 times of nonce counter 705 with another counter 706
Value be added obtain, it is different, joined RAM group counter 707 control read which organize RAM.Specifically, with counter
On the basis of 706, when counting down to 6, RAM group counter 707 negate (RAM group counter 707 is one, because only that
Two groups of RAM), only when counter 706, which is equal to 6 and RAM group counter, is equal to 1, counter 705, which counts, just adds 1.So follow
Ring is primary, raw 108 addresses of common property.Briefly, one group of output 6 times upper first in Fig. 6, then arrive next group of output 6 times again
Return to one group of output 6 times, such passes.It should be noted that read operation is that 6 parallel-by-bits export every time, it is by Fig. 6
In 6 common output datas of RAM, the RAM that take less than in some modulation mappings carry out it by total control module altogether
Shielding, therefore export and can intelligently determine output digit according to mapping mode is modulated, to realize parallel output to next
Module carries out map modulation.As shown in fig. 6, first group of 6 data of output effect are S under 64QAM modulation system0,0S0, 18S0,36S0,54S0,72S0,90, second group is S1,108S1,126S1,144S1,162S1,180S1,198, it can be seen that the data break of reading is
Intertexture column N corresponding to 18 namely 802.11n 40MHzCOL, realize the effect write described in formula (1) and read by column line by line.Class
As, other OFDM modes, such as 802.11a, 802.11ac etc. can be by the maximum values of modification read-write counting come real
Existing identical function.
Since existing communication standard all joined MIMO technology (Multiple Input Multiple Output), it is therefore desirable to the third level be added
The interleaved transforms of the third level are put into before the second level interweaves and the by interleaved transforms, the interleaver of the parallel processing that the present invention designs
After level-one interweaves.In conjunction with above-mentioned read operation, it is assigned to the initial value of read operation, it is made to carry out circulative shift operation.Table 3 is basis
The displacement numerical value that formula (3) acquires specifically enters and because interleaver of the invention is two according to the difference of modulation system
Parallel output, so numerical value will be shifted divided by 2 × NBPCPSThe address of initial value is obtained, if remainder is 0, is meant that just
Initial value uses upper one group of RAM, if remainder is 1, means that initial value uses next group of RAM.
Entire read/write address generation unit is the most important part of interleaver, and interleaver of the invention can make to interweave one
First and third level intertexture are completed in secondary read-write, are avoided and are wasted a large amount of RAM resource because of multi-level pmultistage circuit.And it can will delete
Two bit data parallel memorizings that complementary modul block or stream parsing module transmit, further according to modulation system, intelligently output needs
The data of modulation.Entire element circuit is realized simple, only need to avoid multiplication, division by simply negating and add operation
Arithmetic operation, therefore hardware consumption resource is relatively low and complexity is low.
Interweave completing the first order with after third level intertexture, starts to carry out second level interleaved transforms.Described above one, three-level
The data of interleaver transmission are 6, therefore input to second level interleaver is also 6, but for BPSK modulation system
Highest order is only used, actually remaining 5 data is invalid, and similarly, QPSK only uses the two bits of highest order,
16QAM only uses highest four, and 64QAM then utilizes 6 all data.The second level, which interweaves, only has 16QAM modulation
What mode and 64QAM modulation system needed to carry out, as shown in the intertexture of the preceding segment description second level, phase is controlled whether by counter
Mutual data are changed to reach.As shown in fig. 7, for second level two kinds of mapping modes of intertexture of 64QAM digital modulation, the first shown side
Formula, front and back three is respectively circulated up shifting one in every input six, and shown second method, front and back three in every input six
Respectively circulation moves one downwards for position.It by shift result or is done nothing according to controller, resulting result is via total
Control module, which is exported, modulates mapping block to the next module to interweave inside OFDM transmitter.
In conclusion interleaver provided in an embodiment of the present invention, the intertexture that only is completed by once reading and writing data, and
Realize that two parallel-by-bits input, the implementation method of multi-bit parallel output, the interleave and deinterleave of compatible various protocols realizes that hardware is multiple
Miscellaneous degree is extremely low.It is suitable for the processing of high data throughput.
It should be noted that although only describing the interleaver case study on implementation for being applicable in 802.11n 40MHz mode, it should
With being not limited in these modes.The present invention can be also applicable in the context of other possible operation modes, for example, 802.11a or
Person 802.11ac etc..
Special embodiments and examples of the invention are described above.In the description, although can do
The example of the ofdm system of 802.11 series, but ofdm system is based on present invention can also apply to other.It should be noted that
The present invention can merge multiple operation modes, according to the modulation system of input and bandwidth etc., to select the depth to interweave.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (2)
1. a kind of parallel processing interleaver applied to orthogonal frequency division multiplex transmission system, wherein orthogonal frequency division multiplex transmission system
Including a transmitter, wherein transmitter handles coded data using parallel interleaver, which is characterized in that the parallel processing is handed over
Knitting device includes one, three-level interleaving treatment module, second level interleaving treatment module and total control module；
Described one, three-level interleaving treatment module interweaves and three-level intertexture for handling level-one, wherein one, three-level interleaving treatment mould
Block includes data address generation unit and ping-pong ram memory cell；
The data address generation unit, the unit is for generating read/write address；
The ping-pong ram memory cell, the ping-pong ram memory cell by ping-pong operation, write data into read simultaneously into
Row；In the ping-pong ram memory cell, each Pingpang Memory includes two groups, and every group of storage organization for having 6 RAM；
The second level interleaving treatment module, for being interleaved processing to qam mode；The second level interleaving treatment module,
According to counter controls, change the order of the data of input；
Total control module is connect with data address generation unit, ping-pong ram memory cell, second level interleaving treatment module, above-mentioned number
It is also connect with ping-pong ram memory module according to address generation module；
Need to carry out convolutional encoding and puncturing process before the orthogonal frequency division multiplex transmission system, data by convolutional encoding with
It is parallel by serially switching to after puncturing process, or again by the convolutional encoding of parallel processing and punctured output more multidigit and line number
According to；
Parallel data is input to parallel processing interleaver, then parallel output gives modulation mapping；
Parallel data is input to parallel processing interleaver, and enable signal is opened, with high position data storage into a ping-pong ram
Upper one group of RAM, low data is stored to next group of RAM in a ping-pong ram, according to modulation system, every group of RAM open how much
A RAM；When output, generates address and control every group of RAM circulation output.
2. the parallel processing interleaver according to claim 1 applied to orthogonal frequency division multiplex transmission system, feature exist
In the total control module controls each variable element of parallel processing interleaver, including each according to the index value of transmission
The maximum value of a counter each subcarrier included number of coded bits NBPCPS relevant to modulation system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511009122.8A CN105577325B (en) | 2015-12-25 | 2015-12-25 | A kind of parallel processing interleaver applied to orthogonal frequency division multiplex transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511009122.8A CN105577325B (en) | 2015-12-25 | 2015-12-25 | A kind of parallel processing interleaver applied to orthogonal frequency division multiplex transmission system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105577325A CN105577325A (en) | 2016-05-11 |
| CN105577325B true CN105577325B (en) | 2019-07-09 |
Family
ID=55887060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511009122.8A Active CN105577325B (en) | 2015-12-25 | 2015-12-25 | A kind of parallel processing interleaver applied to orthogonal frequency division multiplex transmission system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105577325B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108183729A (en) * | 2018-03-19 | 2018-06-19 | 西安电子科技大学 | The channel interleaving method and system of power line carrier communication based on FPGA |
| CN110247737A (en) * | 2019-07-05 | 2019-09-17 | 北京神经元网络技术有限公司 | The method and apparatus of error correction applied to high-speed industrial communication system |
| CN111478750B (en) * | 2020-03-12 | 2022-10-14 | 普联技术有限公司 | Data parallel interleaving method, terminal equipment and computer storage medium |
| CN111555761B (en) * | 2020-06-10 | 2023-03-28 | 电子科技大学 | Parallel interleaver, deinterleaver and method suitable for 5G-NR |
| CN112737732B (en) * | 2020-12-25 | 2022-10-04 | 中国科学院国家空间科学中心 | In-channel interleaving system for DVB-T transmitter |
| CN113242084B (en) * | 2021-05-11 | 2022-01-11 | 西安电子科技大学 | Parallel self-adaptive interleaving/de-interleaving method for second generation digital satellite broadcasting system |
| CN114629507B (en) * | 2022-01-25 | 2023-08-04 | 海南大学 | Turbo and LDPC code rate matching and interleaver shared storage design method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055549A (en) * | 2009-11-10 | 2011-05-11 | 中兴通讯股份有限公司 | Rate matching device and method for long term evolution system |
| CN102231631A (en) * | 2011-06-20 | 2011-11-02 | 中兴通讯股份有限公司 | Encoding method for Reed-Solomon (RS) encoder and RS encoder |
| CN104617961A (en) * | 2014-12-30 | 2015-05-13 | 中山大学花都产业科技研究院 | Low hardware complexity of interleaver |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7886203B2 (en) * | 2007-09-05 | 2011-02-08 | Mindtree Consulting Ltd | Method and apparatus for bit interleaving and deinterleaving in wireless communication systems |
-
2015
- 2015-12-25 CN CN201511009122.8A patent/CN105577325B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055549A (en) * | 2009-11-10 | 2011-05-11 | 中兴通讯股份有限公司 | Rate matching device and method for long term evolution system |
| CN102231631A (en) * | 2011-06-20 | 2011-11-02 | 中兴通讯股份有限公司 | Encoding method for Reed-Solomon (RS) encoder and RS encoder |
| CN104617961A (en) * | 2014-12-30 | 2015-05-13 | 中山大学花都产业科技研究院 | Low hardware complexity of interleaver |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105577325A (en) | 2016-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105577325B (en) | A kind of parallel processing interleaver applied to orthogonal frequency division multiplex transmission system | |
| CN106465378B (en) | Method and apparatus for transmitting uplink data | |
| CN101958774B (en) | A kind of feedback information sending method and subscriber equipment | |
| CN101621490B (en) | Method for modulation diversity joint codes of OFDM system | |
| CN101394392B (en) | Signal diversifying method for OFDM system | |
| CN103780341B (en) | Wireless communication transmission method based on parallel coding and parallel interleaving | |
| CN101902303A (en) | Device and method for realizing multiplexing of interleaving and de-interleaving | |
| CN101399554A (en) | Interleaving method and de-interleaving method based on LDPC code and apparatus therefor | |
| CN103684666B (en) | The method that time-interleaved reconciliation is time-interleaved is realized in NGB-W communication system | |
| CN107465483A (en) | Exempt from authorized transmissions method and apparatus | |
| CN104868971A (en) | Interleaving mapping method of LDPC code words, and de-interleaving de-mapping method of LDPC code words | |
| WO2016074226A1 (en) | Interleaving processing method and apparatus in wlan system based on ofmda | |
| CN102271402A (en) | Method and device for mapping resource in downlink control channel | |
| CN110035533A (en) | A kind of method for mapping resource and equipment | |
| CN103563320B (en) | For transmitting method, base station and the user equipment of control channel | |
| CN104617961B (en) | A kind of interleaver of low hardware complexity | |
| CN101330487A (en) | Symbol interlacing method, apparatus and terminal equipment | |
| CN101431503B (en) | Space-frequency modulation method for digital television ground broadcasting transmitter | |
| CN109474373A (en) | Deinterleaving method and interlaced device | |
| CN103236905B (en) | For deinterleaving method and the device of OFDM communications | |
| CN104243382B (en) | Symbol interlacing method | |
| CN101383804B (en) | Digital television ground broadcast transmitter modulation method having time-domain training sequence and BICM | |
| CN103297189B (en) | For the adaptive frequency domain deinterleaving method of ofdm system rotation modulation | |
| CN106533610A (en) | Data transmission method, device and system based on dual-carrier modulation (DCM) | |
| CN102299890B (en) | Multimedia broadcasting wireless signal anti-interference framing modulation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |