CN108183729A - The channel interleaving method and system of power line carrier communication based on FPGA - Google Patents
The channel interleaving method and system of power line carrier communication based on FPGA Download PDFInfo
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- CN108183729A CN108183729A CN201810224147.7A CN201810224147A CN108183729A CN 108183729 A CN108183729 A CN 108183729A CN 201810224147 A CN201810224147 A CN 201810224147A CN 108183729 A CN108183729 A CN 108183729A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/54—Systems for transmission via power distribution lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Abstract
The invention belongs to power line carrier communication fields, disclose a kind of channel interleaving method of the power line carrier communication based on FPGA, the channel interleaving method of the power line carrier communication based on FPGA is tested the mixing intertexture and cyclic shift of the intertexture of code, the intertexture of information code, information code and check code；After interleaving treatment, adjacent bit is assigned in different sub-carrier and is transmitted, adjacent bit is mapped in planisphere on relatively important and inferior important position；Meanwhile memoryless channel is converted into, then coordinate the reduction bit error rate with error correcting code by channels with memory to information discretization on time-domain dimension.The present invention is handled by multi-stage interleaving, to information discretization on time-domain dimension, can channels with memory approx be converted into memoryless channel, then can reduce error rate of system with error correcting code cooperation, be improved system reliability.
Description
Technical field
The invention belongs to power line carrier communication field more particularly to a kind of letters of the power line carrier communication based on FPGA
Road deinterleaving method and system.
Background technology
At present, the prior art commonly used in the trade is such：
In the past 20 years, low-voltage powerline carrier communication has been widely used for electric power supervisory control, remote meter reading, family certainly
The fields such as dynamicization.At present, with the development of the concepts such as intelligent grid, energy internet, " four networks one platform ", low-speed power line communication
Society need cannot be met.
Broadband power line carrier communication refers to bandwidth in 2~30MHz, and transmission rate is in the system of more than 1Mbps.Broadband electricity
Powerline carrier communication system, physical layer is using Orthogonal Frequency Division Multiplexing as core.The original intention of power line design is used only to electric power biography
It is defeated, it does not consider to be carried out data transmission with power line, is not dedicated communication channel.It is connected on low-voltage power line numerous and diverse
Electrical equipment, network topology structure is complicated, equipment random access and cuts out, and the characteristic of channel is severe.Power line channel powers on
Noise in the line of force can be divided into colored background noise, sudden noise, random impulsive noise and recurrent pulse noise etc., wherein
Impulsive noise influences the communication quality of power line maximum, it is considered to be it is wrong that burst is generated when power line medium carries out data transmission
Accidentally the main reason for.The frequency selective fading and impulsive noise of power line channel can lead to the bit-errors of bunchiness, and channel
The purpose of intertexture is the information bit for Distributed Transmission, changes message structure to the maximum extent, make the burst error of channel when
Between on spread, coordinate error correcting code, burst error can be reduced, therefore, it is significant to design suitable channel interleaving method.
Currently used deinterleaving method is block interleaved, and block interleaved is that the signal that Error Correction of Coding exports uniformly is divided into m
A code character, each code character contain n segment datas, are arranged in the matrix of m rows n row, are then from left to right sequential read out in a manner of row.
Nowadays, for broadband power line carrier communication system, it is desirable that the application that can be provided is increasingly abundanter, it is therefore desirable to power line
The raising of carrier-wave transmission rate.In view of this, Turbo code is also applied in power-line carrier communication system, and also requirement has more
Adaptive system, reliability higher channel interleaving method meets system needs.
In conclusion problem of the existing technology is：
(1) at present, power line channel characteristic is poor, is susceptible to burst error, and error rate of system is high.
(2) currently used channel interleaving method is block interleaved, and block interleaved can change the structure of information, but only
It is to be interleaved on one-dimensional in time domain or frequency, for the Block Interleaver of m × n, the period is the transmission of m bit interference effects
If process, the m for generating mistake enters error correcting code decoding than that will become successive bits after deinterleave, and decoding certainly will be caused to lose
It loses, so as to generate compared with high bit-error.
(3) in broadband power line communication, bandwidth is larger, and rate is higher, and available subcarrier number is more, and block interleaved is simultaneously
It cannot change to maximum program the prototype structure of information, intertexture, which is not enough, causes adjacent data that may be still within same son
Channel or adjacent sub-channel can still generate continuous mistake.After leading to continuous mistake, error correcting code cannot correct error correction, system misses
Code check is higher, it is impossible to meet the needs of broadband power line communication.
Solve the difficulty and meaning of above-mentioned technical problem：
Nowadays, with the development of the concepts such as intelligent grid, energy internet, " four networks one platform ", for broadband power line
Carrier communication system, it is desirable that the application that can be provided is increasingly abundanter.The broadband power line communication system of high-speed, with it is roomy,
Rate is high, available subcarrier number is more.Power line channel characteristic is poor, the complexity of the requirement of high-speed and system, to system
Performance proposes requirement.And channel interleaving certainly will bring the delay of system, to sum up how factor, find between delay and performance
Balance improves the where the shoe pinches that system reliability is channel interleaving method design.Existing block interleaved method, it is impossible to fully
Upset raw information structure, can still generate consecutive bit-errors, be not suitable for broadband power line channel circumstance.
Channel interleaving method proposed by the present invention has level Four intertexture, maximum under the premise of small delay is introduced as far as possible
Change the prototype structure for changing information so that adjacent bit is fallen as possible on different available subcarriers and effectively by adjacent bit
It is mapped in planisphere on relatively important and inferior important position, is handled by multi-stage interleaving, to information on time-domain dimension
Channels with memory approx can be converted into memoryless channel by discretization, can effectively reduce the generation of continuous mistake, can
Meet the needs of High-Speed Power Line Communication, realize high speed transmission.
Invention content
In view of the problems of the existing technology, the present invention provides a kind of channels of the power line carrier communication based on FPGA
Deinterleaving method and system flow chart.
The invention is realized in this way a kind of channel interleaving method of the power line carrier communication based on FPGA, is examined
Test the mixing intertexture and cyclic shift of the intertexture of code, the intertexture of information code, information code and check code；After interleaving treatment, by phase
Adjacent bit is assigned in different sub-carrier and is transmitted, and adjacent bit is mapped to relatively important and inferior important in planisphere
On position；Meanwhile to information discretization on time-domain dimension, channels with memory are converted into memoryless channel, then with error correcting code
Cooperation reduces the bit error rate.
Further, the channel interleaving method of the power line carrier communication based on FPGA specifically includes：
Step 1 is interleaved check code processing；
Step 2 is interleaved information code processing；
Step 3 carries out mixing intertexture between information code and check code；
Step 4 carries out cyclic shift processing.
Further, the step 1 specifically includes：
First piece of bit of (n-k)/4 of check code is output in block 1, second piece of bit of (n-k)/4 is output to block 2
In, third block (n-k)/4 bit is output in block 3, and the 4th piece of bit of (n-k)/4 is output in block 4；It is equivalent to examine
Code is deposited into the matrix of 4 row of the row of (n-k)/4, wherein, the first row represents block 1, and the second row represents block 2, third block generation
Table block 3, fourth line represent block 4；When data are written, data are sequentially written in by row；
When reading data, the data of four rows are read simultaneously by row, reads since arranging the 0th, adds on first address first
Upper reading step-length S, the sequence for the row that the first round reads for (0,2*S, 3*S ... ...), the first round read altogether ((n-k)/
4)/S row；
Then, the second wheel is carried out, first address is read and adds 1, is read since arranging the 1st, plus a reading on first address
Step-length S, the sequence of row that the second wheel is read are (1,2*S+1,3*S+1 ... ...), and the second wheel reads altogether ((n-k)/4)/S row,
And so on, the reading taken turns by S reads one-hundred-percent inspection code.
Further, the step 2 specifically includes：
First piece of k/4 bit of information code is output in block 1, second piece of k/4 bit is output in block 2, third
Block k/4 bits are output in block 3, and the 4th piece of k/4 bit is output in block 4；It is equivalent to information code being deposited into a k/4
The matrix of 4 row of row, wherein, the first row represents block 1, and the second row represents block 2, and third block represents block 3, fourth line Representative Region
Block 4；When data are written, data are sequentially written in by row；
When reading data, the data of four rows are read simultaneously by row；Wherein, T=k/4, for the intertexture of information code, from one
A deviant offset row start to read, and are read since being arranged offset first, later plus a reading on first address
Step-length S, the sequence for the row that the first round reads is (offset, (offset+S) mod T, (offset+2*S) modT ... ...), the
One wheel reads (k/4)/S row altogether；
Then, the second wheel is carried out, first address is read and adds 1, is read since arranging the 1st, adds one on first address later
Step-length S is read, the sequence of row that the second wheel is read is (offset+1, (offset+S+1) mod T, (offset+2*S+1)
ModT ... ...), the second wheel reads altogether (k/4)/S row, and so on, the reading taken turns by S reads all information code.
Further, the step 3 specifically includes：
It after check code interweaves, exports as the bit of (n-k)/4, after information code interweaves, exports as k/4 bits, the bit of (n-k)/4
It carries out mixing intertexture with k/4 bits；It is information code that output result, which is preceding 4 bit, then 4 bit trial code, and so on, it completes
Interleaving process between check code and information code；
The serioparallel exchange, including：K bit information codes are become into the number that k/4 bit wide is 4 bits after serioparallel exchange
According to, by (n-k) bit trial code become after serioparallel exchange (n-k)/4 bit wide be 4 bits data；By this n/4 number
According to alternately exporting, information code then verifies that code preceding, and so on；
The step 4 specifically includes：
By step 3 treated data, according to 0 to 7 numbering cycles, each two nibble adjustment sequence successively, for
Marked as 0 and 1, direct output is not handled, for label 2 and 3, ring shift right 1, for label 4 and 5, ring shift right 2,
For label 6 and 7, ring shift right 3；Carry out parallel-serial conversion output again later.
Another object of the present invention is to provide a kind of channel of the power line carrier communication based on FPGA described in realize to hand over
The computer program of organization method.
Another object of the present invention is to provide a kind of channel of the power line carrier communication based on FPGA described in realize to hand over
The information data processing terminal of organization method.
Another object of the present invention is to provide a kind of computer readable storage medium, including instruction, when it is in computer
During upper operation so that computer performs the channel interleaving method of the power line carrier communication based on FPGA.
Another object of the present invention is to provide a kind of channel interleaving system packet of power line carrier communication based on FPGA
It includes：
Check code interleave unit interweaves to check code using RAM and ping-pong structure；
Information code interleave unit interweaves to information code using RAM and ping-pong structure；
Interleave unit is mixed, for serioparallel exchange, mixing intertexture is carried out between information code and check code；
Circulative shift operation unit, for carrying out circulative shift operation, parallel serial conversion later.
Another object of the present invention is to provide a kind of channel equipped with the power line carrier communication based on FPGA
The information data processing terminal of interlacing system.
In conclusion advantages of the present invention and good effect are：
The present invention test the intertexture of code, the intertexture of information code, information code and check code mixing interweave and cycle
Displacement.After interleaving treatment, effectively adjacent bit is assigned in different sub-carrier and is transmitted, while effectively by adjacent bit
Being mapped on relatively important and inferior important position, can effectively reduce the influence that frequency declines to system in planisphere.This
Invention is handled by multi-stage interleaving, to information discretization on time-domain dimension, can channels with memory approx be converted into nothing
Memory channel, then error rate of system can be reduced with error correcting code cooperation, improve system reliability.
For the Block Interleaver of m × n, the period for m bit interference effects transmission process, generates the m ratios of mistake
It will become successive bits after deinterleave and enter error correcting code decoding, decoding failure certainly will be caused.Block interleaved compared to m × n
Device, the present invention have more advantages, and the technology comparison of block interleaved and the present invention are as shown in table 1：
Table 1
Current effective method is to carry out the biography of data using multicarrier using Orthogonal Frequency Division Multiplexing (OFDM) system
It is defeated.Power line channel has frequency selectivity, and when some band interference is big, data can all occur on the subcarrier of the frequency range
Mistake can generate frequency selective fading, lead to the bit of consecutive to generate mistake.The channel based on FPGA of the present invention is handed over
Organization method can ensure that adjacent bit can be fallen after being modulated by OFDM on non-conterminous subcarrier, while can cause phase
In adjacent bit map to the relatively important and secondary important planisphere of planisphere.After intertexture, maximization has disperseed original continuous
Bit, after being handled by deinterleaving, disperse errors, still within the scope of the error correction of error correcting code, so as to mitigate fading channel
Influence to system performance.
The present invention is severe for power line carrier communication channel transfer characteristic, using FPGA resource, proposes channel interleaving side
Channels with memory on time-domain dimension, approx can be converted into memoryless channel, are made by method with the burst error of discrete channel
The error correcting code that random error must be entangled can be used in power-line carrier communication system.By the processing of channel interleaving, then coordinate phase
The error correcting code answered, increases substantially the availability of frequency spectrum at the shortcomings that power line carrier communication characteristic of channel can be overcome poor, so as to profit
Effective communications are carried out with power line.
The emulation experiment of the present invention shows to input information code and check code using particular bit, and information code 0,1 is alternate
128 bits, check code are also 0,1 alternate 128 bit, and parity_out is that check code interweaves as a result, data_out is information
Code interweaves as a result, da_pa_out, which is information code and check code, mixes intertexture as a result, DP_ND is intertexture final output result.It is defeated
Go out twice that clock CLK3 is input clock CLK1, it can be seen that intertexture result before this 64 bits 0, then be the 1 of 64 bits, connect
And be the 0 of 64 bits, then the 1 of 64 bits, it is as a result consistent with Matlab results, it is correct.
Description of the drawings
Fig. 1 is the channel interleaving method flow chart of the power line carrier communication provided in an embodiment of the present invention based on FPGA.
Fig. 2 is the channel interleaving system schematic of the power line carrier communication provided in an embodiment of the present invention based on FPGA.
Fig. 3 is inspection code interleaver hardware realization block diagram provided in an embodiment of the present invention.
Fig. 4 is information code interleaver hardware realization block diagram provided in an embodiment of the present invention.
Fig. 5 is information code provided in an embodiment of the present invention and check code mixed interleaver hardware realization block diagram.
Fig. 6 is cyclic shift hardware realization block diagram provided in an embodiment of the present invention.
Fig. 7 is whole simulation result figure provided in an embodiment of the present invention.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to embodiments, to the present invention
It is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not used to
Limit the present invention.
In the prior art, power line channel characteristic is poor, is susceptible to burst error；Error rate of system is high.
With reference to concrete analysis, the invention will be further described.
As shown in Figure 1, the channel interleaving method of the power line carrier communication provided in an embodiment of the present invention based on FPGA, profit
Channel interleaving is realized with Verilog programs, and the realization of the channel interleaving method mainly includes following steps：
The first step is interleaved check code processing.
Second step is interleaved information code processing.
Third walks, and mixing intertexture is carried out to information code and check code.
4th step carries out cyclic shift processing.
The FPGA realizations of the channel interleaving method of the power line carrier communication include the following steps：
Step 1 interweaves to check code using RAM and ping-pong structure.
Step 2 interweaves to information code using RAM and ping-pong structure.
Step 3, serioparallel exchange carry out mixing intertexture between information code and check code.
Step 4 carries out circulative shift operation, later parallel serial conversion.
The step 1 specifically includes：
Assuming that being that information code and check code transmit out respectively after channel channel coding, information code length is k bits, is examined
Code length is (n-k) bit.The design is 1/2 mainly for code check.This step is interleaved place for (n-k) bit trial code
Reason.
First piece (bit of (n-k)/4) of check code is output in block 1, second piece (bit of (n-k)/4) is output to
In block 2, third block (bit of (n-k)/4) is output in block 3, and the 4th piece (bit of (n-k)/4) is output in block 4.Deng
Valency in the matrix that check code is deposited into 4 row of the row of (n-k)/4, wherein, the first row represents block 1, and the second row represents block
2, third block represents block 3, and fourth line represents block 4.When data are written, data are sequentially written in by row.When reading data, by row
The data of four rows are read simultaneously, is read since arranging the 0th first, reads step-length S plus one on first address later, in this way
The sequence for the row that the first round reads is (0,2*S, 3*S ... ...), and the first round reads altogether ((n-k)/4)/S row；Then, it carries out
Second wheel reads first address and adds 1, i.e., is read since arranging the 1st, reads step-length S, the second wheel plus one on first address later
The sequence of the row of reading is (1,2*S+1,3*S+1 ... ...), and the second wheel reads altogether ((n-k)/4)/S row, and so on, lead to
Cross the reading of S wheels, you can read one-hundred-percent inspection code.Wherein, relevant parameter is shown in Table 1.
Step 2 specifically includes：
This step is interleaved processing for k bit trial codes.First piece (k/4 bits) of information code is output to block
In 1, second piece (k/4 bits) is output in block 2, and third block (k/4 bits) is output in block 3, the 4th piece (k/4 bits)
It is output in block 4.It is equivalent to information code being deposited into the matrix of 4 row of k/4 row, wherein, the first row represents block 1, the
Two rows represent block 2, and third block represents block 3, and fourth line represents block 4.When data are written, data are sequentially written in by row.It reads
When going out data, the data of four rows are read simultaneously by row.For convenience of description, T=k/4 is defined.For the intertexture of information code, it is not
It reads, but to be read since being arranged a deviant offset since arranging the 0th, read since being arranged offset first,
Step-length S is read plus one on first address later, the sequence for the row that such first round reads is (offset, (offset+S)
Mod T, (offset+2*S) modT ... ...), the first round reads altogether (k/4)/S row；Then, the second wheel is carried out, reads first ground
Location adds 1, i.e., is read since arranging the 1st, reads step-length S, the sequence of row that the second wheel is read plus one on first address later
For (offset+1, (offset+S+1) mod T, (offset+2*S+1) modT ... ...), the second wheel reads altogether (k/4)/S
Row, and so on, the reading taken turns by S, you can read all information code.Wherein, relevant parameter is shown in Table 2.
Table 2
| Information code (bit number) | Deviant | Step-length |
| 128 | 16 | 4 |
| 576 | 72 | 16 |
Step 3 specifically includes：
It after check code interweaves, exports as the bit of (n-k)/4, after information code interweaves, exports as k/4 bits, the two is carried out
Mixing interweaves.Output result should be preceding 4 bit as information code, then 4 bit trial code, and so on can be completed check code and
Interleaving process between information code.
Using serioparallel exchange, k bit information codes are become into the data that k/4 bit wide is 4 bits after serioparallel exchange, it will
(n-k) bit trial code becomes the data that (n-k)/4 bit wide is 4 bits after serioparallel exchange.Present processing is sought to
This n/4 data is alternately exported, information code then verifies that code preceding, and so on.
It is 4 using a bit wide, depth is the simple twoport distribution RAM (DRAM) of n/2, and n/2 data are regular
Write-in, sequentially reads later.Specifically, the generation of writing address is sequence, using mould n/2 counters, but
Be write-in content dina it is alternately to change, dina information codes before this, are check code later, and so on.
Step 4 specifically includes：
By step 3 treated data, according to 0 to 7 numbering cycles, each two nibble adjustment sequence successively, for
Marked as 0 and 1, direct output is not handled, for label 2 and 3, ring shift right 1, for label 4 and 5, ring shift right 2,
For label 6 and 7, ring shift right 3.Data later are handled successively by this rule.Carry out parallel-serial conversion output again later.Tool
Body rule is as shown in table 3.
Table 3
| Export nibble serial number | Shift mode |
| 0 or 1 | b0b1b2b3 |
| 2 or 3 | b3b0b1b2 |
| 4 or 5 | b2b3b0b1 |
| 6 or 7 | b1b2b3b0 |
In power line carrier communication, current effective method is using Orthogonal Frequency Division Multiplexing (OFDM) system, is utilized
Multicarrier carries out the transmission of data.The channel interleaving method based on FPGA of the present invention can ensure adjacent bit by OFDM
It can be fallen on non-conterminous subcarrier after modulation, while adjacent bit can be caused to be mapped to the relatively important and secondary weight of planisphere
On the planisphere wanted, so as to mitigate influence of the fading channel to system performance.
Such as Fig. 2, the embodiment of the present invention provides a kind of channel interleaving system of the power line carrier communication based on FPGA and includes：
Check code interleave unit interweaves to check code using RAM and ping-pong structure；
Information code interleave unit interweaves to information code using RAM and ping-pong structure；
Interleave unit is mixed, for serioparallel exchange, mixing intertexture is carried out between information code and check code；
Circulative shift operation unit, for carrying out circulative shift operation, parallel serial conversion later.
With reference to specific embodiment, the invention will be further described.
Assuming that channel coding, using 128 bit lengths, code check is 1/2 coding mode, is exported in result, information code
It is parallel output with check code.
As shown in Figure 1, the realization of the present invention is needed by following steps:
Step 1：The check code of 128 bits is interleaved.
Specifically, the realization of common block interleaved generally realizes interleave function using the read-write of RAM to adjust sequence, adopts
With " out of order write-in, sequentially read " or the method for " being sequentially written in, out of order reading ".
It is conveniently using " being sequentially written in, out of order reading " mode in the present invention.Using CLK1 as clock, position is utilized
Width is 1, and depth is 128 RAM, and the check code of input is stored in RAM in sequence, that is, is sequentially stored into 0~ground of address of RAM
In location 127, the generation unit wadd Generator of writing address can be generated by 128 counter of mould.Take " out of order in reading address
The method of reading " when reading address enable is drawn high, is read out the calculating of address.Based on above-mentioned analysis, code interleaver is examined
The hardware realization block diagram of design is as shown in Figure 3.
The generation that RAM reads address is the key that entirely to design and difficult point.According to check code intertexture thinking and rule
It finds, can be designed that and read scalar/vector radd Generator.Core design such as following formula：
Wadd=cnt1+4cnt2+32cnt3 * MERGEFORMAT (1)
Wherein, it be 3, cnt3 bit wides is 2 that cnt1 bit wides, which are 2, cnt2 bit wides,.The initial value of cnt1, cnt2, cnt3 are 0.
The variation of cnt3 is 0,1,2,3, is then proceeded to by this regular cycles, and when cnt3 is 3, cnt2 adds the variation of 1, cnt2 to be 0,1,
2,3,4,5,6,7, then cnt2 continue by this regular cycles, when cnt2 is 7, cnt1 adds the variation of 1, cnt1 to be 0,1,2,3,
The calculating of 128 reading addresses is realized at this time.It can be calculated according to the formula at this time and read address, key Verilog
Code is as follows：
When reading address calculation, which enables, to be drawn high, the calculating for reading address wadd is proceeded by.It, can by the Code Design
Reading address as 0,32,64,96,4,36,68,100 to calculate ..., 31,63,95,127 are consistent with mentality of designing.
Due to the design using " out of order write-in, sequentially read ", therefore, when a frame data are not completely written to, then cannot
It carries out new data to write out, the data otherwise read will likely can be generated mistake, therefore meeting by the influence of new write-in data
Continuous data can not be handled by leading to the problem of.In view of this problem, the method for solution is exactly using pipeline organization, is utilized
" ping-pong structure " uses two bit wides as 1, and depth is 128 simple dual port RAM, RAM0 and RAM1 is named as, by RAM0
It writes enabled with RAM1 and reads enabled control, realize following process：It is carried out when carrying out write-in data to RAM0, while to RAM1
It reads, data is written when being read out to RAM0, while to RAM1, can ensure the continuous processing of data in this way, and not
Mistake can be generated.
Step 2：128 bit information codes are interleaved.
Information code intertexture, hardware realization block diagram such as Fig. 4 of information code interleaver designs closely similar with the intertexture of check code
It is shown.The main distinction is that the calculating that RAM reads address has a little difference.The core of the calculating of reading address that information code interweaves
Formula is still：
Wadd=cnt1+4cnt2+32cnt3 * MERGEFORMAT (2)
But, in being interweaved due to information code, due to there are intertexture deviant 16, according to mentality of designing, in realization
Certain difference is intertwined with check code.It is 3, cnt3 bit wides is 2 that cnt1 bit wides, which are 2, cnt2 bit wides,.Cnt1, cnt3's is initial
Value is 0, and the initial value of cnt2 is 4.The variation of cnt3 is 0,1,2,3, is then proceeded to by this regular cycles, when cnt3 is 3
When, cnt2 adds the variation of 1, cnt2 to be 4,5,6,7,0,1,2,3, and then cnt2 continues by this regular cycles, when cnt2 is 3,
Cnt1 adds the variation of 1, cnt1 to be 0,1,2,3, realizes the calculating of 128 reading addresses at this time.
In addition to cnt2 initial values difference, it is identical with check code that other calculate reading address code.Therefore, when reading address meter
When calculating enabled draw high, the calculating for reading address wadd is proceeded by.By the Code Design, can calculate reading address is
16,48,80,112 ... 15,47,79,111 are consistent with mentality of designing.In order to handle continuous data, also with " table tennis is tied
Structure " is handled.
Step 3：Information code and check code mixing interweave.
(3a), using serioparallel exchange, 128 bit information codes is become after serioparallel exchange when input clock is CLK1
32 bit wides are the data of 4 bits, and 128 bit trial codes are become the data that 32 bit wides are 4 bits after serioparallel exchange.
Present processing seeks to alternately export this 64 data, and information code then verifies that code preceding, and so on.
(3b) is 4 using a bit wide, and depth is 64 simple twoport distribution RAM (DRAM), and 64 data are had rule
Rule write-in, sequentially reads later.Specifically, the generation of writing address is sequence, using 64 counter of mould, but
Be write-in content dina it is alternately to change, dina information codes before this, are check code later, and so on.After treatment
Data are 64 nibble datas, are handled convenient for the cyclic shift of next stage.Write-in DRAM and the clock of reading DRAM are
CLK2, CLK2 are the two divided-frequencies of CLK1.
By analyzing above, information code and check code interleaver designs are as shown in Figure 5.
Step 4：Cyclic shift processing.
(4a) input clock is CLK2, carries out nibble shifting processing.For marked as 0 and 1, not handling direct output,
For label 2 and 3, ring shift right 1, for label 4 and 5, ring shift right 2, for label 6 and 7, ring shift right 3.It
Data afterwards are handled successively by this rule.
(4b) parallel-serial conversion.Since the data of channel interleaving output will be used further to modulation module, and modulation system
And it is not fixed, it may be possible to which QPSK, 16QAM etc., therefore, the data of information intertexture output should be serial bit stream.After shifting
Data, carry out parallel serial conversion after, export serial bit stream.Clock during output is CLK3, and frequency is four times of CLK2, is
Twice of CLK1.
According to above analysis, the hardware realization block diagram of cyclic shift is as shown in Figure 6.
By more than four steps, using the write-in and reading of the RAM in FPGA, serioparallel exchange, displacement, parallel-serial conversion are utilized
Wait operations that the whole system of channel interleaving can be realized.Using these, have the advantages that logic is simple, time delay is small.
With reference to emulation experiment, the invention will be further described.
As shown in fig. 7, give Verilog analogous diagrams.The figure is one section of simulation waveform of interception, is for the ease of verification
It is no correct, information code and check code are inputted using particular bit, and information code 0,1 alternate 128 bit, check code is also 0,1
Alternate 128 bit, parity_out be check code interweave as a result, data_out be information code interweave as a result, da_pa_out is
Information code and check code mixing interweave as a result, DP_ND is intertexture final output result.It is input clock to export clock CLK3
Twice of CLK1, it can be seen that intertexture result before this 64 bits 0, then be the 1 of 64 bits and be the 0 of 64 bits, then
The 1 of 64 bits, it is as a result consistent with Matlab results, it is correct.
The foregoing is merely the special case of the present invention, i.e. 128 bit of information code, code check 1/2, the situation of 128 bit of check code,
The realization of other situations is similar, only need to change partial parameters.
In the above-described embodiments, can come wholly or partly by software, hardware, firmware or its arbitrary combination real
It is existing.Entirely or partly realized in the form of a computer program product when using, the computer program product include one or
Multiple computer instructions.When loading on computers or performing the computer program instructions, entirely or partly generate according to
Flow or function described in the embodiment of the present invention.The computer can be all-purpose computer, special purpose computer, computer network
Network or other programmable devices.The computer instruction can be stored in a computer-readable storage medium or from one
Computer readable storage medium is transmitted to another computer readable storage medium, for example, the computer instruction can be from one
A web-site, computer, server or data center pass through wired (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)
Or wireless (such as infrared, wireless, microwave etc.) mode is carried out to another web-site, computer, server or data center
Transmission).The computer read/write memory medium can be that any usable medium that computer can access either includes one
The data storage devices such as server, the data center that a or multiple usable mediums integrate.The usable medium can be magnetic Jie
Matter, (for example, floppy disk, hard disk, tape), optical medium (for example, DVD) or semiconductor medium (such as solid state disk Solid
State Disk (SSD)) etc..
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should all be included in the protection scope of the present invention.
Claims (10)
- A kind of 1. channel interleaving method of the power line carrier communication based on FPGA, which is characterized in that the electricity based on FPGA The channel interleaving method of powerline carrier communication is tested the mixing of the intertexture of code, the intertexture of information code, information code and check code Intertexture and cyclic shift；After interleaving treatment, adjacent bit is assigned in different sub-carrier and is transmitted, adjacent bit is reflected It is mapped in planisphere on relatively important and inferior important position；Meanwhile there will be memory to information discretization on time-domain dimension Channel is converted into memoryless channel, then coordinates the reduction bit error rate with error correcting code.
- 2. the channel interleaving method of the power line carrier communication based on FPGA as described in claim 1, which is characterized in that described The channel interleaving method of power line carrier communication based on FPGA specifically includes：Step 1 is interleaved check code processing；Step 2 is interleaved information code processing；Step 3 carries out mixing intertexture between information code and check code；Step 4 carries out cyclic shift processing.
- 3. the channel interleaving method of the power line carrier communication based on FPGA as described in claim 1, which is characterized in that described Step 1 specifically includes：First piece of bit of (n-k)/4 of check code is output in block 1, second piece of bit of (n-k)/4 is output in block 2, Third block (n-k)/4 bit is output in block 3, and the 4th piece of bit of (n-k)/4 is output in block 4；It is equivalent to check code The matrix of 4 row of the row of (n-k)/4 is deposited into, wherein, the first row represents block 1, and the second row represents block 2, and third block represents Block 3, fourth line represent block 4；When data are written, data are sequentially written in by row；When reading data, the data of four rows are read simultaneously by row, is read since arranging the 0th first, one is added on first address A reading step-length S, the sequence for the row that the first round reads is (0,2*S, 3*S ... ...), and the first round reads altogether ((n-k)/4)/S Row；Then, the second wheel is carried out, first address is read and adds 1, is read since arranging the 1st, plus a reading step-length on first address S, the sequence of row that the second wheel is read are (1,2*S+1,3*S+1 ... ...), and the second wheel reads altogether ((n-k)/4)/S row, with this Analogize, the reading taken turns by S reads one-hundred-percent inspection code.
- 4. the channel interleaving method of the power line carrier communication based on FPGA as described in claim 1, which is characterized in that described Step 2 specifically includes：First piece of k/4 bit of information code is output in block 1, second piece of k/4 bit is output in block 2, third block k/4 Bit is output in block 3, and the 4th piece of k/4 bit is output in block 4；It is equivalent to information code being deposited into 4 row of k/4 row Matrix, wherein, the first row represents block 1, and the second row represents block 2, and third block represents block 3, and fourth line represents block 4； When data are written, data are sequentially written in by row；When reading data, the data of four rows are read simultaneously by row；Wherein, T=k/4, it is inclined from one for the intertexture of information code Shifting value offset row start to read, and are read since being arranged offset first, later plus a reading step-length on first address S, the sequence for the row that the first round reads is (offset, (offset+S) mod T, (offset+2*S) mod T ... ...), and first Wheel reads (k/4)/S row altogether；Then, the second wheel is carried out, first address is read and adds 1, is read since arranging the 1st, later plus a reading on first address Step-length S, the sequence of row that the second wheel is read are (offset+1, (offset+S+1) mod T, (offset+2*S+1) mod T ... ...), the second wheel reads altogether (k/4)/S row, and so on, the reading taken turns by S reads all information code.
- 5. the channel interleaving method of the power line carrier communication based on FPGA as described in claim 1, which is characterized in that described Step 3 specifically includes：It after check code interweaves, exports as the bit of (n-k)/4, after information code interweaves, exports as k/4 bits, the bit of (n-k)/4 and k/ 4 bits carry out mixing intertexture；It is information code that output result, which is preceding 4 bit, then 4 bit trial code, and so on, it completes to examine Interleaving process between code and information code；The serioparallel exchange, including：K bit information codes are become into the data that k/4 bit wide is 4 bits after serioparallel exchange, (n-k) bit trial code is become into the data that (n-k)/4 bit wide is 4 bits after serioparallel exchange；This n/4 data is handed over For output, information code then verifies that code preceding, and so on.
- 6. the channel interleaving method of the power line carrier communication based on FPGA as described in claim 1, which is characterized in that described Step 4 specifically includes：By step 3 treated data, according to 0 to 7 numbering cycles, each two nibble adjustment sequence successively, for label For 0 and 1, direct output is not handled, for label 2 and 3, ring shift right 1, for label 4 and 5, ring shift right 2, for Label 6 and 7, ring shift right 3；And so on, carry out parallel-serial conversion output again later.
- 7. a kind of channel interleaving method for realizing the power line carrier communication based on FPGA described in claim 1~6 any one Computer program.
- 8. a kind of channel interleaving method for realizing the power line carrier communication based on FPGA described in claim 1~6 any one Information data processing terminal.
- 9. a kind of computer readable storage medium, including instructing, when run on a computer so that computer is performed as weighed Profit requires the channel interleaving method of the power line carrier communication based on FPGA described in 1~6 any one.
- 10. a kind of channel interleaving method of the power line carrier communication based on FPGA as described in claim 1 based on FPGA Power line carrier communication channel interleaving system, which is characterized in that the channel of the power line carrier communication based on FPGA Interlacing system includes：Check code interleave unit interweaves to check code using RAM and ping-pong structure；Information code interleave unit interweaves to information code using RAM and ping-pong structure；Interleave unit is mixed, for serioparallel exchange, mixing intertexture is carried out between information code and check code；Circulative shift operation unit, for carrying out circulative shift operation, parallel serial conversion later.
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