CN101022286B - Bit scramble parallel processing method and apparatus - Google Patents
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- CN101022286B CN101022286B CN2007100892920A CN200710089292A CN101022286B CN 101022286 B CN101022286 B CN 101022286B CN 2007100892920 A CN2007100892920 A CN 2007100892920A CN 200710089292 A CN200710089292 A CN 200710089292A CN 101022286 B CN101022286 B CN 101022286B
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Abstract
A method for carrying out scrambling-parallel treatment on bit includes expanding value of scrambling code to be negative infinite, moving phase value of bit scrambling code sequence in bit phase value storage towards positive infinite for N sub-traction M numbers of phases and storing them, using M as non-effective bit digit at low bit in the first parallel data sequence and N as bit digit of parallel data sequence, inputting parallel data sequence and using moved bit scrambling code sequence and said parallel data sequence to finalize scrambling-operation.
Description
Technical field
The high speed downlink packet that the present invention relates to Wideband Code Division Multiple Access (WCDMA) (WCDMA) system inserts (HSDPA) technical field, relates in particular to a kind of bit scramble parallel processing method and device.
Background technology
The third generation moves the operating process that partnership (3GPP) normal structure has defined the bit scramble in the processing of WCDMA high speed downlink packet access (HSDPA) symbol level, and is specific as follows:
Use b
Im, 1, b
Im, 2, b
Im, 3..., b
Im, BExpression is input to the bit stream of bit scramble resume module, and wherein B represents the bit number in the bit stream, and i represents transmission channel number, uses d
Im, 1, d
Im, 2, d
Im, 3..., d
Im, BThe bit stream of exporting after the expression bit scramble resume module.
Then the relation between these two bit streams can be expressed as:
d
Im, k=(b
Im, k+ y
k) mod 2 k=1,2 ..., B, wherein mod represents modulo operation, y
kK value for scrambler sequence y generates according to following formula:
In this formula, sequence g={g
1, g
2..., g
16}={ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,1}.
From first formula as can be seen, when carrying out bit scramble, information bit b of every input
Im, k, the bit scramble module obtains corresponding scrambler sequence bit y
k, both carry out the binary addition operation, have just finished the bit scramble operation of this input bit.After the input of full detail bit-order, promptly finished the bit scramble operation of whole code block.
The Transmission Time Interval (TTI) of HSDPA has only 2 milliseconds, need finish whole symbol levels usually and handle in 2 milliseconds.Beat of serial mode is only finished the scrambling of an information bit, and the bit scramble operating time is directly proportional with incoming bit stream length B.Along with the increase of HSDPA service traffics, and the increase that needs the sector number of support, the bit scramble processing time is more and more considerable, makes the processing time of leaving other treatment steps for shorten, and increases the HSDPA symbol level and handles implementation complexity.For addressing this problem, the bit scramble action need adopts parallel processing structure.
For convenience of description, below the degree of parallelism of hypothesis scrambling operation is N, and N is not less than 16.For N less than 16 situation, handle mechanism with N be not less than 16 o'clock similar.
Fig. 1 is the structural representation of bit scramble parallel processing apparatus in the prior art.As shown in Figure 1, it is made up of two parts: scrambler sequence maker 110 and sequence scrambler 120.When first parallel data sequence of a transmission block is imported, an effective new data block indication is provided simultaneously, make scrambler sequence maker 110 export corresponding N bit scrambler sequence y
N* (j-1)+1, y
N* (j-1)+2, y
N* (j-1)+3..., y
(N*j)(j=1), this sequence is input to sequence scrambler 120 and finishes with the scrambling of list entries operation.Data sequence of later every input, the scrambler sequence maker is all exported corresponding scrambler sequence, is input to the sequence scrambler and finishes with the scrambling of list entries operation.
Because the formula that scrambler sequence yk can provide by 3GPP in advance calculates, this sequence is the sequence of an immobilized substance, therefore, in present bit scramble parallel processing apparatus, usually uses a read-only memory (ROM) to store whole scrambler sequence y
kFor degree of parallelism is the situation of N, and phase place is the scrambler sequence y of j
N* (j-1)+1, y
N* (j-1)+2, y
N* (j-1)+3..., y
(N*j)Leave the address (j-1) of this ROM in.The phase information j of input data just can read from ROM and obtain following the corresponding scrambler sequence of parallel data like this.
For the HSDPA business, the full-size of a transport channel data piece is 28800 bits, adds 16 bit cyclic redundancy (CRC) bit, and the maximum memory space that can obtain this corresponding ROM needs 28816 bits.In order to save hardware spending, this ROM also can replace with hardware logic, generates corresponding scrambler sequence in real time according to the data sequence phase information.
Fig. 2 is a scrambler sequence maker hardware logic structure schematic diagram.As shown in Figure 2, it is made up of two parts: 16 bit phase value memories 210 and the new phase value maker 220 of N bit.16 bit phase value memories 210 are used to store the scrambler sequence phase information after a preceding scrambling finishes.During the new parallel data sequence of one of every input, old scrambler sequence phase information outputs to the new phase value maker 220 of N bit from 16 bit phase value memories 210, obtain the scrambler sequence to this new data sequence correspondence.Because scrambling operation degree of parallelism is N, therefore, scrambler sequence under this new phase place is the N bit altogether, the sequence scrambler 120 that it outputs to accompanying drawing 1 is finished the scrambling operation to the data sequence, while to 16 bit phase value memories 210, stores its high 16 bit feedback for next data and uses.When a new transport channel data piece was imported, the new data block indication was effective, and 16 bit values of 16 bit phase value memories, 210 outputs are the scrambler sequence y that the bit scramble of 3GPP regulation and stipulation uses
kY
-15To y
0Deng 16 values.
No matter use ROM also to be to use hardware logic to realize the scrambler sequence maker, when input block size B was the integral multiple of N, existing parallel bit scrambling apparatus can be finished data bit scrambling operation smoothly.But in real system, block size B differs, and to establish a capital be the integral multiple of N.At this moment, the processing before the bit scramble is the Cyclic Redundancy Check operation, and in order to handle conveniently, normally the head in data block increases invalid bit.Like this, when new transport channel data blocks of data begins to enter into the bit scramble module, the N Bit data of first input not necessarily is the effective information bit that needs scrambling all, and the N Bit data of input each time afterwards just is the effective information bit that needs scrambling all.The N Bit data of setting input for the first time is from low bit, and preceding M bit all is invalid bit, and carrying out needs this M bit is abandoned before the bit scramble, makes that the lowest bit of (M+1) bit and first scrambler sequence is y
1Scrambling is carried out in alignment.In order to reach this purpose, two kinds of methods are arranged: first kind is that data sequence is moved, and second kind is that scrambler sequence is moved.
First method is that data sequence is moved, and keeps scrambler sequence motionless.M bit is invalid bit before the data sequence, need be from (M+1) than rising abruptly, and every N bit is formed a new sequence, is input to the sequence scrambler.
Fig. 3 is the structural representation of bit scramble parallel processing apparatus that input data sequence is adjusted.As shown in Figure 3, before input data sequence is input to sequence scrambler 320, increased by two section processes logics: one is the delayer 330 of input data, and it realizes the function to a beat of data data delay; One is data selector 340, and it, is selected with the corresponding N Bit data of scrambler sequence from the input data of N bit with through the last data sequence of N bit that postpones according to invalid bit M value.Because the M value can be at random from 0,1 up to (N-1) value, corresponding expression exists in the data block head does not have invalid bit, exist 1 invalid bit up to there being (N-1) individual invalid bit N kind situations such as (just only having a significant bit), so this data selector 340 selects 1 selector to form by N N.
Second kind of processing method is to keep input data sequence motionless, and scrambler sequence is adjusted.When having M invalid bit at the data block head, before the scrambler sequence that the 3GPP regulation is used, insert M bit arbitrarily, the corresponding y of the individual sequential value of (M+1) of scrambler sequence
1When the scrambler sequence maker uses ROM to realize, the content of ROM storage is fixed, still need to adopt data delay and choice structure among Fig. 3, obtain the sequential value in adjacent two memory addresss simultaneously, from this 2N sequential value, select N value, therefore also need delay cell and data selector unit that selects 1 selector to form by N N of a N bit.
When the scrambler sequence maker uses hardware logic to realize, can not use delay cell, but the data selector unit that selects 1 selector to form by N N is also indispensable.
Fig. 4 is the hardware logic structure schematic diagram of scrambler sequence maker that scrambler sequence is adjusted.Compare with Fig. 2, it is except having increased a data selector 430, also the N bit of Fig. 2 must be revised as the new phase value maker 420 of 2*N bit by new phase value maker, the 16 bit scrambler sequence values that provide are provided its function, generate the scrambler sequence value of its corresponding scrambler sequence phase place 2*N bit afterwards.
When therefore scrambler sequence being adjusted, at least still need to use and comprise N N and select 1 data selector, make first parallel input data of corresponding new transmission block, at last Shu Chu N bit scrambler sequence from low to high, (M+1) bit begins to be only the scrambler sequence y of 3GPP regulation and stipulation
k, just (M+1) bit is y
1, (M+2) bit is y
2, go down successively.
Therefore, when a transport block size B is not the integral multiple of degree of parallelism N, no matter the input data are handled, still scrambler sequence is handled, all need a data selection unit of selecting 1 data selector to form by N N at least, exist to take the many shortcomings of resource.
Summary of the invention
The present invention proposes a kind of bit scramble parallel processing method and device, can solve and take the many problems of resource in the prior art.
For this reason, the present invention takes following technical scheme: a kind of bit scramble parallel processing method, be applicable to that the high speed downlink packet of broadband CDMA system inserts the field, and may further comprise the steps:
A, the value of bit scramble scrambler is expanded to minus infinity;
B, the initial phase place value in the 16 bit phase value memories is moved N to the positive infinity direction subtract M phase place, and store, wherein N is the bit number of parallel data sequence, and M is for being positioned at the invalid bit number of low bit in first parallel data sequence; Step B further may further comprise the steps:
B1, described 16 bit phase value memories load corresponding bit scrambling scrambler sequence y from low to high successively
-N-15To y
-NThe initial phase place value;
B2, obtain the invalid bit number M that is positioned at low bit in first parallel data sequence;
B3, the initial phase adjustment that provides N to subtract M cycle enable useful signal to the initial phase adjuster;
B4, described initial phase adjuster of each cycle move one with the phase place of bit scramble scrambler sequence corresponding in the described 16 bit phase value memories to the positive infinity direction, are input to described 16 bit phase value memories again and store;
The y of the phase value corresponding bit scrambling scrambler sequence of B5, last described 16 bit phase value memory stores
-M-15To y
-M
C, input parallel data sequence utilize bit scramble scrambler sequence and described parallel data sequence after moving to finish the scrambling operation.
In the steps A, described bit scramble scrambler sequence meets following formula:
Wherein, y
kBe k the value of described bit scramble scrambler sequence y, B is the bit number of bit data flow.
Step C further may further comprise the steps:
C1, the described parallel data sequence of input;
C2, the phase value of storing in the described 16 bit phase value memories is outputed to the new phase value maker of N bit, generate the N bit value of bit scramble scrambler sequence;
C3, the N bit value of bit scramble scrambler sequence is input to the sequence scrambler, carries out the scrambling operation with described parallel data sequence.
Further comprising the steps of: C4, with high 16 bit storage of the N bit value of described bit scramble scrambler sequence to described 16 bit phase value memories.
A kind of bit scramble parallel processing apparatus, the high speed downlink packet that is applicable to broadband CDMA system inserts the field, comprise 16 bit phase value memories, the initial phase adjuster, new phase value maker of N bit and sequence scrambler, wherein N is the bit number of parallel data, described 16 bit phase value memories are used to receive new data block indication input signal, the sequence phase information input signal, the signal of initial phase adjuster output also sends scrambling code phase information to described initial phase adjuster and the new phase value maker of described N bit, described initial phase adjuster is used to receive the high order bit signal that initial phase is adjusted enable signal and the new phase value maker of described N bit, the new phase value maker of described N bit is used to export the new scrambler sequence phase value of N bit to described sequence scrambler, the data after described sequence scrambler is used to receive the parallel data sequence and exports scrambling.
Described initial phase adjuster comprises the binary adder of 16 alternative data selectors and 14 input.
In described 16 alternative data selectors, input data in the below of the data selector of bit 15 are the bit 0 in high 16 bits of new scrambler sequence phase value of N bit, and the top input signal is the output signal of described 4 input binary adders; Input data in the data selector of other each bits below are the corresponding bit of high 16 bits of the new scrambler sequence phase value of N bit, and top input data are a high bit of the correspondence of 16 bit phase value memory output signals; When the adjustment of input signal initial phase enables when effective, select the data of top port input; When initial phase place adjustment enables when invalid, select the data of below port input.
The output of described 4 input binary adders is connected to the top input of the alternative data selector of bit 15, the memory space #0, the #2 that are input as 16 bit phase value memories of described 4 input binary adders, the dateout of #3, #5.
Adopted technical scheme of the present invention, when transport block size B is not the integral multiple of degree of parallelism N, mode by the unnecessary phase place of insertion portion before scrambler sequence, make N the N that must use when no longer needing align data in original device or alignment scrambler sequence select 1 data selector unit, and only need the selector of 16 alternatives, thereby reduce the complexity of bit scramble parallel processing structure.
Description of drawings
Fig. 1 is the structural representation of bit scramble parallel processing apparatus in the prior art;
Fig. 2 is a scrambler sequence maker hardware logic structure schematic diagram;
Fig. 3 is the structural representation of bit scramble parallel processing apparatus that input data sequence is adjusted;
Fig. 4 is the hardware logic structure schematic diagram of scrambler sequence maker that scrambler sequence is adjusted;
Fig. 5 is the bit scramble parallel processing apparatus structural representation of this embodiment;
Fig. 6 is the mutual structural representation of signal between 16 bit phase value memories and the initial phase adjuster;
Fig. 7 is the flow chart of bit scramble parallel processing in this embodiment.
Embodiment
Below in conjunction with accompanying drawing, and technical scheme of the present invention is described further by embodiment.
For convenience of description, suppose still in this embodiment that the degree of parallelism of scrambling operation is N, and N is not less than 16.For N less than 16 situation, handle mechanism with N be not less than 16 o'clock similar.
Fig. 5 is the bit scramble parallel processing apparatus structural representation of this embodiment.As shown in Figure 5, the bit scramble parallel processing apparatus in this embodiment comprises the new phase value maker of one 16 bit phase value memory 520, initial phase adjuster 510, N bit 530, a sequence scrambler 540.There are 3 input signals in 16 bit phase value memories 520: 16 bit signals of new data block indication input signal, sequence phase information j input signal, the output of initial phase adjuster, the old scrambling code phase information of 16 bit phase value memories, 520 outputs, 16 bits is to initial phase adjuster 510 and the new phase value maker 530 of N bit.The new phase value maker 530 of N bit receives the old scrambling code phase information of 16 bits from 16 bit phase value memories 520, the new scrambler sequence phase value of output N bit, output to sequence scrambler 540, high 16 bits of the new scrambler sequence phase value of the N bit of new phase value maker 530 outputs of N bit simultaneously also output to the initial phase adjuster.Sequence scrambler 540 is from outside input parallel data and receive the new scrambler sequence phase value of N bit that the new phase value maker 530 of N bit is exported.Initial phase adjuster 510 has initial phase to adjust two inputs of high 16 bit signals of the output of enable signal and the new phase value maker of N bit, and its output signal connects an input as 16 bit phase value memories 520.
Fig. 6 is the mutual structural representation of signal between 16 bit phase value memories and the initial phase adjuster.As shown in Figure 6, be the boundary with the chain-dotted line among the figure, left part is an initial phase adjuster 510, the right side is divided into 16 bit phase value memories 520.The bit #0 of 16 bit phase value memories 520 directly exports, and other each bits also feed back to the preceding data selector of a low bit storage space of initial phase adjuster 510 except exporting, be connected to the top input port of this data selector.Such as bit #14, except exporting, also feed back to the initial phase adjuster, be connected to the top data input pin of the new selector of data of the alternative of bit #13 wherein.
The function of each alternative data selector of initial phase adjuster 510 is: when the adjustment of input signal initial phase enables when effective, select the data of top port input, just the dateout of a corresponding high bit memory in the 16 bit phase value memories 520; When initial phase place adjustment enables when invalid, select the data of below port input, just from the corresponding bit of the output signal of the new phase value maker 530 of N bit.
Fig. 7 is the flow chart of bit scramble parallel processing in this embodiment.As shown in Figure 7, bit scramble parallel processing method may further comprise the steps:
Be the bit scramble scrambler sequence y of 3GPP normal structure definition
kExpand to:
Before the new transport block data input, the indication of input signal new data block is changed to significant level, and it is y that 16 bit phase value memories load the initial phase place value from low to high successively
kY
-N-15To y
-N, i.e. y
-N-15Leave lowest bit in, bit #0; y
-N-14Leave bit #1 in; Go down successively; y
-N-1Leave bit #14 in, y
-NLeave higher bit in, bit #15.
At block size B is not the multiple of degree of parallelism N, and when the low M bit of first parallel data of input was not the information bit that needs, M was exactly the invalid bit number that is positioned at low bit in first parallel data sequence.
Provide the initial phase adjustment of N-M periodic width to enable useful signal, this enable signal makes each alternative data selector in the initial phase adjuster select from the signal of top input, the dateout of a corresponding high bit memory from 16 bit phase value memories just, the data selector of bit #15 is then selected the dateout of 4 input binary adders, like this, during each end cycle, compare when the scrambler sequence phase value of 16 bit phase value store memories storage began with this cycle, moved 1 to the positive infinity direction.
When this step finished, the initial phase adjustment enabled to be changed to invalid signals, and the phase value of scrambler sequence 16 bits of 16 bit phase value store memories storage bit from low to high corresponds to bit scramble scrambler sequence y
kY
-M-15To y
-M
Parallel data of every input, 16 bit phase value memories are exported the phase information of 16 bits and are generated the N bit value of scrambling scrambler sequence for N bit phase value maker, are input to the sequence scrambler again, finish the scrambling operation with the parallel data of input.
High 16 bit feedback of bit scramble scrambler sequence are input to the initial phase adjuster, at this moment initial phase adjustment enable signal is an invalid signals, the corresponding bit that the data selector of each bit of initial phase adjuster is selected deposits in the corresponding stored space of 16 bit phase value memories.
By this embodiment, when transport block size B is not the integral multiple of degree of parallelism N, mode by the unnecessary phase place of insertion portion before scrambler sequence, make N the N that must use when no longer needing align data in original device or alignment scrambler sequence select 1 data selector unit, and only need the selector of 16 alternatives, thereby reduce the complexity of bit scramble parallel processing structure.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and those skilled in the art is in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the definition of claim.
Claims (8)
1. a bit scramble parallel processing method is applicable to that the high speed downlink packet of broadband CDMA system inserts the field, it is characterized in that, may further comprise the steps:
A, the value of bit scramble scrambler is expanded to minus infinity;
B, the initial phase place value in the 16 bit phase value memories is moved N to the positive infinity direction subtract M phase place, and store, wherein N is the bit number of parallel data sequence, and M is for being positioned at the invalid bit number of low bit in first parallel data sequence; Step B further may further comprise the steps:
B1, described 16 bit phase value memories load corresponding bit scrambling scrambler sequence y from low to high successively
-N-15To y
-NThe initial phase place value;
B2, obtain the invalid bit number M that is positioned at low bit in first parallel data sequence;
B3, the initial phase adjustment that provides N to subtract M cycle enable useful signal to the initial phase adjuster;
B4, described initial phase adjuster of each cycle move one with the phase place of bit scramble scrambler sequence corresponding in the described 16 bit phase value memories to the positive infinity direction, are input to described 16 bit phase value memories again and store;
The y of the phase value corresponding bit scrambling scrambler sequence of B5, last described 16 bit phase value memory stores
-M-15To y
-M
C, input parallel data sequence utilize bit scramble scrambler sequence and described parallel data sequence after moving to finish the scrambling operation.
2. a kind of bit scramble parallel processing method according to claim 1 is characterized in that, in the steps A, described bit scramble scrambler sequence meets following formula:
Wherein, y
kBe k the value of described bit scramble scrambler sequence y, B is the bit number of bit data flow.
3. a kind of bit scramble parallel processing method according to claim 1 is characterized in that step C further may further comprise the steps:
C1, the described parallel data sequence of input;
C2, the phase value of storing in the described 16 bit phase value memories is outputed to the new phase value maker of N bit, generate the N bit value of bit scramble scrambler sequence;
C3, the N bit value of bit scramble scrambler sequence is input to the sequence scrambler, carries out the scrambling operation with described parallel data sequence.
4. a kind of bit scramble parallel processing method according to claim 3 is characterized in that, and is further comprising the steps of:
C4, with high 16 bit storage of the N bit value of described bit scramble scrambler sequence to described 16 bit phase value memories.
5. bit scramble parallel processing apparatus of realizing the described bit scramble parallel processing method of claim 1, the high speed downlink packet that is applicable to broadband CDMA system inserts the field, it is characterized in that, comprise 16 bit phase value memories, the initial phase adjuster, new phase value maker of N bit and sequence scrambler, wherein N is the bit number of parallel data, described 16 bit phase value memories are used to receive new data block indication input signal, the sequence phase information input signal, the signal of initial phase adjuster output also sends scrambling code phase information to described initial phase adjuster and the new phase value maker of described N bit, described initial phase adjuster is used to receive the high order bit signal that initial phase is adjusted enable signal and the new phase value maker of described N bit, the new phase value maker of described N bit is used to export the new scrambler sequence phase value of N bit to described sequence scrambler, the data after described sequence scrambler is used to receive the parallel data sequence and exports scrambling.
6. a kind of scrambling parallel processing apparatus according to claim 5 is characterized in that, described initial phase adjuster comprises the binary adder of 16 alternative data selectors and 14 input.
7. a kind of scrambling parallel processing apparatus according to claim 6, it is characterized in that, in described 16 alternative data selectors, the below of the data selector of bit 15 input data are the bit 0 in high 16 bits of new scrambler sequence phase value of N bit, and the top input signal is the output signal of described 4 input binary adders; Input data in the data selector of other each bits below are the corresponding bit of high 16 bits of the new scrambler sequence phase value of N bit, and top input data are a high bit of the correspondence of 16 bit phase value memory output signals;
When the adjustment of input signal initial phase enables when effective, select the data of top port input; When initial phase place adjustment enables when invalid, select the data of below port input.
8. a kind of scrambling parallel processing apparatus according to claim 6, it is characterized in that, the output of described 4 input binary adders is connected to the top input of the alternative data selector of bit 15, the memory space #0, the #2 that are input as 16 bit phase value memories of described 4 input binary adders, the dateout of #3, #5.
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| CN102025696B (en) * | 2009-09-16 | 2014-06-04 | 中兴通讯股份有限公司 | Parallel scrambling and descrambling processing device and method |
| CN110247666B (en) * | 2019-05-22 | 2023-08-18 | 深圳大学 | System and method for hardware parallel compression |
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| CN1280366A (en) * | 1999-07-10 | 2001-01-17 | 三星电子株式会社 | Random date generator and scrambler using said generator |
| CN1490811A (en) * | 2002-10-07 | 2004-04-21 | 三星电子株式会社 | Device and method for encrypting and decrypting word by word on CD system |
| CN1645782A (en) * | 2003-11-13 | 2005-07-27 | 三星电子株式会社 | Method and apparatus for bit scrambling for packet transmission/reception in a wireless communication system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1280366A (en) * | 1999-07-10 | 2001-01-17 | 三星电子株式会社 | Random date generator and scrambler using said generator |
| CN1490811A (en) * | 2002-10-07 | 2004-04-21 | 三星电子株式会社 | Device and method for encrypting and decrypting word by word on CD system |
| CN1645782A (en) * | 2003-11-13 | 2005-07-27 | 三星电子株式会社 | Method and apparatus for bit scrambling for packet transmission/reception in a wireless communication system |
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