CN101964183A - Display processing equipment and multi-screen display system - Google Patents
Display processing equipment and multi-screen display system Download PDFInfo
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Abstract
The invention provides display processing equipment and a multi-screen display system applying the same. The display processing equipment comprises a plurality of processing modules, a clock module and a plurality of frequency multiplication modules, wherein the clock module is connected with frequency multiplication modules respectively; each frequency multiplication module is in one-to-one connection with each processing module; the clock module is used for acquiring a synchronous clock and outputting the synchronous clock to each frequency multiplication module; the frequency multiplication modules are used for performing frequency multiplication on the synchronous clock respectively and transmitting the synchronous clock to each processing module; and the processing modules are used for receiving clock signals output by the corresponding frequency multiplication modules and performing image processing according to the clock signals. The multi-screen display system consisting of the display processing equipment provided by the invention has the advantages of higher image display synchronicity and higher image display quality.
Description
Technical field
The present invention relates to the multidisplay technology field, relate in particular to a kind of multihead display system and a kind of equipment of forming described multihead display system.
Background technology
Along with the development of multidisplay technology, the application of multidisplay technology becomes more and more widely.In the multihead display system, usually need a plurality of display processing device combinations to show a complete picture synchronously, for realizing the synchronous demonstration of each described display processing device, generally each described display processing device is sent the synchronic command of executable operations instruction, carry out described synchronic command according to the clock of itself by each described display processing device by the controller of described multihead display system.
Usually after receiving synchronic command, the local zone time that clock of each described display processing device basis itself and described synchronic command obtain carrying out described operational order, yet, the clock of each described display processing device itself has deviation, cause each described display processing device asynchronous in the real time of carrying out described operational order, the frame picture that described multihead display system is shown is also asynchronous, influences display effect.
Summary of the invention
At the nonsynchronous technical matters of display frame of prior art multihead display system, the technical matters that the present invention solves is to provide a kind of display processing device that can improve the display frame synchronism of multihead display system.Can improve reliability, robustness and the stability of multihead display system synchronization clock, the influence of the uncertain factor that the minimizing clock transfer is brought.
A kind of display processing device comprises several processing modules, clock module and several frequency multiplication modules, and described clock module connects each described frequency multiplication module respectively, and each described frequency multiplication module is connected correspondingly with each described processing module.Described clock module is used to obtain synchronous clock, and exports described synchronous clock to each described frequency multiplication module; Described frequency multiplication module is used for respectively described synchronous clock being carried out process of frequency multiplication, transfers to corresponding each described processing module that connects then; Described processing module is used to receive the clock signal of corresponding described frequency multiplication module output and according to described clock signal carries out image processing.
Compared with prior art, in the display processing device of the present invention, described clock module obtains synchronous clock, each described frequency multiplication module needs described synchronous clock frequency multiplication again to each described processing module frequency, therefore, in the multihead display system that a plurality of described display processing devices are formed, each described display processing device can use unified synchronizing clock signals, guarantee the clock synchronization of each described display processing device, improve the picture display quality of multihead display system.Simultaneously, because be provided with described frequency multiplication module, so that the frequency of described synchronous clock can be arranged to is lower, the clock of frequency under 50MHz for example.When described synchronous clock transmits,, therefore can reduce the decay and the shake of synchronous clock transmission between each display processing device because low-speed clock loss in transmission course is less between each described display processing device.
At the nonsynchronous technical matters of display frame of prior art multihead display system, the multihead display system that provides a kind of display frame synchronism higher also is provided the technical matters that the present invention solves.
A kind of multihead display system comprises interconnected several display processing devices, and each described display processing device all comprises several processing modules, clock module and several frequency multiplication modules; Described clock module connects each described frequency multiplication module respectively, and each described frequency multiplication module is connected correspondingly with each described processing module.Described clock module in the described multihead display system comprises the major clock module and from clock module, described major clock module describedly is connected from clock module with each, described major clock module is used to produce synchronous clock, and described synchronous clock is transferred to each is described from clock module be positioned at each described frequency multiplication module of same display processing device; Describedly be used to receive described synchronous clock, and described synchronous clock is transferred to each the described frequency multiplication module that is positioned at same display processing device from clock module; Each described frequency multiplication module is used for described synchronous clock is carried out process of frequency multiplication, transfers to each corresponding described processing circuit module then; Described processing module is used to receive the clock signal of corresponding described frequency multiplication module output and according to described clock signal carries out image processing.
Compared with prior art, in the multihead display of the present invention system, obtain same clock by being connected to each other between each described display processing device, therefore can be according to identical clock carries out image processing operation, it is more synchronous that picture is shown, improves the picture display quality of multihead display system.Simultaneously because all be provided with described frequency multiplication module in each display processing device, the clock multiplier of described clock module output can be converted to the work clock of each described processing module, the frequency of the synchronous clock that therefore described clock module produces can be arranged to lower, for example the clock of frequency under 50MHz.When described synchronous clock transmits,, therefore can reduce the decay and the shake of synchronous clock transmission between each display processing device because low-speed clock loss in transmission course is less between each described display processing device.
Description of drawings
Fig. 1 is the structural representation of multihead display of the present invention system;
Fig. 2 is first's structural representation of a kind of preferred implementation of display processing device of the present invention;
Fig. 3 is the structural representation of the second portion of display processing device shown in Figure 2.
Wherein, 11,21 clock modules;
12 frequency multiplication modules;
13 processing modules;
22 phaselocked loops;
23 image capture devices;
24 image acquisition and processing modules;
25 backboards;
26 data exchange processing modules;
28 display process modules;
29 displays.
Embodiment
See also Fig. 1, Fig. 1 is the structural representation of multihead display of the present invention system.
Described multihead display system comprises interconnected several display processing devices, Fig. 1 has only put down in writing display processing device A and display processing device B, but, can in described multihead display system, interconnected display processing device more than two be set according to the actual conditions needs.
Each described display processing device all comprises clock module 11, several frequency multiplication modules 12 and several processing modules 13; Described clock module 11 connects each described frequency multiplication module 12 respectively, and described frequency multiplication module 12 is connected correspondingly with described processing module 13.
Described clock module 11 has the synchronous clock interface (not indicating) that is used to import or export synchronous clock, and the clock module 11 of each described display processing device is connected to each other with data line by described synchronous clock interface.Described clock module 11 can receive the local clock of described display unit on the one hand, can receive described synchronous clock from other display processing device by described synchronous clock interface on the other hand.
According to user's setting, described clock module 11 can be configured to the major clock module or from clock module.Described major clock module is from the local clock of the described display processing device reception at its place, and export the synchronous clock of described local clock as whole described multihead display system, described major clock module is to the described synchronous clock of each described frequency multiplication module 12 outputs of same display processing device, and described major clock module also transfers to described synchronous clock and is positioned at the described from clock module of other display processing devices by described synchronous clock interface and corresponding data line simultaneously; Each is described to receive described synchronous clock from the described synchronous clock interface of clock module by separately, and described synchronous clock is transferred to each the described processing module 13 that is arranged in same display processing device.Therefore the described frequency multiplication module 12 in each described display processing device all is that identical described synchronous clock is carried out frequency multiplication, the phase place of clock signal that transfers to each described processing module 13 after each described frequency multiplication module 12 process of frequency multiplication is identical, so the display operation that each described display processing device is carried out can be synchronous.
Usually in a multihead display system, have only the clock module 11 of a display processing device to be configured to described major clock module, the clock module 11 of other display processing device all is configured to described from clock module, in the multihead display system for example shown in Figure 1, the clock module 11 of described display processing device A is configured to described major clock module, and the clock module 11 of described display processing device B is configured to described from clock module.
Further, describedly can receive the local clock of the described display processing device at place separately from clock module, described from clock module when not receiving the synchronous clock of outside input by described synchronous clock interface, described local clock is exported in the described frequency multiplication module 12, as the reference clock of frequency multiplication operation.Therefore, even when not receiving outside synchronous clock, each described display processing device still can be carried out display operation according to described local clock.Usually, can be provided with in the described clock module 11, described synchronizing clock signals has higher output priority than described local clock, promptly both received local clock at described clock module 11, when receiving described synchronous clock again, preferentially described synchronous clock is exported to corresponding frequency multiplication module 12,, then go out described local clock to each described frequency multiplication module 12 if do not receive described synchronous clock.Perhaps, the output of described clock module 11 is chosen between described local clock or described synchronous clock by the user.
As a preferred implementation, produce two or more local clocks in the described display processing device, described clock module 11 comprises the major clock module and from clock module, receives two or more described local clocks.When the described local clock of described clock module 11 outputs, can select one of them described local clock output according to predefined clock Redundant Control rule.Wherein, described clock Redundant Control rule can be set to: when detecting one of them described local clock and depart from predetermined value and reach threshold value, switch to another local clock output, described predetermined value and described threshold value are all set according to actual needs by the user; Perhaps local clock output is therein interrupted or when makeing mistakes, is automatically switched to another local clock output.Because described clock module 11 has received two or more described local clocks and has been provided with described clock Redundant Control rule, therefore, even one of them local clock makes a mistake, also can in time switch to the output of another local clock, can improve the stability of each described display processing device and described multihead display system.Described two or more local clock can adopt VCXO (crystal oscillator) chip to produce.
Described clock module 11 can be by selecting the clock chip of quality multichannel output preferably for use, and the shake when clock output is switched is controlled at very low ps magnitude, realizes the seamless switching between a plurality of described local clocks and the described synchronous clock.
Each described frequency multiplication module 12 is carried out process of frequency multiplication to described reference clock separately respectively according to the working clock frequency needs of its corresponding described processing module 13 that connects, and the clock signal after will handling then transfers to each corresponding described processing module 13.Described frequency multiplication module 12 generally is installed in the same circuit board correspondingly with described processing module 13, described frequency multiplication module 12 can have a plurality of frequency multiplication outputs, so that the work clock of various different frequencies is provided for described processing module 13, a plurality of frequency multiplication outputs of described frequency multiplication module 12 are respectively to obtain after described reference clock is carried out different process of frequency multiplication, as an embodiment, described frequency multiplication module can utilize the phaselocked loop with clock multiplication device function to realize.
Described processing module 13 is used to receive the clock signal after the process of frequency multiplication of corresponding described frequency multiplication module 12 outputs, and carries out corresponding image processing operations according to described clock signal.
Because the frequency of clock signal is high more, in transmission course, particularly the signal attenuation in the long-distance transmissions process is big more, for example, the clock signal of 100MHz decays to 20dB in transmission line, the decay of clock signal in transmission line at 400MHz will reach 40dB so.Therefore, be provided with described frequency multiplication module 12 in each described display processing device of the present invention, can carry out process of frequency multiplication to the synchronous clock that described clock module 11 receives, the described synchronous clock that transmits between described each described display processing device can be arranged to have lower frequency.As a preferred implementation, the frequency of described synchronous clock is not higher than 50MHz, can reduce the decay of synchronous clock in transmission course effectively, need not at receiving end extra clock to be set and repairs chip, reduces system cost.
Compared with prior art, in display processing device of the present invention and the multihead display system, obtain same clock by being connected to each other between each described display processing device, therefore can be according to identical clock carries out image processing operation, it is more synchronous that picture is shown, improves the picture display quality of multihead display system.And the described processing module of each in the same display processing device is also used identical synchronous clock, and each described processing module that therefore also can solve same display processing device is carried out data processing and the stationary problem when calculating.
Please further consult Fig. 2 and Fig. 3, Fig. 2 is first's structural representation of a kind of preferred implementation of display processing device of the present invention; Fig. 3 is the structural representation of the second portion of display processing device shown in Figure 2.
In the present embodiment, described display processing device comprises the clock module 21 that is used for clocking, the phaselocked loop 22 that is used for clock signal is carried out process of frequency multiplication, and the image capture device 23 that connects successively, image acquisition and processing module 24, backboard 25, data exchange processing module 26, display process module 28 and display 29; And, described clock module 21 connects described image acquisition and processing module 24 by described backboard 25 and a described phaselocked loop 22, described clock module 21 connects described display process module 28 by described backboard 25 and another described phaselocked loop 22, and described clock module 21 connects described data exchange processing module 26 by the 3rd described phaselocked loop 22.
The principle of work of described display processing device is as follows:
At first be set by the user described clock module 21 in the described display processing device for the major clock module or from clock module, if described clock module 21 is configured to the major clock module, then described clock module 21 connects the clock module of other display processing devices, and the local clock that obtains described display processing device transfers to the clock module of other each described display processing device as the synchronous clock of described multihead display system; If described clock module 21 is configured to from clock module, then described clock module 21 receives the synchronous clock of other display processing device outputs by the synchronous clock interface of correspondence.In the present embodiment, described clock module produces and the frequency of the described synchronous clock that transmits between each described display processing device is 27MHz, because the clock frequency of transmitting between each described display processing device is lower, therefore the loss and the distortion of clock signal are less, need not to be provided with special clock recovery circuitry in each display processing device the synchronous clock that receives is recovered to handle.
In a described display processing device, the described synchronous clock of described clock module 21 outputs is sent to the described phaselocked loop 22 that connects described image acquisition and processing module 24 by described backboard 25 respectively; Be sent to the described phaselocked loop 22 that connects described display process module 28 by described backboard 25; And the described phaselocked loop 22 that is sent to the described data exchange processing module 26 of connection.
Each described phaselocked loop 22 needs according to the frequency of operation of each described processing module (image, demonstration or exchanges data) of its connection respectively, to frequency is that the described synchronous clock of 27MHz carries out process of frequency multiplication, then each corresponding described processing module of output.Wherein, the frequency that exports the clock signal of described image acquisition and processing module 24 and described display process module 28 to is 243MHz; The frequency that exports the clock signal of described data exchange processing module 26 to is 121.5MHz.
After described image acquisition and processing module 24 receive frequencies are the described clock signal of 243MHz, according to described clock signal the view data of described image capture module collection is carried out Flame Image Process such as digital-to-analog conversion, and transfer to described data exchange processing module 26 by described backboard 25; After described data exchange processing module 26 receive frequencies are the described clock signal of 121.5MHz, according to described clock signal the view data of described image acquisition and processing module 24 outputs is carried out processing such as image segmentation, and the parts of images data after will cutting apart transfer to corresponding described display process module 28 by described backboard 25; After described display process module 28 receive frequencies are the described clock signal of 243MHz, according to described clock signal the parts of images data of described data exchange processing module 26 outputs are carried out display process, then display data transmissions is shown in each display 29.
When described clock module 21 does not receive the described synchronous clock of external transmission, between a plurality of local clocks of the described display device of correspondence, choose one according to predefined clock redundancy rule and export each described phaselocked loop 22 to, guarantee the operate as normal of each described display processing device.
Above-described embodiment of the present invention does not constitute the qualification to protection domain of the present invention.Any modification of being done within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within the claim protection domain of the present invention.
Claims (10)
1. a display processing device comprises several processing modules, and described processing module is used for the receive clock signal and according to described clock signal carries out image processing, it is characterized in that:
Described display processing device also comprises clock module and frequency multiplication module, and described clock module connects each described frequency multiplication module respectively, and each described frequency multiplication module is connected correspondingly with each described processing module;
Described clock module is used to obtain synchronous clock, and exports described synchronous clock to each described frequency multiplication module;
Described frequency multiplication module is used for respectively described synchronous clock being carried out process of frequency multiplication, transfers to corresponding each described processing module that connects then.
2. display processing device as claimed in claim 1 is characterized in that: described clock module obtains the local clock of described display processing device as described synchronous clock.
3. display processing device as claimed in claim 1 is characterized in that: described clock module comprises the synchronous clock interface, and described clock module receives the described synchronous clock of outside input by the synchronous clock interface.
4. display processing device as claimed in claim 3, it is characterized in that: described clock module is further used for receiving the local clock of described display processing device, when not receiving the described synchronous clock of outside input, described clock module transfers to described frequency multiplication module with described local clock; Described frequency multiplication module is further used for described local clock is carried out process of frequency multiplication, transfers to corresponding each described processing module that connects then.
5. as claim 1,2 or 4 described display processing devices, it is characterized in that: described clock module receives a plurality of described local clocks, in output during described local clock, according to the user set switch the described a plurality of local clocks of output one of them.
6. multihead display system, comprise interconnected several display processing devices, each described display processing device all comprises several processing modules, and described processing module is used for the receive clock signal and according to described clock signal carries out image processing, it is characterized in that:
Each described display processing device also comprises clock module and several frequency multiplication modules, and described clock module connects each described frequency multiplication module respectively, and each described frequency multiplication module is connected correspondingly with each described processing module;
Described clock module in the described multihead display system comprises the major clock module and from clock module, described major clock module describedly is connected from clock module with each, described major clock module is used to produce synchronous clock, and described synchronous clock is transferred to each is described from clock module be positioned at each described frequency multiplication module of same display processing device; Describedly be used to receive described synchronous clock, and described synchronous clock is transferred to each the described frequency multiplication module that is positioned at same display processing device from clock module;
Each described frequency multiplication module is used for described synchronous clock is carried out process of frequency multiplication, transfers to each corresponding described processing circuit module then.
7. multihead display as claimed in claim 6 system, it is characterized in that: each described local clock that is further used for receiving described display processing device from clock module, when clock module does not receive described synchronous clock, described local clock is transferred to each the described frequency multiplication module that is positioned at same display processing device when described;
Each described frequency multiplication module is further used for described local clock is carried out process of frequency multiplication, transfers to each corresponding described processing circuit module then.
8. multihead display as claimed in claim 7 system is characterized in that: describedly receive a plurality of described local clocks from clock module, and when the output local clock according to predefined clock redundancy rule switch a plurality of described local clocks of output one of them.
9. multihead display as claimed in claim 6 system, it is characterized in that, described major clock module receives a plurality of local clocks of described display processing device, and according to predefined clock redundancy rule switch a plurality of described local clocks of output one of them as described synchronous clock.
10. as claim 8 or 9 described multihead display systems, it is characterized in that described clock redundancy rule is: when detecting one of them described local clock and depart from predetermined value and reach threshold value, switch to another local clock output.
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