CN101763840A - Synchronous display device, stacking splicing display system and synchronous display method thereof - Google Patents
Synchronous display device, stacking splicing display system and synchronous display method thereof Download PDFInfo
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Abstract
The invention relates to a synchronous display device and a synchronous display method. The device comprises a synchronous control circuit, more than one mainboards and more than two display cards. Any one of mainboards is inserted with at least one display card. The synchronous control circuit comprises a frame synchronous control circuit and a reference clock generating circuit. A signal output end of the frame synchronous control circuit is connected with a signal input end of each mainboard. A signal output end of the reference clock generating circuit is connected with a clock signal input end of each display card. The frame synchronous control circuit generates a reference frame synchronous signal or uses a frame synchronous signal of a display channel of a preset display card as the reference frame synchronous signal. Each mainboard adjusts the frame synchronous signal of the display channel of the corresponding display card according to the reference frame synchronous signal. The invention adopts the same reference frame synchronous signal and reference clock signal to together complete synchronous display, cannot generate the clock error and also cannot generate the accumulated error among the frame synchronous signals so as to improve accuracy and continuity of synchronization among the display signals.
Description
Technical field
The present invention relates to the image display technology field, the synchronous display method of particularly a kind of synchronous display apparatus and synchronous display apparatus and a kind of stack display system, a kind of splice displaying system.
Background technology
Application number is 200810198074.5, publication number is that the patented claim of CN101383913A discloses a kind of display overlapping control system and control method thereof, this system includes the superposing control circuit, the frame synchronization control circuit, display and at least two shows signal output units, the demonstration output terminal of each shows signal output unit is connected with the superposing control circuit appliance, the signal input end of frame synchronization control circuit and each shows signal output unit, the superposing control circuit is electrically connected, superposing control circuit and display are electrically connected, the frame synchronization control circuit is dynamically adjusted (adjusting by adopting adjustment demonstration flyback time parameter) according to the frame synchronizing signal of each shows signal output unit, make the frame synchronizing signal of each shows signal output unit keep synchronously dynamic, the superposing control circuit is with the vision signal stack back output of each shows signal output unit.This application has realized a kind of a plurality of shows signal and the synchronous method of benchmark synchronizing signal, and when splicing for a plurality of displays, as long as be synchronous between each reference signal of these a plurality of shows signal, so, the demonstration of whole splice displaying system will be synchronous.
But, in the disclosed scheme of this application, the crystal oscillator of each display card be respectively based on separately independently clock signal come work, and the basic index of oscillator is all relevant with output frequency, compare with ideal frequency, always can there be certain error in the output frequency of oscillator, and the error here mainly is made up of three aspects:
One, frequency accuracy: if crystal oscillator frequency is fixed frequency output, and do not have other mode of frequency regulation (for example electricity adjustment or mechanical adjustment or the like), so, will put forward this index, i.e. the departure degree of the dispatch from the factory frequency and the ideal frequency of crystal oscillator to crystal oscillator;
They are two years old, temperature stability: the output frequency of oscillator can be subjected to influence of temperature variation, referring to shown in Figure 1, it is the temperature frequency family curve synoptic diagram of crystal oscillator, it is relevant with the cutting angle of crystal, and the temperature stability of crystal oscillator depends on the crystal that selection is suitable, and design suitable oscillatory circuit, make the two co-ordination, to keep the intrinsic stability of crystal, for example ± and 10ppm/0 ℃～+ 50 ℃, the maximum changing range that is illustrated in frequency in the warm area of regulation is 20ppm, sometimes, frequency range is with respect to a reference value, and generally the output frequency with 25 ℃ of room temperatures is a reference frequency;
They are three years old, ageing rate (long-term stability): the running parameter of crystal can change along with the time, thereby cause the frequency drift of crystal oscillator, and this and other external factor has nothing to do, when crystal is initially added some points, aging very fast, along with the development of time can make moderate progress, after several weeks of experience, can reach minimum ageing rate, if add suitable electric current to crystal, welding resistance AT cuts the crystal ageing rate and was generally 5ppm/ 1 year, after the 3ppm/ 1 year, if custom system requires stricter ageing rate then will consider: or by increasing frequency adjustment end, so that after date is recalibrated output frequency in the time of one section, or adopts higher-quality crystal resonator, for example glass bulb or cold pressure welding encapsulation etc.
The above ± 10ppm is equivalent to 10/1000000ths, and the frame rate of present most display is 60Hz, cycle is 1/60 second, promptly 0.017 second, to calculate according to ± 10ppm, one hour cumulative errors is 3600 seconds * 10/1000000=0.036 seconds, and 0.036 second error has been far longer than 0.017 second frame period, in order to allow system continuous one day 8 hours, and a plurality of frame synchronizing signal cumulative errors less than 0.017 second frame period 10% in, this is suitable difficulty.
Therefore, because the basic index of oscillator is all relevant with output frequency, influences such as frequency accuracy, temperature stability, ageing rate all can cause between the actual output frequency domain of oscillator and the ideal frequency and have error, therefore thereby can there be cumulative errors in the crystal of each display card or crystal oscillator, and needing often to adopt this application number is that mode in 200810198074.5 is revised synchronously.But, display card for various maturation, especially for the GPU display card, it is extremely very difficult thing that their parameter is made amendment, most of producer does not allow the client to revise local parameter yet, can only finish by being provided with of display parameter of integral body, so the response time is also untimely, and show that output can instantaneous interruption, cause the display image shake or moment blank screen or moment the flower screen.
Summary of the invention
The object of the present invention is to provide a kind of synchronous display apparatus and synchronous display method, a kind of stack display system, splice displaying system, to realize the synchronous accuracy between the shows signal.
For achieving the above object, the present invention by the following technical solutions:
A kind of synchronous display apparatus, comprise: synchronization control circuit, more than one motherboard, and plural display card, insert on any one motherboard and be connected with at least one display card, described synchronization control circuit comprises the frame synchronization control circuit, reference clock produces circuit, the signal output part of described frame synchronization control circuit is connected with the signal input part of each described motherboard, the signal output part that described reference clock produces circuit is connected with the clock signal input terminal of each described display card, the frame synchronizing signal of display channel that described frame synchronization control circuit produces reference frame synchronization signal or will preset display card is as reference frame synchronization signal, and each described motherboard is adjusted the frame synchronizing signal of the display channel of each corresponding display card according to described reference frame synchronization signal.
A kind of synchronous display apparatus, it is characterized in that, comprise: synchronization control circuit, more than one motherboard, and plural display card, insert on any one motherboard and be connected with at least one display card, described synchronization control circuit comprises the frame synchronization control circuit, reference clock produces circuit, the signal output part of described frame synchronization control circuit is connected with the signal input part of each described motherboard, the signal output part that described reference clock produces circuit is connected with the clock signal input terminal of each described display card, the shows signal output terminal of each described display card is connected with described frame synchronization control circuit, the frame synchronizing signal of display channel that described frame synchronization control circuit produces reference frame synchronization signal or will preset display card is as reference frame synchronization signal, judge the frame synchronizing signal of display channel of each display card and the deviation range of described reference frame synchronization signal, each described display card respectively shows the frame synchronizing signal of passage accordingly according to the described deviation range adjustment of each display channel of correspondence.
A kind of stack display system comprises display unit, overlap-add procedure unit, also comprises aforesaid synchronous display apparatus, and each described display card is connected with described overlap-add procedure unit, and described overlap-add procedure unit is connected with described display unit.
A kind of splice displaying system comprises combination, also comprises aforesaid synchronous display apparatus, each described display card respectively with the corresponding connection of at least one concatenation unit in the described combination.
A kind of synchronous display method of aforesaid synchronous display apparatus comprises step:
Each motherboard is adjusted the frame synchronizing signal of the display channel of each display card of correspondence synchronously according to the reference frame synchronization signal of described frame synchronization control circuit.
According to the solution of the present invention, all motherboards in the synchronous display apparatus are connected with same frame synchronization control circuit, all display cards produce circuit with same reference clock and are connected, the reference clock signal that produces by same clock reference clock generation circuit makes the clock signal of each display card synchronous, export synchronously according to the reference frame synchronization signal that the frame synchronization control circuit produces or determines, promptly adopt identical reference frame synchronization signal and reference clock signal to finish display synchronization jointly, owing to adopt same reference clock signal, can not produce clocking error, each frame synchronizing signal can not produce cumulative errors yet, thereby has improved synchronous accuracy and continuation between the shows signal.
Description of drawings
Fig. 1 is the temperature frequency family curve synoptic diagram of crystal oscillator;
Fig. 2 is the structural representation of the embodiment one of synchronous display apparatus of the present invention;
Fig. 3 is the connection mode synoptic diagram that is applied to the RS232 in the synchronous display apparatus of the present invention;
Fig. 4 is the structural representation of the embodiment two of synchronous display apparatus of the present invention;
Fig. 5 is the structural representation of the embodiment three of synchronous display apparatus of the present invention;
Fig. 6 is the structural representation of the embodiment four of synchronous display apparatus of the present invention.
Embodiment
Consider in existing demonstration field, can be by a plurality of PC respectively to the laggard line output of the signal Processing of each several part with tiled display, also can be a plurality of display cards to be set show in PC to carry out hyperchannel, therefore, in following elaboration, respectively with the tiled display of a plurality of PCs with in a PC, carry out the situation that hyperchannel shows and be illustrated respectively by a plurality of display cards.
Embodiment one:
Referring to shown in Figure 2, be the structural representation of the synchronous display apparatus embodiment one of synchronous display apparatus of the present invention.
As shown in Figure 2, in this example, be that to carry out tiled display with a plurality of PCs be that example describes, suppose that each PC has included only a display card, as shown in the figure, this synchronous display apparatus includes synchronization control circuit and plural PC, wherein, this synchronization control circuit comprises the frame synchronization control circuit, reference clock produces circuit, each PC includes a motherboard and a display card, each display card inserts and is connected on the motherboard of its place PC, the clock signal input terminal of the display card of all PCs is connected with the signal output part that reference clock produces circuit, and the signal input part of the motherboard of all PCs is connected with the signal output part of frame synchronization control circuit.In diagram, Vh representative frame synchronizing signal, clk represents clock signal, the frame synchronizing signal Vh1 of PC1, the frame synchronizing signal Vh2 of PC2, ..., the frame synchronizing signal Vhn of PCn all is connected with the signal output part of frame synchronization control circuit, be connected to the input end of clock clk1 of the display card of PC1, be connected to the input end of clock clk2 of the display card of PC2, ..., the input end of clock clk3 that is connected to the display card of PCn all is connected with the signal output part of reference clock generation circuit, described reference clock produces circuit and produces reference clock signal, described frame synchronization control circuit produces reference frame synchronization signal, and the motherboard of each PC is adjusted the frame synchronizing signal of each corresponding display card according to this reference frame synchronization signal.
Scheme according to aforesaid present embodiment, the motherboard of all PCs all is connected with same frame synchronization control circuit, the input end of clock of the display card of all PCs all is connected with the signal output part of same reference clock generation circuit, the clock signal (to call reference clock signal in the following text) that produces the circuit generation by same reference clock makes the clock signal of each display card synchronous, adjust the frame synchronization output of each display card by the frame synchronizing signal (to call reference frame synchronization signal in the following text) of same frame synchronization control circuit generation, promptly adopt identical reference frame synchronization signal and reference clock signal to finish display synchronization jointly, owing to adopt same reference clock signal, can not produce clocking error, each frame synchronization can not produce cumulative errors yet, thereby has improved synchronous accuracy and continuation between the shows signal.
In addition, because the price of crystal oscillator is very cheap at present, use also very convenient, therefore, usually all be that display card for each PC uses separately independently crystal oscillator respectively in use, do not make each display card share a crystal oscillator and not can take into account, adopt synchronizing signal from same crystal oscillator, more not can take into account shared same clock source between each different PC, because this brings certain complicacy in the system wiring design, and allow each display card use separately clock source respectively, relatively easy during installation and design, Just because of this, because each display card uses clock source separately respectively, can't guarantee the synchronism in the clock source of each display card, thereby cause the clocking error between each display card, and then make the frame synchronization output of each display card produce cumulative errors, cause the synchronous inaccurate of final shown stack or splicing signal.
And in our scheme, by making the shared clock signal of each display card from same clock source (being the said reference clock generation circuit), though brought certain complexity when installing for the device initial designs, but, because each display card all is the reference clock signal that adopts from same clock source (being that the above-mentioned reference clock of the present invention produces circuit), guaranteed the consistance of the strictness of the clock synchronization between each display card, and when frame synchronizing signal is adjusted, also be based on reference frame synchronization signal from same frame synchronization control circuit, thereby can not produce clocking error when exporting synchronously, cumulative errors be can not produce between each frame synchronizing signal yet, synchronous accuracy and continuation between the shows signal of each display card guaranteed.
Because PC not necessarily can be known the initialization time or the start-up time of each display unit at an easy rate, therefore, when system start-up, can at first carry out the process of a subsynchronous adjustment, it is disclosed mode in 200810198074.5 the patented claim that concrete mode can adopt application number, perhaps also can be: after the reference frame synchronization signal that detects the frame synchronization control circuit, after through a Preset Time section, each display card is carried out initialization operation, and just the reference frame synchronization signal with the frame synchronization control circuit is identical so that the frame synchronization of the display channel of each display card is exported.
PC can detect the reference frame synchronization signal of frame synchronization control circuit output by install software, and the frame synchronizing signal of the display channel of this reference frame synchronization signal and display card compared, if the two is inconsistent or gap is excessive (promptly having surpassed the preset range that is allowed), then need the frame synchronizing signal that the display channel of display card produces is adjusted, gap up to the two narrows down in the preset range of permission, concrete adjustment mode can be that disclosed mode is identical in 200810198074.5 the patented claim with application number, does not repeat them here.
In addition, in order further to improve accuracy and real-time, can detect difference lock in time by adopting interrupt response, and adjust in view of the above, concrete mode can be identical with mode of the prior art, for example: reference frame synchronization signal is received motherboard, when frame synchronizing signal arrives, allow the CPU of motherboard produce interruption; The parameter of display card is set, makes when certain display channel carries out frame flyback or frame synchronization produces interruption when beginning.More than each all writes down time when interrupting producing when interrupt producing, and then the time that the display channel of each display card is produced time of interrupting and reference frame synchronization signal interruption compares, whether the time that the interruption of judgment standard frame synchronizing signal takes place is identical with the time that each display channel produces interruption, if it is inequality, then the frame synchronization of discrepant display channel is adjusted, made each frame synchronizing signal reach consistent.
Reach synchronously or basic synchronization (being in the frame synchronization error range that allowing of frame synchronization error) after, system just can normally move, owing to be based on identical reference frame synchronization signal and reference clock signal during operation, therefore do not need to adjust yet midway, the frame synchronization zero-time of each display unit of the applied splice displaying system of this synchronous display apparatus is consistent for a long time.
In addition, for the some of them overlapping system, back output need superpose to the signal of each display card, because the present invention program's is synchronous more accurate, therefore, when carrying out overlap-add procedure, the signal after the overlap-add procedure can not produce skew or drift yet, and the control of stack logic is also more simple and reliable.
Wherein, the frequency of the clock signal that the clock synchronization control circuit is produced can be as reference clock according to needed clock (for example 27Mhz).Because this clock frequency is higher, stability and reliability problems have been brought during transmission, therefore, sometimes need the influence of adopting some measures to be brought to address these problems, for example signal driving, signal shielding, interference protection measure or the like, concrete embodiment can be to adopt existing mode in the prior art.
In order to transmit farther distance, sometimes need to become differential signal to transmit conversion of signals, for example when distance surpasses certain distance (for example 1 meter) or signal when decay or distortion are arranged or the like, concrete mode can be adopt with prior art in identical mode; Perhaps also can make the reference clock that adopts lower frequency.3.375Mhz (this be 27Mhz 1/8th) for example, and carry out frequency multiplication (8 times) at use side and handle, promptly between clock synchronization control circuit and display card, be connected a frequency multiplier, with to carrying out process of frequency multiplication (generating the clock of 27Mhz after 8 times) from the clock signal of clock synchronization control circuit output, concrete process of frequency multiplication mode can be adopt with prior art in identical mode.
The frame synchronizing signal of frame synchronization control circuit output can output to the RS232 interface of each PC by the mode of RS232, any one among DSR, DTR, RI, CTS, the RTS etc. for example, as shown in Figure 3, it is the connection mode synoptic diagram of RS232, they all are the one-way transmission signals, therefore will avoid two output terminal short circuits when mounted.
Wherein, the display card in above-mentioned each PC can be traditional display card, also can be the GPU display card.
In addition, because present GPU display card generally has 2 display channels, in the design of existing GPU display card, the frame synchronizing signal of these two display channels is generally also inconsistent, and the same clock input of the general employing of two display channels of same GPU display card, therefore, do not have cumulative errors between a plurality of frame synchronizing signals, be generally fixed error, so, when adjusting, can be one by one adjust at the frame synchronizing signal of each display channel of display card, for the very high PC of speed, under the situation that does not influence real-time, also can be to adjust simultaneously.
In above-mentioned elaboration to embodiments of the invention, be to carry out synchronous tiled or synchronous stack demonstration between the output at there being a plurality of PCs to show, and having included only a display card in each PC describes, and in the assembling of the PC of existing reality, may need to adopt a plurality of display cards in the PC, at this moment, at this PC, the signal input part of the mainboard card of this PC is connected with the signal output part of frame synchronization control circuit, the clock signal input terminal of each display card of this PC all is connected with the signal output part of clock synchronization control circuit, wherein, this display card can be common video card, also can be the GPU display card.
At this moment, have under the situation of a plurality of display cards at this some PCs wherein, in synchronous display apparatus of the present invention, all display cards all produce circuit with same reference clock and are connected, the reference clock signal that produces the circuit generation by same reference clock makes the clock signal of each display card synchronous, adjust the frame synchronization output of each display card by the reference frame synchronization signal of same frame synchronization control circuit generation, promptly adopt identical reference frame synchronization signal and reference clock signal to finish display synchronization jointly, owing to adopt same reference clock signal, can not produce clocking error, each frame synchronizing signal can not produce cumulative errors yet, thereby has improved synchronous accuracy and continuation between the shows signal.
Wherein, when the initial start system adjusts synchronously, concrete adjustment mode is identical with mode explained above, for PC, can be one by one the display channel of each display card of this PC to be adjusted, for the very high PC of speed with a plurality of display cards, under the situation that does not influence real-time, can be to adjust simultaneously, concrete adjustment mode repeat them here with of the prior art identical yet.
In view of the above, for this PC with a plurality of display cards, owing to have plural display card in this PC, and each display card has at least one display channel, at this display card is under the situation of GPU display card, each GPU display card generally all has 2 display channels, therefore, when needs splice by hyperchannel output or superpose demonstration, have at PC under the situation of the display card of required number and display channel, it also can be the process of finishing synchronous demonstration by a PC, at this moment, synchronous demonstration of the present invention comprises this PC, include at least one motherboard and at least two display cards in this PC, each display card inserts respectively and is connected on this motherboard, the signal input part of motherboard is connected with the signal output part of frame synchronization control circuit, the clock signal input terminal of each display card all is connected with the signal output part of reference clock generation circuit, the reference clock signal that produces the circuit generation by same reference clock makes the clock signal of each display card synchronous, adjust the frame synchronization output of each display card by the reference frame synchronization signal of same frame synchronization control circuit generation, promptly adopt identical reference frame synchronization signal and reference clock signal to finish display synchronization jointly, owing to adopt same reference clock signal, can not produce clocking error, cumulative errors be can not produce between each frame synchronizing signal yet, thereby synchronous accuracy and continuation between the shows signal improved.
This when showing synchronously by a plurality of display cards in the PC, consider that just the display channel at each display card in this PC carries out synchronously, and need not to carry out synchronously with the synchronizing signal of other outside PCs, therefore, when specific implementation, synchronization control circuit in the aforesaid way can be arranged on the inside of this PC, and can select for use the crystal oscillator of an assigned frequency or resonator as reference clock signal, the crystal oscillator of this assigned frequency or resonator can be pairing crystal oscillator of wherein some display cards or resonator, and the clock signal of its generation is transferred to the clock signal input terminal of each display card.The frame synchronizing signal that can also select one of them display channel for use is as reference frame synchronization signal, and controls or adjust the frame synchronization of other display channels with this reference frame synchronization signal.
Wherein, when the initial start system adjusts synchronously, identical in concrete adjustment mode and the foregoing description, for this mode of the present invention, can be one by one the display channel of each display card to be adjusted, for the very high PC of speed with a plurality of display cards, under the situation that does not influence real-time, can be to adjust simultaneously, concrete adjustment mode repeat them here with of the prior art identical yet.
Embodiment two:
In above-mentioned explanation to embodiment one, be with one independently the frame synchronization control circuit produce reference frame synchronization signal and describe to carry out the frame synchronization adjustment, in fact, also can be to adopt the frame synchronizing signal of display channel of one of them display card as reference frame synchronization signal, and carry out the frame synchronization adjustment in view of the above, thereby can produce reference frame synchronization signal specially.
Referring to shown in Figure 4, it is the structural representation of the embodiment two of synchronous display apparatus of the present invention, in this example, mainly being with the difference of the foregoing description one, is to select for use the frame synchronizing signal of display channel of one of them display card as reference frame synchronization signal in the present embodiment.
As shown in Figure 4, in the synchronous display apparatus of present embodiment, the frame synchronizing signal of the display channel of the display card of PC1, outputing to when display shows, also output to the signal input part of motherboard of other each PC as reference frame synchronization signal, be to be to adopt the frame synchronizing signal of display channel output of display card of PC1 in the present embodiment as reference frame synchronization signal, except other each PCs of PC1 are adjusted the frame synchronizing signal of the display channel of its display card according to this reference frame synchronization signal.Identical in the mode that concrete synchronous display mode and frame synchronization are adjusted and the foregoing description one do not repeat them here.
Wherein, above-mentioned explanation is that the frame synchronizing signal with the display channel of the display card that adopts PC1 is that example describes as reference frame synchronization signal, this explanation only is exemplary explanation, in fact, also can be to select for use other the frame synchronizing signal of display channel of display card of PC as reference frame synchronization signal.
In addition, for some display card, GPU display card for example, it generally has two display channels, therefore, have under the situation that some display card has a plurality of display channels, or all display cards all are positioned under the situation of same PC, can be to adopt the frame synchronizing signal of display channel of appointment, and the frame synchronizing signal of other each display channel be adjusted according to this reference frame synchronization signal as reference frame synchronization signal.
Identical in other technologies feature in the present embodiment and the foregoing description one do not repeat them here.
In the explanation of the various embodiments described above, be to describe in the mode that reference frame synchronization signal is connected to motherboard, in fact, when specific implementation, also can be to adopt custom-designed synchronization control circuit to realize, this synchronization control circuit includes and produces the also reference clock generation circuit of output reference clock signal, the main control part (being referred to as the frame synchronization control circuit) of achieve frame synchro control, and one or more serial line interfaces are (as RS232, RS485 and Ethernet interface etc.), receive each PC respectively by each serial line interface, wherein, this main control part can be by single-chip microcomputer, DSP or FPGA wait and realize control, reference clock generation circuit produces and exports the reference clock signal more than 2, and each reference clock signal all is to drive back output through signal, reference frame synchronization signal and an above frame synchronizing signal are input in this synchronization control circuit, and wherein this reference frame synchronization signal can be the frame synchronizing signal that is selected from one of them display channel output.Below describe at the embodiment of the synchronous display apparatus of the present invention under this embodiment.
Embodiment three:
Referring to shown in Figure 4, be the structural representation of synchronous display apparatus embodiment three of the present invention, it is that the custom-designed synchronization control circuit of above-mentioned employing is realized the simplest a kind of mode in the synchronous control mode.
In diagram, be divided into single-chip microcomputer or FPGA is that example describes with master control part, reference clock produces the reference clock signal clk1 that circuit produced, clk2 is connected respectively to the input end of clock of corresponding two display card (not shown)s, Vh1 represents the frame synchronizing signal from display channel 1, Vh2 represents the frame synchronizing signal from display channel 2, Vh1 as reference frame synchronization signal, FPGA carries out the time contrast to Vh1 and Vh2, compare the difference value between the two, and judge whether this difference value has surpassed the preset range that is allowed, if surpass, then this difference value is delivered to the display channel 2 pairing PC motherboards that produce frame synchronizing signal Vh2 by communication interface, this motherboard is adjusted the display parameter of this display channel 2 according to this difference value, when difference be 0 or reach the preset range of permission after, display parameter are set to initial parameter, perhaps also can be, master control part is divided according to adjustment instruction of this difference value generation, this motherboard is adjusted the display parameter of display channel 2 according to this adjustment instruction, makes the difference value of the frame synchronizing signal of two display channels reach the preset range that is allowed.
Identical in other technologies feature in the present embodiment and the foregoing description one do not repeat them here.
Embodiment four:
Shown in Fig. 5, be the structural representation of the embodiment four of synchronous display apparatus of the present invention, it is the extended mode on the basis of the synchronous display apparatus shown in Fig. 4.
Referring to shown in Figure 5, more display channel needs synchronously, concrete control mode is identical with the mode shown in above-mentioned Fig. 4: reference clock produces the reference clock signal clk1 that circuit produced, clk2......, clkn is connected respectively to the input end of clock of corresponding display card (not shown), Vh1 represents the frame synchronizing signal from display channel 1, Vh2 represents the frame synchronizing signal from display channel 2, ..., Vhn represents the frame synchronizing signal from display channel n, Vh1 as reference frame synchronization signal, FPGA with Vh1 respectively with Vh2, ..., Vhn carries out the time contrast, whether the difference value between judging has separately respectively surpassed the preset range that is allowed, surpassed in difference value under the situation of preset range, the difference value that has surpassed preset range is separately delivered to the motherboard of the pairing PC of display channel that produces this frame synchronizing signal respectively by the corresponding communication interface, each motherboard is adjusted the display parameter of corresponding display channel respectively according to this received difference value, when difference be 0 or reach allowed band after, display parameter are set to initial parameter, perhaps also can be, surpassed under the situation of preset range the master control part branch produces respectively according to each difference value and adjusts instruction in difference value, and will adjust the motherboard that instruction sends to the pairing PC of corresponding display channel respectively, each motherboard is adjusted the display parameter of the display channel of correspondence according to received adjustment instruction respectively, makes the difference value of itself and reference frame synchronization signal reach the preset range that is allowed.
Identical in other technologies feature in the present embodiment and the foregoing description three do not repeat them here.
Realize synchronous mode at the custom-designed synchronization control circuit of employing among the foregoing description three and the embodiment four, concrete synchronizing process can be:
At least from two display channels extract frame synchronizing signals (be embodied in a PC display card each display channel or be the display channel of two PC, " extraction " means may need the shows signal of a circuit from binding, as separating among the DVI, concrete implementation can be to adopt existing mode in the prior art) be transferred to synchronization control circuit respectively, the reference clock signal that reference clock generation circuit produces is connected respectively to the input end of clock of each video card, communicates to connect between synchronization control circuit and the PC;
After master control part branch in the synchronization control circuit receives these frame synchronizing signals, the frame synchronizing signal of selecting or specifying a display channel is as reference frame synchronization signal, frame synchronization to this reference frame synchronization signal and other each display channels is measured time of arrival, obtain the frame synchronization time of arrival and the deviation of reference frame between synchronous time of arrival of each display channel, judge whether this deviate has surpassed the preset range that is allowed, and send to the pairing display card of display channel that deviate has surpassed the preset range that allows and to adjust steering order or to send this deviate;
Corresponding display card is adjusted the display parameter of its corresponding display channel, so that frame synchronization basically identical time of arrival of each display channel after receiving and adjusting steering order or send deviate.
Shows signal after the above-mentioned frame synchronization can directly output to display unit or display shows, also can be to be connected to the signal segmentation circuit, export the realization tiled display again after shows signal cut apart, concrete implementation can be to be that disclosed mode is identical in 200810029953.5 the patented claim with application number, does not repeat them here.
In addition, in the scheme in the foregoing description three, embodiment four, the frame synchronizing signal that is certain display channel that will be extracted is as reference frame synchronization signal, at the frame synchronization control circuit relatively after the frame synchronizing signal and the difference value between this reference frame synchronization signal of the display channel of other each display card, judge whether this difference value has surpassed the preset range that is allowed, if surpass, then corresponding each motherboard is adjusted the frame synchronizing signal of the display channel of corresponding display card according to this difference value.In fact, when realizing, also can be to produce a reference frame synchronization signal by this frame synchronization control circuit, and judge difference value between the frame synchronizing signal of display channel of this reference frame synchronization signal and each display card, judge whether this difference value has surpassed the preset range that is allowed, if surpass, then corresponding motherboard is adjusted the frame synchronizing signal of the display channel of the display card of correspondence according to the difference value of correspondence, concrete adjustment mode is identical with mode in the foregoing description three, four, does not repeat them here.
In addition, above-mentioned each display card, can be all to insert to be connected on the same motherboard, also can be to insert respectively to be connected on the different motherboards, or wherein insert on certain several motherboard and be connected with plural display card, concrete frame synchronization is adjusted identical in mode and the various embodiments described above, does not repeat them here.
According to the synchronous display apparatus of the invention described above, a kind of synchronous display method can also be provided, the concrete method of synchronization is identical with mode in the above elaboration, does not repeat them here.
Because the processing that shows synchronously both can be applied in the processing of stack demonstration, also can be to be applied in the processing of tiled display, therefore, synchronous display apparatus according to the invention described above, the system that the present invention can also provide a kind of display system that superposes, a kind of splice displaying system and stack and splicing to combine, wherein:
This display system that superposes, include overlap-add procedure unit and display unit, also comprise aforesaid synchronous display apparatus of the present invention, wherein, this overlap-add procedure unit is connected with each display card, this overlap-add procedure unit is connected with described display unit, and the signal after the frame synchronization process of each display card outputs to display unit and shows after carrying out overlap-add procedure through the overlap-add procedure unit;
This splice displaying system, include the combination that is spliced by concatenation unit, also comprise aforesaid synchronous display apparatus of the present invention, wherein, each described display card respectively with the corresponding connection of at least one concatenation unit in the described combination, the signal after the frame synchronization process of each display card outputs to respectively on the corresponding concatenation unit and shows.
Above-described embodiment of the present invention only is at the wherein detailed description of several specific embodiments, does not constitute the qualification to protection domain of the present invention.Any modification of being done within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within the claim protection domain of the present invention.
Claims (10)
1. synchronous display apparatus, it is characterized in that, comprise: synchronization control circuit, more than one motherboard, and plural display card, insert on any one motherboard and be connected with at least one display card, described synchronization control circuit comprises the frame synchronization control circuit, reference clock produces circuit, the signal output part of described frame synchronization control circuit is connected with the signal input part of each described motherboard, the signal output part that described reference clock produces circuit is connected with the clock signal input terminal of each described display card, the frame synchronizing signal of display channel that described frame synchronization control circuit produces reference frame synchronization signal or will preset display card is as reference frame synchronization signal, and each described motherboard is adjusted the frame synchronizing signal of the display channel of each corresponding display card according to described reference frame synchronization signal.
2. synchronous display apparatus, it is characterized in that, comprise: synchronization control circuit, more than one motherboard, and plural display card, insert on any one motherboard and be connected with at least one display card, described synchronization control circuit comprises the frame synchronization control circuit, reference clock produces circuit, the signal output part of described frame synchronization control circuit is connected with the signal input part of each described motherboard, the signal output part that described reference clock produces circuit is connected with the clock signal input terminal of each described display card, the shows signal output terminal of each described display card is connected with described frame synchronization control circuit, the frame synchronizing signal of display channel that described frame synchronization control circuit produces reference frame synchronization signal or will preset display card is as reference frame synchronization signal, judge the frame synchronizing signal of display channel of each display card and the deviation range of described reference frame synchronization signal, each described display card respectively shows the frame synchronizing signal of passage accordingly according to the described deviation range adjustment of each display channel of correspondence.
3. synchronous display apparatus according to claim 1 and 2 is characterized in that:
Also comprise the frequency multiplier that is connected between described clock synchronization control circuit and each the described display card;
And/or
Described display card is the GPU display card;
And/or
Described frame synchronization control signal is transferred to described motherboard by DSR or DTR or RI or CTS or RTS signal from described frame synchronization control circuit.
4. synchronous display apparatus according to claim 1 and 2 is characterized in that:
The number of described motherboard is 1, and described motherboard and each described display card are positioned on the same PC;
Perhaps
The number of described motherboard is at least 2, and each motherboard lays respectively on the PC, includes in each PC with described motherboard and inserts at least one the described display card that is connected.
5. synchronous display apparatus according to claim 3 is characterized in that:
The number of described motherboard is 1, and described motherboard and each described display card are positioned on the same PC;
Perhaps
The number of described motherboard is at least 2, and each motherboard lays respectively on the PC, includes at least one the described display card that is connected with described motherboard in each PC.
One kind the stack display system, it is characterized in that, comprise display unit, overlap-add procedure unit, also comprise as any described synchronous display apparatus of claim 1 to 5, each described display card is connected with described overlap-add procedure unit, and described overlap-add procedure unit is connected with described display unit.
7. a splice displaying system is characterized in that, comprises combination, also comprise as any described synchronous display apparatus of claim 1 to 5, each described display card respectively with the corresponding connection of at least one concatenation unit in the described combination.
8. the synchronous display method of a synchronous display apparatus, described synchronous display apparatus comprises: synchronization control circuit, more than one motherboard, and plural display card, insert on any one motherboard and be connected with at least one display card, described synchronization control circuit comprises the frame synchronization control circuit, reference clock produces circuit, the signal output part of described frame synchronization control circuit is connected with the signal input part of each described motherboard, the signal output part that described reference clock produces circuit is connected with the clock signal input terminal of each described display card, and described synchronous display method comprises step:
Each motherboard is adjusted the frame synchronizing signal of the display channel of each display card of correspondence synchronously according to the reference frame synchronization signal of described frame synchronization control circuit.
9. synchronous display method according to claim 8, it is characterized in that, the mode of described synchronous adjustment comprises: detect the reference frame synchronization signal of described frame synchronization control circuit, and after detecting described reference frame synchronization signal Preset Time section, the display unit of each display card of initialization.
10. according to Claim 8 or 9 described synchronous display methods, it is characterized in that, also comprise step: the clock sync signal from described clock synchronization circuit output is carried out process of frequency multiplication, and the clock sync signal after the process of frequency multiplication is sent into the clock signal input terminal of described display card.
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| CN200910042304A CN101763840A (en) | 2009-08-31 | 2009-08-31 | Synchronous display device, stacking splicing display system and synchronous display method thereof |
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| CN200910042304A CN101763840A (en) | 2009-08-31 | 2009-08-31 | Synchronous display device, stacking splicing display system and synchronous display method thereof |
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