CN101594225B - Synchronous receiving circuit and method - Google Patents
Synchronous receiving circuit and method Download PDFInfo
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- CN101594225B CN101594225B CN200810097490A CN200810097490A CN101594225B CN 101594225 B CN101594225 B CN 101594225B CN 200810097490 A CN200810097490 A CN 200810097490A CN 200810097490 A CN200810097490 A CN 200810097490A CN 101594225 B CN101594225 B CN 101594225B
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Abstract
The invention discloses a synchronous receiving circuit and a method. When a transmission end only supplies a data signal but not supplies a frequency signal for a receiving end to execute synchronization, a time sequence of the frequency signal which is used for receiving data and is generated by the synchronous receiving circuit is dynamically regulated so as to achieve a precise synchronous receiving purpose. The synchronous receiving circuit comprises a frequency generator, an edge detector, a synchronous unit and a latching unit, wherein the frequency generator generates a first frequency signal according to an input data signal; the edge detector is used for detecting the edge of the input data signal so as to generate an index signal; the synchronous unit is coupled to the frequency generator and the edge detector and is used for dynamically regulating the first frequency signal according to the index signal; and the latching unit is coupled to the synchronous unit and is used for latching the input data signal according to the regulated first frequency signal.
Description
Technical field
The present invention relates to a kind of circuit for synchronizing that relates to, relate in particular to a kind of synchronous receiving circuit and method.
Background technology
In a communication system, when carrying out transfer of data,, and do not provide frenquency signal to carry out synchronization (synchronization) for receiving terminal if the transmission end only provides data signals, receiving terminal inside need produce frenquency signal voluntarily, to receive synchronously.Among Figure 1A, data signals is not for there being the ideal case of shake (jitter), and its frequency is f MHz, and the frenquency signal that receiving terminal produces is 2f MHz.If receiving terminal lies in each falling edge execution of this frenquency signal and latchs (latch) action, then can obtain the correct latch data shown in Figure 1A.Yet, when data signals has shake, can cause its timing drift, make receiving terminal latched data mistake, shown in Figure 1B.If receiving terminal is in time revised the sequential of the frenquency signal that is produced to signal shake, then timing drift can be accumulated and increasing, causes all mistakes of follow-up latched data.
Summary of the invention
Technical problem to be solved by this invention provides a kind of synchronous receiving circuit; Can only data signals be provided in the transmission end and when not providing frenquency signal to carry out synchronization for receiving terminal; The sequential of the frenquency signal that its inside of dynamic adjustment produces voluntarily, is used for receiving synchronously, and then avoid timing drift.In addition; It also provides a kind of synchronous receiving method; It also can only provide data signals in the transmission end and when not providing frenquency signal to carry out synchronization for receiving terminal, dynamically adjusts the sequential of the frenquency signal that its inside produces voluntarily, is used for receiving synchronously, and then has also avoided timing drift.
In order to solve above technical problem, the invention provides following technical scheme:
The present invention discloses a kind of synchronous receiving circuit, comprises: frequency generator, according to input data signals, synchronized generation first frequency signal; The edge detection device is in order to carry out edge detection to the input data signals, to produce indicating signal; Synchronous unit is coupled to frequency generator and edge detection device, in order to the sequential of dynamic adjustment first frequency signal; And latch units, be coupled to synchronous unit, in order to according to the regulated first frequency signal, latch the input data signals.
The present invention discloses a kind of synchronous receiving method in addition, comprises the following step: according to the input data signals, produce the first frequency signal; The input data signals is carried out edge detection, to produce indicating signal; According to indicating signal, dynamically adjust the sequential of first frequency signal.
Because synchronous receiving circuit of the present invention; Can only data signals be provided in the transmission end and when not providing frenquency signal to carry out synchronization for receiving terminal; The sequential of the frenquency signal that its inside of dynamic adjustment produces voluntarily, is used for receiving synchronously, and then avoided timing drift.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
Figure 1A is the frenquency signal that the existing receiving terminal utilization of explanation produces voluntarily, latchs the sketch map of the data signals of the nothing shake that is received.
Figure 1B is the frenquency signal that the existing receiving terminal utilization of explanation produces voluntarily, latchs the sketch map of the data signals that shake is arranged that is received.
Fig. 2 is the calcspar of one of synchronous receiving circuit of the present invention embodiment.
Fig. 3 is the calcspar of one of synchronous receiving circuit of the present invention preferred embodiment.
Fig. 4 is with a signal sequential chart, the running of the synchronous receiving circuit of key diagram 3.
Fig. 5 is the flow chart of one of synchronous receiving method of the present invention preferred embodiment.
[primary clustering symbol description]
20,30: synchronous receiving circuit 21,31: frequency generator
22,32: edge detection device 23,33: synchronous unit
331: phase counter 332: the sequential adjustment unit
333,334: controlling signal
24,34: latch units
51 ~ 55: the flow process of one of synchronous receiving method preferred embodiment
Embodiment
Fig. 2 is the calcspar of one of synchronous receiving circuit 20 of the present invention embodiment, comprises a frequency generator 21, one edge detector 22, a synchronous unit 23 and a latch units 24.Synchronous receiving circuit 20 receives the input data signals; Do not have and follow the foreign frequency signal; The input data signals that frequency generator 21 foundations are received, synchronized generation one first frequency signal, that is; With the input data signals is the timing reference point, produces follow-up frenquency signal required when wanting latch data.The input data signals is digitized signal, comes representative data with low level and high levle.Edge detection device 22 is in order to the input data signals is carried out edge detection, to produce an indicating signal.Whether edge detection system detecting input data signals produces signal transition (transition), and the rising edge representative switches to high levle from low level, and the falling edge representative switches to low level from high levle.Indicating signal points out to import the signal transition of data signals; Therefore the sequential of indicating signal lags behind the rising edge or the falling edge of input data signals; The amplitude that falls behind is preferably with a decision settling time (set-up time) according to the input data signals; Representative input settling time data signals reaches stable state and wants the time spent when transition, so indicating signal can be used to indicate the time point of input data signals arrival stable state, in order to latching of follow-up data.The purpose of synchronous receiving circuit 20 will be carried out the time point latch with being used for the first frequency signal of latch data exactly, i.e. the rising edge of first frequency signal or falling edge are adjusted to this indicating signal synchronously, and latched data is correct to guarantee.
Synchronous unit 23 is coupled to frequency generator 21 and edge detection device 22, can dynamically adjust the phase place of first frequency signal according to indicating signal, with the sampling time point of optimization first frequency signal representative.Present difference of injection time when between the predetermined state switching points of the opinion point of this indicating signal and first frequency signal; Or title phase difference; Show when indicating signal falls behind the first frequency signal; The time point of promptly importing data signals arrival stable state is later than the first frequency signal and carries out the time point that latchs, and synchronous unit 23 postpones the sequential of first frenquency signal, that is postpones the next one up-down edge of first frenquency signal.On the other hand, when this present difference of injection time showed that indicating signal takes the lead the first frequency signal, synchronous unit 23 is the sequential of first frequency signal in advance.
Latch units 24 is coupled to synchronous unit 23, can latch the input data signals according to the first frequency signal after the adjustment sequential, that is, with regulated first frequency signal sampling input data signals.
Fig. 3 is the calcspar of a preferred embodiment of synchronous receiving circuit 30 of the present invention; Wherein, Frequency generator 31 foundation input data signals, synchronized generation first frequency signal and second frequency signal, the frequency of second frequency signal is an integral multiple of the frequency of first frequency signal.For example, it is the timing reference point that frequency generator 31 can be imported data signals, produces earlier the second frequency signal, again with second frequency signal frequency elimination to produce the first frequency signal.32 pairs of inputs of edge detection device data signals is carried out edge detection, to produce indicating signal.In this embodiment; The sequential of indicating signal lags behind the amplitude of rising edge or falling edge of input data signals except decision settling time according to the input data signals, is that unit represents should settling time with the frequency period (the back literary composition is represented with T) of second frequency signal preferably.For example, if be equivalent to 2T settling time, then edge detection device 32 is preferably advocated (assert) indicating signal in the up-down edge 2T place that lags behind the input data signals.
Synchronous unit 33 comprises a phase counter (phase counter) 331 and one sequential adjustment unit 332.Phase counter 331 is coupled to frequency generator 31 and edge detection device 32, can upgrade a phase meter numerical value according to the second frequency signal; And this phase meter numerical value can be represented the phase place of first frequency signal; For example, the every increase by of the value of phase meter numerical value, promptly represent the first frequency signal from last time initial state switching points experienced the time span of 1T again; And its value is counted to n-1 from 0 circularly; Each count to n-1 from 0 and promptly represent a frequency period that has experienced the first frequency signal, in this embodiment, the frequency of second frequency signal be the first frequency signal frequency n doubly.Therefore, on behalf of present first frequency signal, phase meter numerical value be in what phase place.
When edge detection device 32 was advocated (assert) indicating signal to phase counter 331, phase counter 331 can be by controlling signal 333 outputs phase meter numerical value to sequential adjustment unit 332 at this moment.Because this phase meter numerical value has been represented the phase place of the corresponding first frequency signal of time point of indicating signal opinion; Thereby sequential adjustment unit 332 can estimate the present difference of injection time between the predetermined state switching points of indicating signal and first frequency signal by this, will how to adjust the sequential of first frequency signal with decision.For example, when this present difference of injection time showed that indicating signal falls behind the first frequency signal, sequential adjustment unit 332 was carried out a phase compensation, prolonged the width (as prolonging 1T) of the present frequency of first frequency signal, to postpone the sequential of first frenquency signal.On the other hand; When present difference of injection time shows that indicating signal takes the lead the first frequency signal; Preferably, for avoiding data loss, sequential adjustment unit 332 is carried out resynchronization (re-synchronization); To produce the next frequency of first frequency signal immediately, supply latch units 34 to carry out data latching.Further, sequential adjustment unit 332 can be by controlling signal 334, this phase meter numerical value of resetting.For instance; When sequential adjustment unit 332 desires prolong 1T with the present frequency of first frequency signal; The time that phase meter numerical value in the time of can indicating signal being advocated is experienced also prolongs 1T (become and be 2T); That is keep the same phase count value and reach 2T, that is to say phase compensation 1T, and phase meter numerical value is counted to the end that n-1 Shi Cai represents a frequency period of first frequency signal; On the other hand, sequential adjustment unit 332 can also produce the next frequency of first frequency signal immediately by controlling signal 334 replacement phase counters 331, and phase meter numerical value is reset to 0, restarts counting with indication from this next one frequency.
Fig. 4 is with a signal sequential chart, and the running of the synchronous receiving circuit 30 of the 3rd figure is described.In Fig. 4; Synchronous receiving circuit 30 can be implemented on a display port (Display Port) interface; And the input data signals is auxiliary (AUX) channel signal of this display port interface, and its frequency is 1MHz, and does not have the foreign frequency signal of following; Frequency generator 31 produces the first frequency signal of 2MHz and the second frequency signal of 16MHz, to receive AUX channel signal.The 4th figure has shown the relative timing of AUX channel signal, first frequency signal, second frequency signal, indicating signal and phase meter numerical value, and wherein, latch units 34 is carried out data latching in the falling edge of each first frequency signal; After edge detection device 32 advocates that indicating signal system lags behind each up-down edge of AUX channel signal; The 2nd rising edge place of second frequency signal; The i.e. position of about 2T; This can be according to design requirement change suitable length, with the settling time of reflection AUX channel signal, and the sequential point of the AUX channel signal of guaranteeing correctly to take a sample; The phase meter numerical value of phase counter 331 ties up in each frequency period of first frequency signal and counts to 7 from 0.
In this embodiment; Desirable situation is; Phase meter numerical value when indicating signal produces is 7; So can be considered between indicating signal and first frequency signal does not have difference of injection time, presents the state of semaphore lock (lock), and guarantees that the falling edge of first frequency signal can correctly latch the AUX channel signal that is in stable state.Yet shown in the 4th figure, when the 5th, 8 frequency period of first frequency signal, the phase meter numerical value when indicating signal is advocated is 7, and it is poor to need not compensation of phase, presents the state of semaphore lock; 1st, during 2,3,4,7 frequency periods; Phase meter numerical value when indicating signal is advocated is 0 or 1 (two indicating signals are arranged in the 4th, 7 frequency period, all refer to previous here), and sequential adjustment unit 332 judges that indicating signal lags behind the first frequency signal; And the excute phase compensation; In this embodiment,, know this technological personage and can make other and possibly change the width extending 1T of the present frequency of first frequency signal.Sequential adjustment unit 332 is via controlling signal 334, and the time that the phase meter numerical value when indicating signal is produced is experienced also prolongs 1T, and for example, in the 1st frequency period, the time lengthening that phase meter numerical value 1 is experienced is 2T; During the 7th frequency period, the phase meter numerical value when back indicating signal produces is 6, sequential adjustment unit 332 thereby judge that this indicating signal takes the lead the first frequency signal; Move and carry out to reset; With the 8th frequency of real-time generation first frequency signal, and phase meter numerical value is reset to 0, in this embodiment via controlling signal 334; Sequential adjustment unit 332 is in response to count value dynamic compensation 1T phase place or synchronous again first frequency signal, the count value of for example resetting.
Fig. 5 is the flow chart of a preferred embodiment of synchronous receiving method of the present invention, and it comprises the following step:
Step 51: according to an input data signals, synchronized generation first frequency signal and second frequency signal, wherein the frequency of second frequency signal is an integral multiple of the frequency of first frequency signal.
Step 52: this input data signals is carried out edge detection, and to produce an indicating signal, wherein the sequential of this indicating signal is that a rising edge or that lags behind this input data signals descends because of preset distance place, for example a 2T.
Step 53: according to the second frequency signal, produce a phase meter numerical value, wherein this phase meter numerical value is represented the phase place of first frequency signal.
Step 54:, dynamically adjust the sequential of first frequency signal according to this indicating signal.
Step 55:, latch this input data signals according to the regulated first frequency signal.
In the step 51, the first frequency signal is preferably produced by second frequency signal frequency elimination.In the step 52, the sequential of indicating signal lags behind the rising edge of input data signals or the amplitude of falling edge, is according to suitably determining a settling time of importing data signals.
In the step 54, the phase meter numerical value when being advocated by this indicating signal can be judged the present difference of injection time between indicating signal and first frequency signal.When this present difference of injection time shows that indicating signal falls behind the first frequency signal, postpone the sequential of first frenquency signal; When this present difference of injection time shows that indicating signal takes the lead the first frequency signal, shift to an earlier date the sequential of first frequency signal.In a preferred embodiment, when this present difference of injection time showed that indicating signal falls behind the first frequency signal, the phase place of dynamic compensation first frequency signal was with the width of the present frequency that prolongs the first frequency signal; When this present difference of injection time shows that indicating signal takes the lead the first frequency signal, synchronous again first frequency signal, the phase meter numerical value of for example resetting is to produce the next frequency of first frequency signal immediately.
Synchronous receiving method of the present invention can be applied to a display port interface, and the input data signals is the AUX channel signal of display port interface.It should be noted that; The present invention is particularly conducive to sync signal at a high speed and receives; Because in the environment of high-speed transfer, perhaps because the elongation of high-speed transfer linear distance, for example display port connecting line; Signal jitter (jitter) can be along with fast frequency be accumulated apace, and the conception of dynamic compensation frenquency signal of the present invention can realize accurately getting the also purpose of data.
In sum, the present invention discloses a kind of synchronous receiving circuit, comprises frequency generator, edge detection device, synchronous unit and latch units; Frequency generator according to the input data signals, produces the first frequency signal; The edge detection device is in order to carry out edge detection to the input data signals, to produce indicating signal; Synchronous unit is coupled to frequency generator and edge detection device, in order to according to indicating signal; Dynamically adjust the first frequency signal; The opinion time point system of indicating signal lags behind the rising edge of input data signals or descends because of a preset distance place, and preset distance system is according to decision settling time of input data signals, for example; When synchronous unit when the opinion time point of indicating signal falls behind a predetermined state switching points of first frequency signal; The sequential that postpones first frenquency signal, and when synchronous unit during in the predetermined state switching points of the leading first frequency signal of the opinion time point of this indicating signal, the sequential of first frequency signal in advance; Latch units is coupled to this synchronous unit, in order to according to this regulated first frequency signal, latchs the input data signals.
The present invention also discloses a kind of synchronous receiving method, comprises step: according to the input data signals, produce the first frequency signal; The input data signals is carried out edge detection, to produce indicating signal; According to indicating signal, dynamically adjust the sequential of first frequency signal, for example; Difference of injection time between detecting indicating signal and first frequency signal then according to difference of injection time, is dynamically adjusted the sequential of first frequency signal; For example, when one of the backward first frequency signal of indicating signal is scheduled to state switching points, postpone the sequential of first frenquency signal; Perhaps, when indicating signal takes the lead the predetermined state switching points of first frequency signal, shift to an earlier date the sequential of first frequency signal; When indicating signal and first frequency signal do not have difference of injection time, locking first frequency signal; According to dynamic regulated first frequency signal, latch the input data signals.Further, according to the input data signals, synchronized generation second frequency signal, the frequency of second frequency signal is the integral multiple of the frequency of first frequency signal; And, according to the second frequency signal, upgrade phase meter numerical value, and phase meter numerical value is represented the phase place of first frequency signal.For example; The phase meter numerical value of dynamic adjustment step system when indicating signal is advocated shows when one of the backward first frequency signal of this indicating signal is scheduled to state switching points; Carry out a phase compensation; Width with the present frequency that prolongs this first frequency signal; It is long that the width that for example prolongs the present frequency of first frequency signal reaches one-period of second frequency signal, and this phase meter numerical value when indicating signal is advocated is when showing the predetermined state switching points of the leading first frequency signal of indicating signal, and replacement first frequency signal is to produce next frequency immediately.
The above is to utilize preferred embodiment to specify the present invention, and unrestricted scope of the present invention.Allly know this skill personage and all can understand, can make many possibly the variation, still do not break away from the spirit and scope of the present invention according to the announcement of above embodiment.
Claims (20)
1. the circuit of a synchronous receiving data is characterized in that, it comprises:
One frequency generator according to an input data signals, produces a first frequency signal;
The one edge detector is in order to this input data signals is carried out edge detection, to produce an indicating signal;
One synchronous unit is coupled to this frequency generator and this edge detection device, in order to according to this indicating signal, dynamically adjusts this first frequency signal; And
One latch units is coupled to this synchronous unit, in order to according to this regulated first frequency signal, latchs this input data signals.
2. the circuit of synchronous receiving data as claimed in claim 1 is characterized in that, the opinion time point of said indicating signal is at a preset distance place of a rising edge that lags behind this said input data signals or a falling edge.
3. the circuit of synchronous receiving data as claimed in claim 2 is characterized in that, said preset distance is the settling time decision according to said input data signals.
4. the circuit of synchronous receiving data as claimed in claim 1 is characterized in that, when said synchronous unit falls behind a predetermined state switching points of said first frequency signal in the opinion time point of this indicating signal, postpones the sequential of said first frequency signal.
5. the circuit of synchronous receiving data as claimed in claim 1 is characterized in that, said synchronous unit shifts to an earlier date the sequential of said first frequency signal when a predetermined state switching points of the leading said first frequency signal of the opinion time point of this indicating signal.
6. the circuit of synchronous receiving data as claimed in claim 1 is characterized in that, said frequency generator is according to said input data signals; Synchronized generation one second frequency signal; The frequency of said second frequency signal is an integral multiple of the frequency of said first frequency signal, and said synchronous unit comprises a phase counter, in order to the said second frequency signal of foundation; Upgrade a phase meter numerical value, said phase meter numerical value is represented the phase place of said first frequency signal.
7. the circuit of synchronous receiving data as claimed in claim 6 is characterized in that, said first frequency signal is to be produced by said second frequency signal frequency elimination.
8. the circuit of synchronous receiving data as claimed in claim 6 is characterized in that, said synchronous unit more comprises:
One sequential adjustment unit is coupled to said phase counter and said frequency generator, and the said phase meter numerical value when advocating according to said indicating signal is dynamically adjusted the sequential of said first frequency signal.
9. the circuit of synchronous receiving data as claimed in claim 8; It is characterized in that; Said phase meter numerical value when said indicating signal is advocated shows when said indicating signal lags behind said first frequency signal; Said sequential adjustment unit is carried out a phase compensation, with the width of the present frequency that prolongs said first frequency signal.
10. the circuit of synchronous receiving data as claimed in claim 8; It is characterized in that; When the said phase meter numerical value when said indicating signal is advocated shows the leading said first frequency signal of said indicating signal; The said sequential adjustment unit said first frequency signal of resetting is to produce the next frequency of said first frequency signal immediately.
11. the circuit of synchronous receiving data as claimed in claim 1 is characterized in that, the circuit system of said synchronous receiving data is applied to a display port interface, and said input data signals system is an auxiliary channel signal of said display port interface.
12. the method for a synchronous receiving data is characterized in that, it comprises:
According to an input data signals, produce a first frequency signal;
Said input data signals is carried out edge detection, to produce an indicating signal; And
According to said indicating signal, dynamically adjust the sequential of said first frequency signal;
According to said dynamic regulated first frequency signal, latch said input data signals.
13. the method for synchronous receiving data as claimed in claim 12 is characterized in that, said method is auxiliary (AUX) passage that is applied to a display port interface.
14. the method for synchronous receiving data as claimed in claim 12 is characterized in that, said dynamic adjustment step comprises:
Detect the difference of injection time between said indicating signal and said first frequency signal; And
According to said difference of injection time, dynamically adjust the sequential of said first frequency signal.
15. the method for synchronous receiving data as claimed in claim 12 more comprises step:, lock said first frequency signal when between said indicating signal and said first frequency signal during no difference of injection time.
16. the method for synchronous receiving data as claimed in claim 12 is characterized in that, the opinion time point of said indicating signal is at a preset distance place of a rising edge that lags behind said input data signals or a falling edge.
17. the method for synchronous receiving data as claimed in claim 12 is characterized in that, said dynamic adjustment step is when one of the backward said first frequency signal of said indicating signal is scheduled to state switching points, postpones the sequential of said first frequency signal.
18. the method for synchronous receiving data as claimed in claim 12 is characterized in that, said dynamic adjustment step is when one of the leading said first frequency signal of said indicating signal is scheduled to state switching points, shifts to an earlier date the sequential of said first frequency signal.
19. the method for synchronous receiving data as claimed in claim 12 is characterized in that, it further comprises:
According to said input data signals, synchronized generation one second frequency signal, the frequency of said second frequency signal is an integral multiple of the frequency of said first frequency signal; And
According to said second frequency signal, upgrade a phase meter numerical value, wherein said phase meter numerical value is represented the phase place of said first frequency signal.
20. the method for synchronous receiving data as claimed in claim 19; It is characterized in that; Said dynamic adjustment step is that the said phase meter numerical value when said indicating signal is advocated shows when one of the backward said first frequency signal of said indicating signal is scheduled to state switching points; Carry out a phase compensation, with the width of the present frequency that prolongs said first frequency signal.
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| CN200810097490A CN101594225B (en) | 2008-05-30 | 2008-05-30 | Synchronous receiving circuit and method |
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| CN102904562B (en) * | 2011-07-26 | 2015-02-25 | 宏碁股份有限公司 | Multisampling frequency circuit and multisampling frequency method |
| TWI487302B (en) * | 2011-10-12 | 2015-06-01 | Raydium Semiconductor Corp | Sampling phase selection method for a stream of data bits |
| CN103179410A (en) * | 2011-12-26 | 2013-06-26 | 联咏科技股份有限公司 | Shutter glasses, three-dimensional image system and shutter glasses control method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1909376A (en) * | 2005-05-04 | 2007-02-07 | 瑞昱半导体股份有限公司 | Phase and frequency detection circuits |
| CN101063984A (en) * | 2006-04-28 | 2007-10-31 | 鸿富锦精密工业（深圳）有限公司 | system and method for automatically arranging order of picture frame |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1909376A (en) * | 2005-05-04 | 2007-02-07 | 瑞昱半导体股份有限公司 | Phase and frequency detection circuits |
| CN101063984A (en) * | 2006-04-28 | 2007-10-31 | 鸿富锦精密工业（深圳）有限公司 | system and method for automatically arranging order of picture frame |
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| Title |
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| JP特开2003-188864A 2003.07.04 |
| JP特开平10-247954A 1998.09.14 |
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