WO2020061785A1

WO2020061785A1 - Video frame synchronization system, video processing device and video frame synchronization method

Info

Publication number: WO2020061785A1
Application number: PCT/CN2018/107448
Authority: WO
Inventors: 宗靖国; 周晶晶; 刘伟欣
Original assignee: 西安诺瓦电子科技有限公司
Priority date: 2018-09-26
Filing date: 2018-09-26
Publication date: 2020-04-02
Also published as: CN112074896B; CN112074896A

Abstract

Disclosed is a video frame synchronization system, comprising: a synchronization signal detection comparator, comprising a reference field synchronization signal input end, a feedback field synchronization signal input end and a detection comparison result output end; a controller connected to the detection comparison result output end of the synchronization signal detection comparator; a programmable clock generator connected to the controller; a video timing generator comprising a video timing configuration parameter input end, a pixel clock signal input end and a video timing signal output end, wherein the video timing configuration parameter input end is connected to the controller, the pixel clock signal input end is connected to the programmable clock generator, and the video timing signal output end is connected to the feedback field synchronization signal input end of the synchronization signal detection comparator; and a video encoder connected to the video timing signal output end of the video timing generator. Further disclosed are a video processing device and a video frame synchronization method.

Description

Video frame synchronization system, video processing device and video frame synchronization method

Technical field

The present application relates to the field of display technology, and in particular, to a video frame synchronization system, a video processing device, and a video frame synchronization method.

Background technique

Genlock (video output phase-locking) technology is used to control the timing parameters of the output video signal of the device, such as: HS (line synchronization signal), VS (field synchronization signal), PCLK (pixel clock signal), so that the timing parameters are especially VS ( The field synchronization signal) is synchronized with the external reference signal to achieve the purpose of synchronizing the output video signal with the reference signal. When multiple video processing devices (video splicers) work together to splice large video images, it is necessary to ensure that the output of all devices is synchronized, and a single device needs to enable the Genlock (video output phase lock) function to synchronize the video output to the same reference signal. If there is no frame synchronization function, the edges of the output image will appear torn between devices. In a studio environment, the video processing device outputs video to the screen. When the camera is shooting scenes that include the screen, the camera video sampling needs to be synchronized with the refresh of the output image on the screen. Otherwise, the image on the screen captured by the camera will have scrolling stripes.

Therefore, it is particularly important to provide a video frame synchronization system, a video processing device, and a video frame synchronization method capable of solving the above problems.

Summary of the Invention

The embodiments of the present application provide a video frame synchronization system, a video processing device, and a video frame synchronization method, which can keep a target field synchronization signal and a reference field synchronization signal always synchronized.

In one aspect, a video frame synchronization system provided by an embodiment of the present application includes: a synchronization signal detection comparator including a reference field synchronization signal input terminal, a feedback field synchronization signal input terminal, and a detection comparison result output terminal; a controller, connected The detection and comparison result output terminal of the synchronization signal detection comparator; a programmable clock generator connected to the controller; a video timing generator including a video timing configuration parameter input terminal, a pixel clock signal input terminal, and a video timing A signal output terminal, the video timing configuration parameter input terminal is connected to the controller, the pixel clock signal input terminal is connected to the programmable clock generator, and the video timing signal output terminal is connected to the synchronization signal detection comparator. The feedback field synchronization signal input terminal; and a video encoder connected to the video timing signal output terminal of the video timing generator.

In an embodiment of the present application, the synchronization signal detection comparator further includes: a phase comparison unit, configured to compare a feedback field synchronization signal input from the feedback field synchronization signal input terminal with a reference field synchronization signal input. The phase of the reference field synchronization signal input at the terminal; a frequency comparison unit for comparing the frequencies of the feedback field synchronization signal and the reference field synchronization signal; a comparison result generation unit for comparing the phase comparison unit and the frequency The comparison result of the comparison unit generates a frequency adjustment amount of the pixel clock signal.

In an embodiment of the present application, the video timing signal output terminal includes: a target field synchronization signal output terminal, a line synchronization signal output terminal, an effective display data strobe signal output terminal, and a pixel clock signal output terminal; the target field The synchronization signal output terminal is connected to the feedback field synchronization signal input terminal of the synchronization signal detection comparator; the video encoder is connected to the target field synchronization signal output terminal, the line synchronization signal output terminal, and the effective display data. A strobe signal output terminal and the pixel clock signal output terminal.

In an embodiment of the present application, the video frame synchronization system further includes a video processor, and an output end of the video processor is connected to the video data input end of the video encoder.

In another aspect, a video processing device provided by an embodiment of the present application includes a programmable logic device including a reference field synchronization signal source input terminal, a detection and comparison result output terminal, a video timing configuration parameter input terminal, and a pixel clock signal input. Terminal, video timing signal output terminal and video data output terminal; a controller connected to the detection and comparison result output terminal of the programmable logic device and the video timing configuration parameter input terminal; a programmable clock generator connected to the A controller and the pixel clock signal input terminal of the programmable logic device; and a video encoder connected to the video timing signal output terminal and the video data output terminal of the programmable logic device; wherein, the The programmable logic device is configured to obtain a reference field synchronization signal according to a signal input from a source input terminal of the reference field synchronization signal, detect a frame frequency of the reference field synchronization signal, and output the frame frequency through the detection and comparison result output terminal. According to the video timing configuration parameter input from the video timing configuration parameter input terminal, A pixel clock signal input from a prime clock signal input terminal to generate a target field synchronization signal, output the target field synchronization signal through the video timing signal output terminal, compare the reference field synchronization signal and the target field synchronization signal, Obtaining a frequency adjustment amount of the pixel clock signal according to a result of the comparison, and outputting the frequency adjustment amount to the controller through the detection and comparison result output terminal so that the controller controls the frequency adjustment amount according to the frequency adjustment amount The programmable clock generator updates the pixel clock signal, and updates the target field synchronization signal according to the updated pixel clock signal.

In an embodiment of the present application, the reference field synchronization signal supply source input terminal includes a plurality of video signal input terminals and a genlock signal input terminal.

In an embodiment of the present application, the programmable logic device is further configured to process video data to obtain processed video data, and output the processed video data through the video data output terminal.

On the other hand, a video frame synchronization method provided by an embodiment of the present application includes: acquiring a reference field synchronization signal and detecting a frame frequency of the reference field synchronization signal; and calculating a pixel clock signal according to an output resolution and the frame frequency. Generating a clock configuration parameter according to the frequency of the pixel clock signal, and generating a video timing configuration parameter according to the output resolution; generating a pixel clock signal according to the clock configuration parameter; Generating a target field synchronization signal driven by the pixel clock signal; comparing the reference field synchronization signal with the target field synchronization signal to obtain a comparison result, and obtaining a frequency adjustment amount of the pixel clock signal according to the comparison result; Updating the pixel clock signal with the frequency and the frequency adjustment amount of the pixel clock signal; and updating the target field synchronization signal under the driving of the updated pixel clock signal according to the video timing configuration parameter.

In an embodiment of the present application, the step of comparing the reference field synchronization signal and the target field synchronization signal to obtain a comparison result includes: comparing a phase of the reference field synchronization signal with a phase of the target field synchronization signal. To obtain a phase relative relationship; compare the frequency of the reference field synchronization signal with the frequency of the target field synchronization signal to obtain a frequency relative relationship; and use the phase relative relationship and the frequency relative relationship as the comparison result.

In an embodiment of the present application, the step of obtaining a reference field synchronization signal includes: receiving an input video signal and / or a genlock signal; and obtaining at least one field synchronization based on the input video signal and / or the genlock signal. A signal; selecting a field sync signal from the at least one field sync signal as the reference field sync signal.

The above technical solution may have one or more of the following advantages: By redesigning the structure of the video frame synchronization system, the target field synchronization signal and the reference field synchronization signal can be kept synchronized at all times.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solutions of the embodiments of the present application more clearly, the drawings used in the description of the embodiments are briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. Those of ordinary skill in the art can obtain other drawings according to the drawings without paying creative labor.

FIG. 1A is a schematic structural diagram of a video frame synchronization system according to an embodiment of the present application; FIG.

FIG. 1B is a schematic structural diagram of another video frame synchronization system according to an embodiment of the present application; FIG.

2A is a schematic structural diagram of a video processing device according to another embodiment of the present application;

2B is a connection diagram of an output video signal and a Genlock signal that are always synchronized in another embodiment of the present application;

2C is a connection diagram of an output video signal and an input video signal that are always synchronized in another embodiment of the present application;

3A is a schematic flowchart of a video frame synchronization method according to another embodiment of the present application;

3B is a schematic diagram showing the relationship between Vtotal and Htotal and a reference field synchronization signal, a target field synchronization signal, and a line synchronization signal according to another embodiment of the present application;

4A is a schematic diagram of a phase relationship between a reference field synchronization signal and a field synchronization signal according to another embodiment of the present application;

4B is another schematic diagram of another phase relationship between a reference field synchronization signal and a field synchronization signal according to another embodiment of the present application;

5A is a schematic diagram of a frequency relationship between a reference field synchronization signal and a field synchronization signal according to another embodiment of the present application;

5B is another schematic diagram of another frequency relationship between a reference field synchronization signal and a field synchronization signal according to another embodiment of the present application.

detailed description

In the following, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

As shown in FIG. 1A, a video frame synchronization system 10 provided by an embodiment of the present application mainly includes a synchronization signal detection comparator 11, a controller 13, a programmable clock generator 15, a video timing generator 17, and a video. Encoder 19.

The synchronization signal detection comparator 11 includes, for example, a reference field synchronization signal input terminal 111, a feedback field synchronization signal input terminal 113, and a detection comparison result output terminal 115. Specifically, the synchronization signal detection comparator 11 receives the reference field synchronization signal through the reference field synchronization signal input terminal 111, measures the frame rate of the reference field synchronization signal, and outputs the reference field synchronization through the detection and comparison result output terminal 115. The frame rate of the signal.

The controller 13 is connected to the detection and comparison result output terminal 115 of the synchronization signal detection comparator 11, for example. The controller 13 includes, for example, a microcontroller. Specifically, the microcontroller is implemented by, for example, a single-chip microcomputer. Specifically, the controller 13 receives, for example, the frame rate of the reference field synchronization signal output by the detection and comparison result output terminal 115 of the synchronization signal detection comparator 11 according to the output resolution and the frame of the reference field synchronization signal. Frequency calculation to obtain the frequency of the pixel clock signal, and generate a clock configuration parameter according to the frequency of the pixel clock signal, and generate a video timing configuration parameter according to the output resolution.

The programmable clock generator 15 is connected to the controller 13, for example. . Specifically, the programmable clock generator 15 receives, for example, the clock configuration parameter generated by the controller 13 and generates a pixel clock signal according to the clock configuration parameter.

The video timing generator 17 includes, for example, a video timing configuration parameter input terminal 171, a pixel clock signal input terminal 173, a video timing signal output terminal 175, a video timing configuration parameter input terminal 171 connected to the controller 13, and a pixel clock signal input terminal 173 connected to a programmable The clock generator 15, the video timing signal output terminal 175 is connected to the feedback field synchronization signal input terminal 113 of the synchronization signal detection comparator 11. Specifically, the video timing generator 17 receives the video timing configuration parameter generated by the controller 13 through the video timing configuration parameter input terminal 171, and generates a target field under the driving of the pixel clock signal according to the video timing configuration parameter. The synchronization signal is output through the video timing signal output terminal 175.

It is worth mentioning here that in actual application, the video timing generator 17 generates not only the target field synchronization signal under the driving of the pixel clock signal according to the video timing configuration parameters, but the actual generated It is a video timing signal including the pixel clock signal, the target field synchronization signal, the line synchronization signal (HS), and the effective display data strobe signal (DE). The video timing signals are output through the video timing signal output terminal 175 together. Correspondingly, the video timing signal output terminal 175 includes a target field synchronization signal output terminal for outputting the target field synchronization signal, a line synchronization signal output terminal for outputting the line synchronization signal, and outputting the effective display. Data strobe signal effective display data strobe signal output terminal and pixel clock signal output terminal for outputting the pixel clock signal; the target field synchronization signal output terminal is connected to the feedback field of the synchronization signal detection comparator Synchronous signal input terminal; video timing signal output terminal 175 is the target field synchronization signal output terminal, the line synchronization signal output terminal, the effective display data strobe signal output terminal, and the pixel clock signal output terminal, respectively. Video encoder 19.

Specifically, the video encoder 19 is, for example, configured to receive the video timing signal output from the video timing signal output terminal 175, and perform video processing on the video signal received through the video data input terminal 191 under the control of the video timing signal. Output after processing such as encoding, for example, display to the display. The video encoder 19 is, for example, an HDMI video encoder.

The synchronization signal detection comparator 11 is further configured to receive, via the feedback field synchronization signal input terminal 113, the target field synchronization signal in the video timing signal output by the video timing generator 17 through the video timing signal output terminal 175, and compare the target field synchronization signal. Reference the field synchronization signal and the target field synchronization signal, and obtain a frequency adjustment amount of the pixel clock signal according to a result of the comparison; the controller 13 is further configured to, for example, according to the frequency and the pixel clock signal The frequency adjustment amount updates the clock configuration parameter to obtain the updated clock configuration parameter; the programmable clock generator 15 is further configured to update the pixel clock signal to obtain the updated pixel clock signal according to the updated clock configuration parameter; video timing generation The comparator 17 is further configured to update the target field synchronization signal to obtain the updated target field synchronization signal under the driving of the updated pixel clock signal according to the video timing configuration parameter; and then, the synchronization signal detection comparator 11 and the controller 13 The programmable clock generator 15 and the video timing generator 17 continue to execute such a cycle. The looping process is that the synchronization signal detection comparator 11 continuously compares the updated target field synchronization signal obtained from the video timing generator 17 with the reference field synchronization signal and obtains the frequency adjustment amount of the pixel clock signal according to the comparison result. The controller 13 adjusts and controls the programmable clock generator 15 and the video timing generator 17 according to the frequency adjustment amount to finally update the target field synchronization signal output by the video timing generator 17. In this way, the video frame synchronization system 10 achieves that the target field synchronization signal output by the video timing generator 17 is always synchronized with the reference field synchronization signal by fine-tuning the target field synchronization signal.

The synchronization signal detection comparator 11 and the video timing generator 17 are implemented by, for example, an FPGA chip. Specifically, the synchronization signal detection comparator 11 and the video timing generator 17 are implemented on the same FPGA chip, for example. Of course, the synchronization signal detection comparator 11 and the video timing generator 17 can also be implemented by other discrete components. As shown in FIG. 1B, in other embodiments, the video frame synchronization system 10 may further include, for example, a video processor 18. The video processor 18 is, for example, a Nova video processor V900 or another suitable video processor. The output terminal 181 of the video processor 18 is connected to the video data input terminal 191 of the video encoder 19, and is used to perform video processing on the input video signal, such as stitching and rotation, and then output the video signal to the video encoder 19 through the output terminal 181 of the video processor 18. Video data input terminal 191.

The synchronization signal detection comparator 11 further includes, for example, a phase comparison unit 1101, a frequency comparison unit 1103, and a comparison result generation unit 1105. Specifically, the phase comparison unit 1101 is used to compare the phase of the feedback field synchronization signal inputted from the feedback field synchronization signal input terminal 113 and the reference field synchronization signal inputted from the reference field synchronization signal input terminal 111; for example, the frequency comparison unit 1103 is used to The frequencies of the feedback field synchronization signal and the reference field synchronization signal are compared; for example, the comparison result generating unit 1105 is configured to generate a frequency adjustment amount of the pixel clock signal according to a comparison result of the phase comparison unit 1101 and the frequency comparison unit 1103.

As shown in FIG. 2A, a video processing device 20 according to another embodiment of the present application mainly includes a programmable logic device 21, a controller 23, a programmable clock generator 25, and a video encoder 27.

The programmable logic device 21 includes, for example, a reference field synchronization signal source input terminal 2101, a detection comparison result output terminal 2103, a video timing configuration parameter input terminal 2105, a pixel clock signal input terminal 2107, a video timing signal output terminal 2108, and video data. Output 2109. The reference field synchronization signal supply source input terminal 2101 includes, for example, a plurality of video signal input terminals and a genlock signal input terminal.

Specifically, the programmable logic device 21 further includes, for example, a synchronization signal detection and comparison unit 211, a clock generation unit 213, a video processing unit 215, a multiplexer 217, an input detection and synchronization signal separation unit 218, and an input detection unit 219. The programmable logic device 21 is, for example, an FPGA chip.

The synchronization signal detection and comparison unit 211 is connected to the input detection and synchronization signal separation unit 218 and the input detection unit 219 through a multiplexer 217, for example. The input detection and synchronization signal separation unit 218 and the input detection unit 219 are respectively connected to the multiple video signal input terminals and the genlock signal input terminal of the reference field synchronization signal input terminal 2101, and the input detection and synchronization signal separation The unit 218 is configured to receive multiple input video signals (such as INPUTA, INPUTB, and INPUTC, etc.) as shown in FIG. 2A through the multiple video signal input terminals of the reference field synchronization signal source input terminal 2101, and Multiple input video signals are used for input detection and synchronization signal separation. The input detection unit 219 is configured to receive a Genlock (genlock) signal through the genlock signal input terminal of the reference field synchronization signal source input terminal 2101, and perform input detection on the Genlock signal. It is worth mentioning here that, in practical applications, the reference video signal input source 2101 of the plurality of video signal input terminals and the genlock signal input terminal, for example, only one or other number of input terminals have inputs Is not limited to having inputs. The multiplexer 217 is used, for example, to receive multiple signals output by the input detection and synchronization signal separation unit 218 and the input detection unit 219, and selects one signal to output to the synchronization signal connected thereto under the direct or indirect control of the controller 23. Detection and comparison unit 211.

The synchronization signal detection and comparison unit 211 is also connected to the timing generation unit 213 and the detection and comparison result output terminal 2103, for example. The timing generation unit 213 is connected to, for example, a video timing configuration parameter input terminal 2105, a pixel clock signal input terminal 2107, and a video timing signal output terminal 2108. The video processing unit 215 is connected to a video data output terminal 2109.

The controller 23 is connected to the detection comparison result output terminal 2103 and the video timing configuration parameter input terminal 2105, for example. The controller 23 includes, for example, a microcontroller. Specifically, the microcontroller is implemented by, for example, a single-chip microcomputer.

The programmable clock generator 25 is connected to the controller 23 and the pixel clock signal input terminal 2107, for example.

Specifically, the programmable logic device 21 is, for example, used to obtain a reference field synchronization signal according to a signal input from the reference field synchronization signal supply source input terminal 2101, detect a frame rate of the reference field synchronization signal, and output a signal through a detection and comparison result output terminal 2103. According to the frame rate, the input video sequence configuration parameter input terminal 2105 according to the video sequence configuration parameter input is driven by the pixel clock signal received through the pixel clock signal input terminal 2107 to generate a target field synchronization signal and output through the video timing signal output terminal 2108. Comparing the target field synchronization signal with the reference field synchronization signal and the target field synchronization signal, obtaining a frequency adjustment amount of the pixel clock signal according to a result of the comparison, and outputting the detected result through the comparison result output terminal 2103 The frequency adjustment amount reaches the controller 23 to control the programmable clock generator 25 to update the pixel clock signal according to the frequency adjustment amount, and update the target field synchronization signal according to the updated pixel clock signal.

It is worth mentioning here that, in practical application, the programmable logic device 21 is driven by the pixel clock signal received through the pixel clock signal input terminal 2107 according to the video timing configuration parameter received through the video timing configuration parameter input terminal 2105. Is not only the target field synchronization signal, but it actually generates a video timing signal including the pixel clock signal, the target field synchronization signal, the line synchronization signal (HS), and the effective display data strobe signal (DE) . The video timing signals are output through the video timing signal output terminal 2108 together.

The video encoder 27 is connected to a video timing signal output terminal 2108 and a video data output terminal 2109, for example. The video encoder 27 is, for example, an HDMI video encoder.

The programmable logic device 21 is also used to process the video data through the video processing unit 215, such as stitching and rotation, to obtain processed video data, and output the processed video data to the video encoder 27 through the video data output terminal 2109.

The video encoder 27 is, for example, configured to receive the video timing signal output from the video timing signal output terminal 2108, and to control the processed video data output to the received video data output terminal 2109 under the control of the video timing signal. Output after video encoding and other processing, for example, output to the display.

The video processing device 20 achieves the goal of ensuring that the target field synchronization signal and the reference field synchronization signal output by the timing generating unit 213 are always synchronized by fine-tuning the target field synchronization signal, thereby ensuring that the video signal output by the video encoder 27 is synchronized with the reference field. The provider of the signal (such as an input video signal or a Genlock signal) is always synchronized.

As shown in FIG. 2B, it is a connection diagram that the video processing device 20 realizes that the output video signal and the Genlock signal are always synchronized. The video processing devices 1, 2, and 3 are, for example, the video processing device 20. After receiving the externally input Genlock signal, the video processing device 1 outputs the Genlock signal to the video processing device 2 and the video processing device 2 receives and then outputs the Genlock signal to the video processing device 3, so that the video processing devices 1, 2, and 3 can be in the same Genlock. The purpose of the signal is to achieve the purpose of always synchronizing with the Genlock signal through the special structure of the video processing device 20 through the special structure of the video processing device 20, and the final output images are synchronized, as shown in the multiple display screens in FIG. 2B (in FIG. 2B, 3 side-by-side LED display screens), the output images corresponding to the video processing equipments 1, 2 and 3 respectively, for example, there is no tearing between the diagonal lines shown in the figure, that is, the video processing equipments 1, 2, 3 are realized Always synchronized with the Genlock signal. As shown in FIG. 2C, it is a connection diagram for the video processing device 20 to realize that the output video signal and the input video signal are always synchronized. Among them, the video processing devices 1, 2, and 3 are also the video processing device 20 and the video processing device 1, respectively. After receiving the input video signal from the external input, the input video signal is output to the video processing equipments 1, 2, and 3 respectively, so that the video processing equipments 1, 2, and 3 can pass the video processing by the same input video signal. The special structure of the device 20 is used to achieve the purpose of always being synchronized with the input video signal. The final output image is synchronized. As shown in the display screen in FIG. There is no tearing between the oblique lines shown in the figure, that is, the synchronization between the video processing devices 1, 2, and 3 and the input video signal is always achieved.

As shown in FIG. 3A, a video frame synchronization method 30 according to another embodiment of the present application is provided. The video frame synchronization method 30 is executed, for example, in the video frame synchronization system 10 of the foregoing embodiment or the video processing device 20 of the foregoing another embodiment. For specific structures and functions of the video frame synchronization system 10 and the video processing device 20, refer to the foregoing embodiments. The description is not repeated here. The flow of the video frame synchronization method 30 is briefly described below. Video frame synchronization method 30 mainly includes:

Step S31: acquiring a reference field synchronization signal and detecting a frame frequency of the reference field synchronization signal. Specifically, step S31 is implemented by, for example, the synchronization signal detection comparator 11 of the video frame synchronization system 10 or the synchronization signal detection comparison unit 211 in the programmable logic device 21 of the video processing device 20.

Specifically, the step of obtaining a reference field synchronization signal in step S31 includes: receiving an input video signal and / or a genlock signal; obtaining at least one field synchronization signal based on the input video signal and / or the genlock signal; and The at least one field synchronization signal selects one field synchronization signal as the reference field synchronization signal.

Step S33: calculating the frequency of the pixel clock signal according to the output resolution and the frame rate, generating a clock configuration parameter according to the frequency of the pixel clock signal, and generating a video timing configuration parameter according to the output resolution. Specifically, step S33 is implemented by, for example, the controller 13 of the video frame synchronization system 10 or the controller 23 of the video processing device 20.

Step S35: Generate a pixel clock signal according to the clock configuration parameter. Specifically, step S35 is implemented by, for example, the programmable clock generator 15 of the video frame synchronization system 10 or the programmable clock generator 25 of the video processing device 20.

Step S36: Generate a target field synchronization signal under the driving of the pixel clock signal according to the video timing configuration parameters. Specifically, step S36 is implemented by, for example, the video timing generator 17 of the video frame synchronization system 10 or the timing generation unit 213 in the programmable logic device 21 of the video processing device 20. It is worth mentioning here that, in actual application, the timing generating unit 213 in the video timing generator 17 of the video frame synchronization system 10 or the programmable logic device 21 of the video processing device 20 is based on the video timing configuration parameters in the It is not only the target field synchronization signal that is generated by the pixel clock signal, but it actually generates the pixel clock signal, the target field synchronization signal, the line synchronization signal (HS), and the effective display data. (DE) video timing signals. The video timing signals are output to the video encoder 19 of the video frame synchronization system 10 or the video encoder 27 of the video processing device 20 together.

Step S37: Compare the reference field synchronization signal and the target field synchronization signal to obtain a comparison result, and obtain a frequency adjustment amount of the pixel clock signal according to the comparison result. Specifically, step S37 is implemented by, for example, the synchronization signal detection comparator 11 of the video frame synchronization system 10 or the synchronization signal detection comparison unit 211 in the programmable logic device 21 of the video processing device 20.

The calculation formula of the frequency of the pixel clock signal is FPCLK = FVS (ref) * Htotal * Vtotal, where FPCLK is the frequency of the pixel clock, FVS (ref) is the frame frequency of the reference field synchronization signal, Htotal Is the clock period of the horizontal synchronization signal, and Vtotal is the clock period of the reference field synchronization signal. Specifically, a schematic diagram of the relationship between Vtotal and Htotal and the reference field synchronization signal, the target field synchronization signal, and the line synchronization signal is shown in FIG. 3B.

The step of comparing the reference field synchronization signal and the target field synchronization signal in step S37 to obtain a comparison result includes: comparing a phase of the reference field synchronization signal with a phase of the target field synchronization signal to obtain a relative phase relationship. Comparing the frequency of the reference field synchronization signal with the frequency of the target field synchronization signal to obtain a relative frequency relationship. Specifically, the phase relationship of the target field synchronization signal with respect to the reference field synchronization signal includes, for example, two cases of leading as shown in FIG. 4A and lagging as shown in FIG. 4B; The frequency relationship of the signal includes two cases of lead shown in FIG. 5A and lag shown in FIG. 5B. Specifically, to obtain the frequency adjustment amount of the pixel clock signal according to the comparison result, reference may be made to the feedback adjustment strategy shown in Table 1.

Table 1 Feedback regulation strategies

As for the sizes of h1 and h2 in Table 1, you can set appropriate values as required. For example, the sizes of h1 and h2 may be adjusted according to how much the phase of the target field synchronization signal leads or lags the phase of the reference field synchronization signal.

Step S38: Update the pixel clock signal according to the frequency and the frequency adjustment amount of the pixel clock signal. Specifically, step S38 is implemented by, for example, the controller 13 and the programmable clock generator 15 of the video frame synchronization system 10 or the controller 23 and the programmable clock generator 25 of the video processing device 20. as well as

Step S39: Update the target field synchronization signal under the driving of the updated pixel clock signal according to the video timing configuration parameters. Specifically, step S39 is implemented by, for example, the video timing generator 17 of the video frame synchronization system 10 or the timing generation unit 213 in the programmable logic device 21 of the video processing device 20.

In summary, the foregoing embodiment of the present application achieves the technical effect of ensuring that the target field synchronization signal output by the video timing generator 17 or the timing generation unit 213 is always synchronized with the reference field synchronization signal by fine-tuning the target field synchronization signal. A reliable and compatible video frame synchronization solution.

It is worth mentioning here that the video frame synchronization system 10, the video processing device 20, and the video frame synchronization method 30 of the foregoing embodiments of the present application can all be adapted to the studio and video splicing output scenarios.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and / or method may be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the unit / module is only a logical function division. In actual implementation, there may be another division manner. For example, multiple units or modules may The combination can either be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.

The units / modules described as separate components may or may not be physically separated, and the components displayed as units / modules may or may not be physical units, may be located in one place, or may be distributed to multiple channels. Network unit. Some or all of the units / modules may be selected according to actual needs to achieve the solution objective of this embodiment.

In addition, each functional unit / module in each embodiment of the present application may be integrated into one processing unit / module, or each unit / module may exist separately physically, or two or more units / modules may be integrated into one Unit / module. The above-mentioned integrated units / modules can be implemented in the form of hardware, or in the form of hardware plus software functional units / modules.

The integrated unit / module implemented in the form of a software functional unit / module may be stored in a computer-readable storage medium. The above software functional unit is stored in a storage medium and includes several instructions for causing one or more processors of a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments of the present application. Part of the steps. The foregoing storage media include: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc. The medium.

The above embodiments are only used to describe the technical solution of the present application, but not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still apply the foregoing embodiments. The recorded technical solutions are modified, or some technical features are equivalently replaced; and these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

A video frame synchronization system includes:

The synchronization signal detection comparator includes a reference field synchronization signal input terminal, a feedback field synchronization signal input terminal, and a detection comparison result output terminal;

A controller connected to the detection and comparison result output terminal of the synchronization signal detection comparator;

A programmable clock generator connected to the controller;

The video timing generator includes a video timing configuration parameter input terminal, a pixel clock signal input terminal, and a video timing signal output terminal. The video timing configuration parameter input terminal is connected to the controller, and the pixel clock signal input terminal is connected to the controller. A programmable clock generator, wherein the video timing signal output terminal is connected to the feedback field synchronization signal input terminal of the synchronization signal detection comparator; and

A video encoder is connected to the video timing signal output terminal of the video timing generator.
The video frame synchronization system according to claim 1, wherein the synchronization signal detection comparator further comprises:

A phase comparison unit, configured to compare a phase of a feedback field synchronization signal input from the feedback field synchronization signal input terminal and a reference field synchronization signal input from the reference field synchronization signal input terminal;

A frequency comparison unit, configured to compare frequencies of the feedback field synchronization signal and the reference field synchronization signal;

A comparison result generating unit is configured to generate a frequency adjustment amount of a pixel clock signal according to a comparison result of the phase comparison unit and the frequency comparison unit.
The video frame synchronization system according to claim 1, wherein the video timing signal output terminal comprises: a target field synchronization signal output terminal, a line synchronization signal output terminal, an effective display data strobe signal output terminal, and a pixel clock signal output terminal. The target field synchronization signal output terminal is connected to the feedback field synchronization signal input terminal of the synchronization signal detection comparator; the video encoder is connected to the target field synchronization signal output terminal, the line synchronization signal output terminal, The effective display data strobe signal output terminal and the pixel clock signal output terminal.
The video frame synchronization system according to claim 1, wherein the video frame synchronization system further comprises a video processor, and an output end of the video processor is connected to the video data input end of the video encoder.
A video processing device includes:

Programmable logic device, including reference field synchronization signal source input detection and comparison result output terminal, video timing configuration parameter input terminal, pixel clock signal input terminal, video timing signal output terminal and video data output terminal;

A controller connected to the detection and comparison result output terminal of the programmable logic device and the video timing configuration parameter input terminal;

A programmable clock generator connected between the controller and the pixel clock signal input terminal of the programmable logic device; and

A video encoder connected to the video timing signal output terminal and the video data output terminal of the programmable logic device;

Wherein, the programmable logic device is configured to obtain a reference field synchronization signal according to a signal input from a source input terminal of the reference field synchronization signal, detect a frame rate of the reference field synchronization signal, and output the result through the detection and comparison output terminal. The frame frequency and the video timing configuration parameter input from the video timing configuration parameter input end are driven by the pixel clock signal input from the pixel clock signal input end to generate a target field synchronization signal, and the video timing signal output end Outputting the target field synchronization signal, comparing the reference field synchronization signal and the target field synchronization signal, obtaining a frequency adjustment amount of the pixel clock signal according to a result of the comparison, and outputting The frequency adjustment amount to the controller so that the controller controls the programmable clock generator to update the pixel clock signal according to the frequency adjustment amount, and updates the target according to the updated pixel clock signal Field sync signal.
The video processing device according to claim 5, wherein the reference field synchronization signal source input terminal comprises a plurality of video signal input terminals and a genlock signal input terminal.
The video processing device according to claim 5, wherein the programmable logic device is further configured to process video data to obtain processed video data and output the processed video data through the video data output terminal.
A video frame synchronization method includes:

Acquiring a reference field synchronization signal and detecting a frame rate of the reference field synchronization signal;

Calculating the frequency of the pixel clock signal according to the output resolution and the frame rate, generating a clock configuration parameter according to the frequency of the pixel clock signal, and generating a video timing configuration parameter according to the output resolution;

Generating a pixel clock signal according to the clock configuration parameter;

Generating a target field synchronization signal under the driving of the pixel clock signal according to the video timing configuration parameter;

Comparing the reference field synchronization signal with the target field synchronization signal to obtain a comparison result, and obtaining a frequency adjustment amount of the pixel clock signal according to the comparison result;

Updating the pixel clock signal according to the frequency and the frequency adjustment amount of the pixel clock signal; and

Updating the target field synchronization signal under the driving of the updated pixel clock signal according to the video timing configuration parameter.
The video frame synchronization method according to claim 8, wherein the step of comparing the reference field synchronization signal and the target field synchronization signal to obtain a comparison result comprises:

Comparing the phase of the reference field synchronization signal with the phase of the target field synchronization signal to obtain a relative phase relationship;

Comparing the frequency of the reference field synchronization signal with the frequency of the target field synchronization signal to obtain a relative frequency relationship;

The phase relative relationship and the frequency relative relationship are used as the comparison result.
The video frame synchronization method according to claim 8, wherein the step of obtaining a reference field synchronization signal comprises:

Receiving input video signals and / or genlock signals;

Obtaining at least one field synchronization signal based on the input video signal and / or the genlock signal;

Selecting a field sync signal from the at least one field sync signal as the reference field sync signal.