CN114710700A - Data display method, device and equipment - Google Patents
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- 230000001360 synchronised effect Effects 0.000 claims abstract description 13
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4307—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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Abstract
The invention discloses a data display method, a data display device and data display equipment. Wherein, the method comprises the following steps: a first video daughter card in the card-inserting type equipment receives a reference signal generated by a second video daughter card in the card-inserting type equipment; the first video daughter card adjusts a local clock based on the reference signal; the first video daughter card generates a video time sequence signal based on the adjusted local clock and the reference signal; the first video daughter card outputs video data based on the timing signals. The invention solves the technical problem that the time sequence of the output interface of the card-inserting type video processing equipment can not be synchronized in a free state because an external reference source is required to be introduced in the prior art.
Description
Technical Field
The invention relates to the technical field of video processing, in particular to a data display method, a data display device and data display equipment.
Background
In the card-inserting type equipment, when the output interfaces of the sub-cards are spliced and displayed, because the output clocks of the sub-cards are different in source, the output images among the sub-cards are asynchronous, and the final spliced display images are incomplete, therefore, the output interfaces are required to be synchronously processed.
In the prior art, as shown in fig. 1, an input source is respectively sent to a daughter card a and a daughter card B, and a video frame synchronization signal of the input source is acquired in the daughter card a and the daughter card B as a synchronization reference signal. Meanwhile, in the daughter card a and the daughter card B, the timing signals when the interface outputs the video are generated by the output interface video display clock generated by the clock chip, wherein the timing signals include output synchronization signals. Then each sub-card can respectively obtain the phase relation between the synchronous reference signal and the frame synchronization signal when the interface outputs the video, and the phase relation is sent to the clock adjusting module, the frequency of the local output interface video display clock is calculated through a clock adjusting algorithm, the clock frequency is adjusted in real time, the phase relation between the frame synchronization signal and the synchronous reference signal when the interface outputs the video is locked in a certain range, and therefore the output synchronization of each sub-card interface is achieved.
However, the prior art must introduce a video source as a synchronization reference signal, and cannot realize synchronization in the free run state. In addition, in the prior art, the frame rate of the output interface must be consistent with the frame rate of the reference source, and synchronization cannot be realized when the frame rates are inconsistent.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the invention provides a data display method, a data display device and data display equipment, which at least solve the technical problem that in the prior art, a card-type video processing device cannot enable the time sequence of an output interface to be synchronized in a free state due to the fact that an external reference source must be introduced.
According to an aspect of an embodiment of the present invention, there is provided a data display method including: a first video daughter card in the card-inserting type equipment receives a reference signal generated by a second video daughter card in the card-inserting type equipment; the first video daughter card adjusts a local clock based on the reference signal; the first video daughter card generates a video time sequence signal based on the adjusted local clock and the reference signal; the first video daughter card outputs video data based on the timing signals. By adopting the data display method, the reference signals are provided for all the video sub-cards in the card-inserting type equipment through one video sub-card in the card-inserting type equipment, so that the card-inserting type equipment can still keep the output video synchronization under the free state of a plurality of output interface book orders.
Optionally, the reference signal includes a reference time tick signal, and the reference time tick signal is generated by a clock crystal oscillator in the second video daughter card, where the first video daughter card adjusts the local clock based on the reference signal, including: the first video daughter card generates a local time tick signal, wherein the frequency of the local time tick signal is the same as that of the reference time tick signal; comparing the phase relationship between the local time tick signals and the received reference time tick signals by a Field Programmable Gate Array (FPGA) in the first video daughter card, and feeding back the phase relationship to a Micro Control Unit (MCU) in the first video daughter card; and the MCU in the first video sub-card adjusts the local clock frequency of the first video sub-card through the clock chip in the first video sub-card based on the phase relation, wherein the local clock is generated by the clock chip.
Optionally, the phase relationship between the local time tick signal and the reference time tick signal comprises at least one of: the phase of the local time tick signal is ahead of the phase of the reference time tick signal and the phase of the local time tick signal lags behind the phase of the reference time tick signal; wherein, MCU in the first video daughter card includes through the clock chip in the first video daughter card that the local clock frequency of adjusting the first video daughter card based on phase relation: reducing the frequency of the local clock when the phase of the local time tick is ahead of the phase of the reference time tick; the frequency of the local clock is increased when the phase of the local time tick is lagging behind the phase of the reference time tick. By the scheme, the frequency difference between the local clocks of any two video daughter cards in the card-inserting equipment is smaller than the preset threshold value, so that the local clocks of any two video daughter cards in the card-inserting equipment can be regarded as the same source clock.
Optionally, the phase relationship further comprises phase difference information between the local time pair signal and the reference time pair signal, wherein the phase difference information is used to determine a frequency adjustment magnitude of the local clock.
Optionally, the number of the first video daughter cards in the card-inserted device is one or more, and the number of the second video daughter cards is one, where a frequency difference value between the adjusted local clock of the first video daughter card and the local clock of the second video daughter card is smaller than a preset frequency difference threshold.
Optionally, the reference signal includes a synchronization update signal, and the generating, by the first video daughter card, the timing signal based on the adjusted local clock and the reference signal includes: the first video daughter card generates a timing signal at a preset frequency through a local clock at the rising edge of the synchronous updating signal, wherein the timing signal is a timing signal of the video output interface, and the timing signal comprises a frame synchronization signal.
According to another aspect of the embodiments of the present invention, there is also provided a data display method, including: generating a reference signal by a second video daughter card in the card-inserting type equipment; the second video daughter card adjusts a local clock based on the reference signal; the second video daughter card generates a timing signal based on the adjusted local clock and the reference signal; the second video daughter card outputs video data based on the timing signals.
According to another aspect of the embodiments of the present invention, there is also provided a data display device including one or more first video sub-cards, and a second video sub-card, wherein the second video sub-card is configured to generate and transmit a reference signal to the first video sub-card, and the first video sub-card adjusts a local clock based on the received reference signal.
According to another aspect of the embodiments of the present invention, there is also provided a data display device, including a clock chip, a processor, and a video output interface, wherein: the processor is used for sending a control instruction to the clock chip, wherein the control instruction is used for controlling the clock chip to generate a reference signal; the clock chip is used for receiving the control instruction sent by the processor, generating a reference signal according to the control instruction and generating a time sequence signal of the video output interface; and the video output interface is used for outputting videos according to the time sequence signals of the video output interface.
According to another aspect of the embodiments of the present invention, there is further provided a data display device, including a master video daughter card and a plurality of slave video daughter cards, wherein: the master video daughter card is used for generating and sending reference signals to the plurality of slave video daughter cards and outputting videos according to the reference signals; and the plurality of slave video daughter cards are used for outputting videos according to the reference signals.
According to another aspect of the embodiments of the present invention, there is also provided a video daughter card, suitable for use in a data display device, including a micro control unit MCU, a field programmable gate array FPGA, a clock chip and a video output interface, where the clock chip is configured to generate a local clock under the control of the MCU, generate a local clock-tick based on the local clock, and generate and send a timing signal of the video output interface to the video output interface based on the local clock; the FPGA is used for receiving reference signals sent by other video daughter cards in the data display equipment, determining the phase relationship between the reference time tick signals and the local time tick signals in the reference signals, and sending the phase relationship to the MCU; the MCU is used for receiving the phase relation sent by the FPGA and adjusting the frequency of the local clock through the clock chip based on the phase relation; and the video output interface is used for receiving the time sequence signal of the video output interface and outputting the video data based on the time sequence signal.
According to another aspect of the embodiments of the present invention, there is also provided a video daughter card, including a micro control unit MCU, a field programmable gate array FPGA, a clock chip, a clock crystal oscillator, and a video output interface, where the clock chip is configured to generate a local clock under the control of the MCU, generate a local clock-tick signal based on the local clock, and generate and send a timing signal of the video output interface to the video output interface based on the local clock; the clock crystal oscillator is used for generating a reference signal; the FPGA is used for determining the phase relation between a reference time tick signal and a local time tick signal in the reference signal and sending the phase relation to the MCU; the MCU is used for receiving the phase relation sent by the FPGA and adjusting the frequency of the local clock through the clock chip based on the phase relation; and the video output interface is used for receiving the time sequence signal of the video output interface and outputting the video data based on the time sequence signal.
According to another aspect of the embodiments of the present invention, there is provided a data display device, suitable for use in a video daughter card, including: the receiving module is used for receiving a reference signal generated by a second video daughter card in the card-inserting type equipment; a first processing module for adjusting a local clock based on the reference signal; a second processing module for generating a timing signal based on the adjusted local clock and the reference signal; and the output module is used for outputting the video data based on the time sequence signal.
According to another aspect of the embodiments of the present invention, there is also provided a nonvolatile storage medium including a stored program, wherein a device in which the nonvolatile storage medium is controlled to perform a data display method when the program is executed.
According to another aspect of the embodiments of the present invention, there is also provided a processor configured to execute a program, where the program executes a data display method.
In the embodiment of the invention, a first video daughter card in the card-inserting type equipment is adopted to receive a reference signal generated by a second video daughter card in the card-inserting type equipment; the first video daughter card adjusts a local clock based on the reference signal; the first video daughter card generates a timing signal based on the adjusted local clock and the reference signal; the first video sub-card outputs video data based on the time sequence signal, and provides reference signals for other video sub-cards through the video sub-card in the card-inserting type device, so that the purpose of synchronizing output pictures of the sub-cards is achieved under the condition that no external reference source exists, the technical effect that the time sequence of an output interface of the card-inserting type video processing device is in a free state is achieved, and the technical problem that the time sequence of the output interface of the card-inserting type video processing device cannot be synchronized in the free state due to the fact that an external reference source must be introduced in the prior art is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of a video synchronization method according to the prior art;
FIG. 2 is a schematic diagram of a data display method according to an embodiment of the invention;
FIG. 3 is a schematic flow chart of a method for synchronously outputting videos by multiple video daughter cards according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a data display device according to an embodiment of the present invention;
FIG. 5a is a schematic diagram of a video daughter card in accordance with an embodiment of the present invention;
FIG. 5b is a schematic diagram of another video daughter card in accordance with an embodiment of the present invention;
FIG. 6 is a schematic diagram of a video display apparatus according to an embodiment of the present invention;
fig. 7 is a schematic diagram of another video synchronization method according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Where a method embodiment of a method of displaying data is provided according to an embodiment of the present invention, it is noted that the steps illustrated in the flowchart of the figure may be performed in a computer system such as a set of computer-executable instructions, and that while a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order different than presented herein.
Fig. 2 is a data display method according to an embodiment of the present invention, as shown in fig. 2, which is applied to a daughter card for providing a reference signal in a card-inserted device, and includes the following steps:
step S202, a first video sub-card in the card-inserting type equipment receives a reference signal generated by a second video sub-card in the card-inserting type equipment;
in some embodiments of the present application, the reference signal in the second video daughter card is generated by a clock crystal in the second video daughter card. Specifically, the clock crystal in the second video daughter card generates a local clock, and then generates a reference signal by the local clock, so as to provide a reference for adjusting the local time tick signal for the first video daughter card and the second video daughter card.
In some embodiments of the present application, the second video daughter card and the first video daughter card are connected by a connection line, and the second video daughter card transmits the reference signal to each of the second video daughter cards through the connection line.
In some embodiments of the present application, the reference signals generated by the second video daughter card based on the local clock include a reference time tick signal and a synchronization update signal. The reference time-tick signal is used for providing a reference for adjusting a local clock for the first video daughter card, and the synchronous updating signal is a timing signal for enabling the first video daughter card and the second video daughter card to start generating the video output interface at the same time point.
In some embodiments of the present application, the local time tick signals are generated in both the first video daughter card and the second video daughter card according to the same rule. Since the same generation rules are followed when generating local time ticks in different video daughter cards, the difference between local time ticks in different video daughter cards may reflect the difference of local clocks in different video daughter cards. Thus, when the first video daughter card receives the reference time tick signal, the first video daughter card may adjust the frequency of the local clock based on the difference between the reference time tick signal and the local time tick signal. In addition, the second video daughter card will also adjust the local clock frequency generated by its clock chip based on its own generated reference signal. Because the phase difference of the local time tick signals in the adjusted first video daughter card and the second video daughter card is within the preset value range relative to the reference signal, the phase difference of the local time tick signals in the adjusted first video daughter card and the adjusted second video daughter card can be considered to be the same, so that the local clock of the first video daughter card and the local clock of the second video daughter card can be considered as the same source clock, that is, the frequencies of the local clocks of the first video daughter card and the second video daughter card are approximately the same.
In some embodiments of the present application, the local time tick or the reference time tick is generated by different video daughter cards at the same frequency.
Step S204, the first video daughter card adjusts a local clock based on the reference signal;
in some embodiments of the present application, the reference signal may include a reference time-tick signal generated by a clock crystal in the second video daughter card, where the adjusting the local clock by the first video daughter card based on the reference signal includes:
a first video daughter card generates a local time tick signal, wherein the frequency of the local time tick signal is the same as that of the reference time tick signal; comparing a phase relation between a local time tick signal and the received reference time tick signal by a Field Programmable Gate Array (FPGA) in the first video daughter card, and feeding back the phase relation to a Micro Control Unit (MCU) in the first video daughter card; and the MCU in the first video sub-card adjusts the local clock frequency of the first video sub-card through the clock chip in the first video sub-card based on the phase relation, wherein the local clock is generated by the clock chip.
In some embodiments of the present application, the reference time tick signal generated in the second video daughter card is transmitted to the FPGA in the first video daughter card through the hardware pin cascade.
In some embodiments of the present application, the local time tick signals generated by different video daughter cards have the same frequency, but the phases of the different local time tick signals may differ due to the different local clock frequencies in the different video daughter cards prior to synchronization.
In some embodiments of the present application, the phase relationship between the local time tick signal and the reference time tick signal comprises at least one of: the phase of the local time tick signal leads the phase of the reference time tick signal and lags the phase of the reference time tick signal; based on the phase relationship, the MCU in the first video daughter card adjusts the local clock frequency of the first video daughter card through the clock chip in the first video daughter card, including the following conditions: reducing the frequency of the local clock when the phase of the local time tick is ahead of the phase of the reference time tick; and increasing the frequency of the local clock when the phase of the local time tick signal lags the phase of the reference time tick signal.
In some embodiments of the present application, the phase relationship further comprises phase difference information between the local time pair signal and the reference time pair signal, wherein the phase difference information is used to determine a frequency adjustment magnitude of the local clock.
In particular, the phase difference information may comprise the magnitude of the phase difference between the local time tick signal and the reference time tick signal.
In some embodiments of the present application, the number of the first video daughter cards in the card-inserted device is one or more, and the number of the second video daughter cards is one, where a frequency difference value between the adjusted local clocks of any two video daughter cards is smaller than a preset frequency difference threshold.
In some embodiments of the present application, the difference between the frequency of the local clock in the first video daughter card and the frequency of the local clock in the second video daughter card may be represented by a phase difference of the local time tick signals, specifically, the phase difference between the local time tick signal and the reference time tick signal is larger when the frequency difference between the respective local clocks of the first video daughter card and the second video daughter card is larger. The frequency difference between the local clocks can therefore be determined by the phase difference between the local time tick signal and the reference time tick signal. Specifically, after the local clock frequencies in the first video daughter card and the second video daughter card are adjusted, when the phase difference between the local time tick signal and the reference time tick signal is smaller than the preset phase difference threshold, it is determined that the frequency difference of the local clock between the first video daughter card and the second video daughter card is not greater than the preset frequency difference threshold, that is, the local clocks of the first video daughter card and the second video daughter card may be approximately regarded as the same source clock.
Step S206, the first video daughter card generates a timing signal based on the adjusted local clock and the reference signal;
in step S208, the first video daughter card outputs video data based on the timing signal.
In some embodiments of the present application, the reference signal includes a synchronization update signal, and the specific process of the first video daughter card generating the timing signal of the video output interface based on the adjusted local clock and the reference signal includes: and the first video daughter card generates a timing signal of the video output interface by a local clock at a preset frequency at the beginning of the rising edge of the synchronous updating signal, wherein the timing signal of the video output interface comprises a frame synchronization signal.
In some embodiments of the present application, the timing signals of the video output interface further include a line synchronization signal and a valid data enable signal.
Fig. 7 shows another data display method according to an embodiment of the present invention, as shown in fig. 7, the method is applied to the second video daughter card, and includes the following steps:
step S702, a second video daughter card in the card-inserting type equipment generates a reference signal;
step S704, the second video daughter card adjusts a local clock based on the reference signal;
step S706, the second video daughter card generates a timing signal based on the adjusted local clock and the reference signal;
in step S708, the second video daughter card outputs video data based on the timing signal.
Fig. 3 is a schematic flowchart of a process when multiple video daughter cards synchronously output video according to an embodiment of the present application, and as shown in fig. 3, taking two output daughter cards of a card-inserted device as an example, a clock crystal oscillator in the daughter card a generates a reference signal, and the reference signal is transmitted to the daughter card B in a cascade manner. The reference signal includes a SyncUpdate signal (synchronization update signal) and a reference time-tick signal. Assuming that the reference signal is a 10Hz periodic signal having a period of 100ms, when the low level width is 1us, the SyncUpdate signal is represented, and Timing of output (Timing signal of output video from the output interface) starts to be generated at the edge of the signal as the start point of synchronization. The other low level width is 0.5us, which represents the reference time tick signal as the reference for synchronization.
The reference signal is transmitted to each daughter card through hardware pins in cascade. And analyzing the reference signal in each daughter card to obtain a SyncUpdate signal and a reference time tick signal. The reference time tick signal is a pulse signal with a fixed period (such as a 10Hz periodic signal). The DispClk (interface output clock) of each daughter card is dynamically configured by an external clock chip. In each daughter card, the local time tick signal is generated by frequency division with the DispClk clock, and the frequency of the local time tick signal is consistent with that of the reference time tick signal (the periodic signal is also 10 Hz). And then, acquiring the phase relation between the local time tick signal and the reference time tick signal, and feeding back the phase relation to the MCU. In the MCU, the frequency of the DispClk is calculated based on the phase relation fed back in real time through a clock regulation algorithm, and a clock chip is dynamically configured according to the calculation result, so that the phase relation between the local time synchronization signal and the reference time synchronization signal is locked in a certain range. When the local time tick signals of the daughter card a and the daughter card B are both phase-locked with the reference time tick signal, the DispClk of the daughter card a and the daughter card B is considered to be approximately homologous.
And finally, in the daughter card A and the daughter card B, the MCU of each daughter card generates output Timing based on DispClk, and resets the output Timing at the edge of a SyncUpdate signal to be used as the starting point of the output Timing. In addition, since the Dispclk of the daughter card A and the Dispclk of the daughter card B are similar to the same source, and the output Timing takes the same time as the starting point, the output Timing of the daughter card A and the output Timing of the daughter card B are synchronized, so that the frame synchronization of the interfaces of the output daughter cards is realized.
In this embodiment, through the above steps, the local clocks of different video daughter cards can be regarded as approximately the same source clock, and the different video daughter cards follow the same generation rule when generating the video output interfaces, so the frequencies of the timing signals generating the video output interfaces in the different video daughter cards can be regarded as the same. In addition, different video daughter cards all start to generate timing signals of the video output interfaces at the rising edge of the synchronous updating signal, that is, different video daughter cards start to generate timing signals of the video output interfaces at the same time point. Therefore, the frequency and the starting time of the time sequence signals of the video output interfaces generated by different video sub-cards are the same, so that the videos output by different video sub-cards are kept synchronous.
Example 2
According to an embodiment of the present invention, there is provided an embodiment of a data display apparatus. As shown in fig. 4, the data display device includes a master video daughter card (i.e., a second video daughter card) 402, one or more slave video daughter cards (i.e., first video daughter cards) 404, wherein: the one or more slave video daughter cards 404 are connected to the master video daughter card 402, the master video daughter card 402 is configured to generate and send a reference signal to the slave video daughter card 404, and the slave video daughter card 404 is configured to adjust a local clock according to the reference signal.
In some embodiments of the present application, the interaction flow between the daughter cards of the data display apparatus shown in fig. 4 during its operation is shown in fig. 3. Specifically, fig. 3 is a schematic flow chart of a multi-video daughter card for synchronously outputting videos according to an embodiment of the present application, and as shown in fig. 3, taking two output daughter cards of a card-inserted device as an example, a clock crystal oscillator is used in a daughter card a to generate a reference signal, and the reference signal is transmitted to a daughter card B in a cascade manner. The reference signal includes a SyncUpdate signal (synchronization update signal) and a reference time-tick signal. Assuming that the reference signal is a 10Hz periodic signal having a period of 100ms, when the low level width is 1us, the SyncUpdate signal is represented, and Timing of output (Timing signal of output video from the output interface) starts to be generated at the edge of the signal as the start point of synchronization. The other low level width is 0.5us, which represents the reference time tick signal as the reference for synchronization.
The reference signal is then transmitted in cascade through the hardware pins to the individual daughter cards. And analyzing the reference signal in each daughter card to obtain a SyncUpdate signal and a reference time tick signal. The reference time tick signal is a pulse signal with a fixed period (such as a 10Hz periodic signal). The DispClk (interface output clock) of each daughter card is dynamically configured by an external clock chip. In each daughter card, the local time tick is generated by frequency division with DispClk clock, and the frequency of the local time tick is consistent with the frequency of the reference time tick (also 10Hz periodic signal). And then, acquiring the phase relationship between the local time tick signal and the reference time tick signal, and feeding back the phase relationship to the MCU. In the MCU, the frequency of the DispClk is calculated based on the phase relation fed back in real time through a clock regulation algorithm, and a clock chip is dynamically configured according to the calculation result, so that the phase relation between the local time synchronization signal and the reference time synchronization signal is locked in a certain range. When the local time tick signals of the daughter card a and the daughter card B are both phase-locked with the reference time tick signal, the DispClk of the daughter card a and the daughter card B is considered to be approximately homologous.
And finally, in the daughter card A and the daughter card B, the MCU of each daughter card generates output Timing based on DispClk, and resets the output Timing at the edge of a SyncUpdate signal to be used as the starting point of the output Timing. In addition, since the Dispclk of the daughter card A and the Dispclk of the daughter card B are similar to the same source, and the output Timing takes the same time as the starting point, the output Timing of the daughter card A and the output Timing of the daughter card B are synchronized, so that the frame synchronization of the interfaces of the output daughter cards is realized.
It should be noted that the data display device provided in the embodiment of the present application can be used to execute the image processing method shown in fig. 2 in embodiment 1, and therefore, the relevant expressions in embodiment 1 are also applicable to the embodiment of the present application, and are not described herein again.
Example 3
According to an embodiment of the present invention, an embodiment of a video daughter card is provided. Fig. 5a is a video daughter card according to an embodiment of the present invention, as shown in fig. 5a, the video daughter card includes: the system comprises a micro control unit MCU502, a field programmable gate array FPGA504, a clock chip 506 and a video output interface 508, wherein the clock chip 506 is used for generating a local clock under the control of the MCU502, generating a local time tick signal based on the local clock, and generating and sending a time sequence signal of the video output interface to the video output interface 508 based on the local clock; the FPGA504 is configured to receive reference signals sent by other video daughter cards in the data display device, determine a phase relationship between a reference time tick signal and a local time tick signal in the reference signals, and send the phase relationship to the MCU 502; the MCU502 is used for receiving the phase relation sent by the FPGA504 and adjusting the frequency of a local clock through the clock chip 506 based on the phase relation; the video output interface 508 is used for receiving the timing signal of the video output interface and outputting the video data based on the timing signal.
According to an embodiment of the present invention, an embodiment of a video daughter card is provided. Fig. 5b is another video daughter card according to an embodiment of the present invention, as shown in fig. 5b, the video daughter card comprising: the device comprises a micro control unit MCU510, a field programmable gate array FPGA512, a clock chip 514, a clock crystal oscillator 516 and a video output interface 518, wherein the clock chip 514 is used for generating a local clock under the control of the MCU510, generating a local time-tick signal based on the local clock, and generating a time-tick signal based on the local clock and sending a time-tick signal of the video output interface to the video output interface 518; a clock oscillator 516 for generating a reference signal; the FPGA512 is configured to determine a phase relationship between a reference time tick signal and a local time tick signal in the reference signal, and send the phase relationship to the MCU 510; the MCU510 is used for receiving the phase relation sent by the FPGA512 and adjusting the frequency of the local clock through the clock chip 514 based on the phase relation; the video output interface 518 is used for receiving the timing signal of the video output interface and outputting the video data based on the timing signal.
It should be noted that the data display device provided in the embodiment of the present application can be used to execute the image processing method described in embodiment 1, and therefore, the relevant description in embodiment 1 is also applicable to the embodiment of the present application, and is not repeated herein.
Example 4
According to an embodiment of the present invention, there is provided an embodiment of a data display apparatus. The data display device is suitable for a video daughter card, and as shown in fig. 6, the data display device includes a receiving module 60, configured to receive a reference signal generated by a second video daughter card in a card-inserted device; a first processing module 62 for adjusting the local clock based on the reference signal; a second processing module 64 for generating timing signals based on the adjusted local clock and the reference signal; and an output module 66 for outputting the video data based on the timing signal.
Example 5
According to an embodiment of the present invention, there is provided a nonvolatile storage medium including a stored program, wherein, when the program is executed, a device in which the nonvolatile storage medium is located is controlled to execute the following data display method: a first video daughter card in the card-inserting type equipment receives a reference signal generated by a second video daughter card in the card-inserting type equipment; the first video daughter card adjusts a local clock based on the reference signal; the first video daughter card generates a video time sequence signal based on the adjusted local clock and the reference signal; the first video daughter card outputs video data based on the timing signals.
According to an embodiment of the present invention, there is provided a processor, configured to execute a program, where the program executes the following data display method: a first video daughter card in the card-inserting type equipment receives a reference signal generated by a second video daughter card in the card-inserting type equipment; the first video daughter card adjusts a local clock based on the reference signal; the first video daughter card generates a video time sequence signal based on the adjusted local clock and the reference signal; the first video daughter card outputs video data based on the timing signals.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk, and various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (12)
1. A method of displaying data, comprising:
a first video sub-card in the card-inserting type equipment receives a reference signal generated by a second video sub-card in the card-inserting type equipment;
the first video daughter card adjusts a local clock based on the reference signal;
the first video daughter card generates a timing signal based on the adjusted local clock and the reference signal;
the first video daughter card outputs video data based on the timing signals.
2. The display method of claim 1, wherein the reference signal comprises a reference time tick signal, wherein the first video daughter card adjusting a local clock based on the reference signal comprises:
the first video daughter card generates a local time tick signal, wherein the frequency of the local time tick signal is the same as the frequency of the reference time tick signal;
comparing the phase relationship between the local time tick signals and the received reference time tick signals by a Field Programmable Gate Array (FPGA) in the first video daughter card, and feeding back the phase relationship to a Micro Control Unit (MCU) in the first video daughter card;
and the MCU in the first video sub-card adjusts the local clock frequency of the first video sub-card through a clock chip in the first video sub-card based on the phase relation, wherein the local clock is generated by the clock chip.
3. A display method as claimed in claim 2, in which the phase relationship between the local time tick signal and the reference time tick signal comprises at least one of: the phase of the local time tick signal leads the phase of the reference time tick signal and the phase of the local time tick signal lags the phase of the reference time tick signal; wherein, the MCU in the first video daughter card adjusts the local clock frequency of the first video daughter card through the clock chip in the first video daughter card based on the phase relationship includes:
reducing the frequency of the local clock when the phase of the local time tick is ahead of the phase of the reference time tick;
increasing the frequency of the local clock when the phase of the local time tick signal lags the phase of the reference time tick signal.
4. The display method according to claim 2 wherein the phase relationship further comprises phase difference information between the local time pair signal and the reference time pair signal, wherein the phase difference information is used to determine a frequency adjustment magnitude of the local clock.
5. The display method according to claim 1, wherein the number of the first video daughter cards in the card-inserted device is one or more, the number of the second video daughter cards is one, and a frequency difference value between the adjusted local clock of the first video daughter card and the local clock of the second video daughter card is smaller than a preset frequency difference threshold.
6. The display method according to claim 1, wherein the reference signal comprises a synchronization update signal, and the first video daughter card generates a timing signal based on the adjusted local clock and the reference signal comprises:
and the first video daughter card generates a timing signal by a local clock at a preset frequency at the beginning of the rising edge of the synchronous updating signal, wherein the timing signal is a timing signal of a video output interface, and the timing signal further comprises a frame synchronization signal.
7. A method of displaying data, comprising:
a second video daughter card in the card-inserting type equipment generates a reference signal;
the second video daughter card adjusts a local clock based on the reference signal;
the second video daughter card generates a timing signal based on the adjusted local clock and the reference signal;
the second video daughter card outputs video data based on the timing signal.
8. A data display device comprising one or more first video sub-cards, and a second video sub-card, wherein,
the one or more first video sub-cards are connected with the second video sub-card, the second video sub-card is used for generating and sending a reference signal to the first video sub-card, and the first video sub-card and the second video sub-card adjust a local clock based on the reference signal.
9. A video daughter card is characterized by comprising a micro control unit MCU, a field programmable gate array FPGA, a clock chip and a video output interface, wherein,
the clock chip is used for generating a local clock under the control of the MCU, generating a local time tick signal based on the local clock, and generating and sending a time sequence signal of the video output interface to the video output interface based on the local clock;
the FPGA is used for receiving reference signals sent by other video daughter cards in the data display equipment, determining the phase relationship between the reference time tick signals and the local time tick signals in the reference signals, and sending the phase relationship to the MCU;
the MCU is used for receiving the phase relation sent by the FPGA and adjusting the frequency of the local clock through the clock chip based on the phase relation;
the video output interface is used for receiving a time sequence signal of the video output interface and outputting video data based on the time sequence signal.
10. A video daughter card is characterized by comprising a micro control unit MCU, a field programmable gate array FPGA, a clock chip, a clock crystal oscillator and a video output interface, wherein,
the clock chip is used for generating a local clock under the control of the MCU, generating a local time tick signal based on the local clock, and generating and sending a time sequence signal of the video output interface to the video output interface based on the local clock;
the clock crystal oscillator is used for generating a reference signal;
the FPGA is used for determining the phase relation between a reference time tick signal and a local time tick signal in the reference signal and sending the phase relation to the MCU;
the MCU is used for receiving the phase relation sent by the FPGA and adjusting the frequency of the local clock through the clock chip based on the phase relation;
the video output interface is used for receiving the time sequence signal of the video output interface and outputting video data based on the time sequence signal.
11. A data display device adapted for use in a video daughter card as claimed in claim 9, comprising:
the receiving module is used for receiving a reference signal generated by a second video daughter card in the card-inserting type equipment;
a first processing module for adjusting a local clock based on the reference signal;
a second processing module for generating a timing signal based on the adjusted local clock and the reference signal;
and the output module is used for outputting video data based on the time sequence signal.
12. A non-volatile storage medium, comprising a stored program, wherein when the program runs, a device in which the non-volatile storage medium is located is controlled to execute the data display method according to any one of claims 1 to 6.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101039145A (en) * | 2007-03-30 | 2007-09-19 | 华为技术有限公司 | Method and apparatus for realizing clock |
| CN101166630A (en) * | 2005-04-26 | 2008-04-23 | 株式会社理光 | Pixel clock generator, pulse modulator, and image forming apparatus |
| CN101776985A (en) * | 2009-12-29 | 2010-07-14 | 广东威创视讯科技股份有限公司 | Synchronous display device, and synchronous tiled display system and synchronous display method thereof |
| CN101815177A (en) * | 2010-03-11 | 2010-08-25 | 广东威创视讯科技股份有限公司 | Synchronous displaying device, synchronous displaying method and superposition splice displaying system |
| CN103065610A (en) * | 2013-01-08 | 2013-04-24 | 北京淳中视讯科技有限公司 | Split joint screen synchronous disposal method and split joint screen synchronous disposal device |
| CN104639158A (en) * | 2014-12-30 | 2015-05-20 | 广东大普通信技术有限公司 | Method for regulating synchronous double phase-locked loops |
| CN104980150A (en) * | 2014-04-09 | 2015-10-14 | 许文 | Clock frequency regulation phase locking method based on FPGA |
| CN107784992A (en) * | 2016-08-25 | 2018-03-09 | 晨星半导体股份有限公司 | Display control apparatus and control method |
| CN210327842U (en) * | 2019-11-25 | 2020-04-14 | 无锡思朗电子科技有限公司 | Digital audio and video signal clock synchronization system |
| CN112074896A (en) * | 2018-09-26 | 2020-12-11 | 西安诺瓦星云科技股份有限公司 | Video frame synchronization system, video processing apparatus, and video frame synchronization method |
| CN112422770A (en) * | 2020-11-18 | 2021-02-26 | 厦门视诚科技有限公司 | Synchronization method and system for multiple 4K-resolution video processors |
| CN113037459A (en) * | 2019-12-25 | 2021-06-25 | 西安诺瓦星云科技股份有限公司 | Clock synchronization method and device and video processing equipment |
-
2022
- 2022-03-24 CN CN202210297126.4A patent/CN114710700A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101166630A (en) * | 2005-04-26 | 2008-04-23 | 株式会社理光 | Pixel clock generator, pulse modulator, and image forming apparatus |
| CN101039145A (en) * | 2007-03-30 | 2007-09-19 | 华为技术有限公司 | Method and apparatus for realizing clock |
| CN101776985A (en) * | 2009-12-29 | 2010-07-14 | 广东威创视讯科技股份有限公司 | Synchronous display device, and synchronous tiled display system and synchronous display method thereof |
| CN101815177A (en) * | 2010-03-11 | 2010-08-25 | 广东威创视讯科技股份有限公司 | Synchronous displaying device, synchronous displaying method and superposition splice displaying system |
| CN103065610A (en) * | 2013-01-08 | 2013-04-24 | 北京淳中视讯科技有限公司 | Split joint screen synchronous disposal method and split joint screen synchronous disposal device |
| CN104980150A (en) * | 2014-04-09 | 2015-10-14 | 许文 | Clock frequency regulation phase locking method based on FPGA |
| CN104639158A (en) * | 2014-12-30 | 2015-05-20 | 广东大普通信技术有限公司 | Method for regulating synchronous double phase-locked loops |
| CN107784992A (en) * | 2016-08-25 | 2018-03-09 | 晨星半导体股份有限公司 | Display control apparatus and control method |
| CN112074896A (en) * | 2018-09-26 | 2020-12-11 | 西安诺瓦星云科技股份有限公司 | Video frame synchronization system, video processing apparatus, and video frame synchronization method |
| CN210327842U (en) * | 2019-11-25 | 2020-04-14 | 无锡思朗电子科技有限公司 | Digital audio and video signal clock synchronization system |
| CN113037459A (en) * | 2019-12-25 | 2021-06-25 | 西安诺瓦星云科技股份有限公司 | Clock synchronization method and device and video processing equipment |
| CN112422770A (en) * | 2020-11-18 | 2021-02-26 | 厦门视诚科技有限公司 | Synchronization method and system for multiple 4K-resolution video processors |
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