CN115842893A - Picture synchronous output method, device and equipment - Google Patents
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Abstract
The application discloses a method, a device and equipment for synchronously outputting pictures. Wherein, the method comprises the following steps: acquiring a first input picture and a first picture to be output corresponding to the first input picture; outputting a first output picture according to the first picture to be output, and determining a phase difference between the first picture to be output and the first output picture; acquiring a second input picture adjacent to the first input picture and a second picture to be output corresponding to the second input picture, and determining a first number of reference clock cycles corresponding to the second output picture according to the second picture to be output and the phase difference; the second output picture is output for a first number of reference clock cycles. The method and the device solve the technical problems that in the related technology, a single chip microcomputer and a clock chip are additionally introduced to maintain synchronous output of the pictures, the cost is high, and the control process is complex.
Description
Technical Field
The present application relates to the field of image display technologies, and in particular, to a method, an apparatus, and a device for synchronously outputting frames.
Background
With the rapid development of computing power and storage power of computers, the sizes of images and videos faced by the video processing industry are various and flexible, and the size of an input picture needs to be scaled to the size of a display picture according to point-to-point. The image picture and the display picture have the size range of as small as 280P and as large as 8K resolution, the sizes of the two sides can be matched at will, but the introduced problem is that delay is additionally added in an image display link, images at different positions are processed between different equipment, and finally all the images are spliced together, so that how to display the same picture at the same time needs a GENLOCK (synchronous phase lock) function, all systems process the same picture at the same time, the display is synchronously started, the synchronous picture can be ensured to be output and displayed, the output picture is ensured to be switched between different frame frequencies and stable, and the picture is not flashed, not black and not dim.
In the related art, a GENLOCK module is usually used to detect a phase difference between a picture to be output, which is expected to be output, and an output picture which is actually output, and then a single chip is used to dynamically adjust the frequency of a reference clock, and the size of the reference clock period is modified on the basis of maintaining the number of the reference clock periods corresponding to each frame of picture unchanged, so as to compensate the lead or lag of the picture. Although the scheme can keep synchronous output of the picture, a singlechip and a clock chip are additionally introduced, so that the cost is increased, and the complexity of system control is increased.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the application provides a method, a device and equipment for outputting a picture synchronously, which are used for at least solving the technical problems that in the related technology, a singlechip and a clock chip are additionally introduced for maintaining the picture synchronous output, the cost is high and the control process is complex.
According to an aspect of an embodiment of the present application, there is provided a picture synchronization output method, including: acquiring a first input picture and a first picture to be output corresponding to the first input picture; outputting a first output picture according to the first picture to be output, and determining a phase difference between the first picture to be output and the first output picture; acquiring a second input picture adjacent to the first input picture and a second picture to be output corresponding to the second input picture, and determining a first number of reference clock cycles corresponding to the second output picture according to the second picture to be output and the phase difference; outputting the second output picture within the first number of reference clock cycles.
Optionally, acquiring the first input picture at a first frame rate; and determining the first to-be-output picture at a second frame rate according to the first input picture at the first frame rate.
Optionally, the first output picture at a third frame rate is output according to the first to-be-output picture at the second frame rate.
Optionally, determining a second number of reference clock cycles corresponding to the first to-be-output picture according to the second frame rate; determining a third number of reference clock cycles corresponding to the first output picture according to the third frame rate; and determining the phase difference according to the second quantity and the third quantity.
Optionally, determining a fourth number of reference clock cycles corresponding to the second to-be-output picture; determining a fifth number of reference clock cycles corresponding to the phase difference; determining the first number according to the fourth number and the fifth number.
Optionally, comparing the phase difference with a preset threshold; when the phase difference is smaller than the preset threshold value, determining that the second output picture is a next frame picture of the first output picture; and when the phase difference is greater than the preset threshold value, determining the frame number of the second output image as a target frame number according to the phase difference, wherein the target frame number is not less than two.
Optionally, when the second output picture is a frame, outputting the second output picture within the first number of reference clock cycles; when the second output picture is a plurality of frames, determining a sixth number of reference clock cycles corresponding to each frame of the second output picture according to the first number and the target frame number, and outputting one frame of the second output picture in each sixth number of reference clock cycles.
Optionally, the reference clock cycle length is a fixed value.
According to another aspect of the embodiments of the present application, there is also provided a picture synchronization output apparatus, including: the device comprises an acquisition module, a display module and a display module, wherein the acquisition module is used for acquiring a first input picture and a first picture to be output corresponding to the first input picture; the first output module is used for outputting a first output picture according to the first picture to be output and determining the phase difference between the first picture to be output and the first output picture; the determining module is used for acquiring a second input picture adjacent to the first input picture and a second picture to be output corresponding to the second input picture, and determining a first number of reference clock cycles corresponding to the second output picture according to the second picture to be output and the phase difference; a second output module for outputting the second output picture within the first number of reference clock cycles.
According to another aspect of the embodiments of the present application, there is also provided a picture synchronization output apparatus including: a memory in which a computer program is stored, and a processor configured to execute the above-described screen synchronization output method by the computer program.
In the embodiment of the application, a first input picture and a first to-be-output picture corresponding to the first input picture are obtained, a first output picture is output according to the first to-be-output picture, and a phase difference between the first to-be-output picture and the first output picture is determined; acquiring a second input picture adjacent to the first input picture and a second picture to be output corresponding to the second input picture, and determining a first number of reference clock cycles corresponding to the second output picture according to the second picture to be output and the phase difference; the second output picture is output for a first number of reference clock cycles. The phase difference between the first to-be-output picture and the first output picture is determined only through the GENLOCK module, under the condition that the size of the reference clock cycle is not changed, the number of the reference clock cycles corresponding to the second output picture is correspondingly adjusted, picture synchronous output can be achieved, system control complexity is greatly reduced, and the technical problems that in the related art, a single chip microcomputer and a clock chip are required to be additionally introduced to maintain picture synchronous output, cost is high, and the control process is complex are solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic view showing a structure of a picture synchronization output system according to the related art;
fig. 2 is a schematic diagram of a principle of a picture synchronization output according to the related art;
FIG. 3 is a flowchart illustrating a method for outputting frames synchronously according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an input and an output of a genblock module according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a picture synchronization output according to an embodiment of the present application;
FIG. 6 is a schematic diagram of another picture synchronization output according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a picture synchronization output device according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
For a better understanding of the embodiments of the present application, some of the terms or expressions appearing in the course of describing the embodiments of the present application are to be interpreted as follows:
GENLOCK (GENLOCK): the input and output picture data field frequency is synchronized to ensure the phase delay jitter is in us level.
Example 1
In the related art, when picture output display is performed, after an input picture is determined, a picture to be output and expected to be output can be determined according to the input picture, and then an actual output picture is output according to the picture to be output, in the process, the GENLOCK module can detect a phase difference between each frame of the picture to be output and the output picture in real time and feed back the phase difference to an MCU (Microcontroller Unit, a micro control Unit, also called a single chip), the MCU performs clock configuration on a clock chip again according to the phase difference, and dynamically adjusts the REFER CLK (reference clock) frequency through the clock chip, so as to accelerate or delay the generation of the output picture, thereby ensuring that the picture to be output and the output picture are the same in frequency and phase. Generally, it is necessary to control the phase deviation of the picture to be output and the output picture to be less than 1us.
Specifically, taking fig. 2 as an example, a reference clock period corresponding to a to-be-output picture is an input stable period, a reference clock period corresponding to an output picture is an output stable period, and assuming that a frame rate of the to-be-output picture is 1, that is, 1 frame per second is a stable picture, the frame is generated from 10 reference clock periods, after the output of the first frame output picture, it is found that the frame is advanced by 1 reference clock period compared to the first frame to-be-output picture, that is, only 0.9s is used, so that the extra 0.1s must be complemented in the next frame output picture, that is, the second frame output picture needs to be output within 1.1s, but since the number of reference clock periods corresponding to the second frame output picture is still 10, at this time, the reference clock frequency can only be modified by the MCU, that is, that the size of the reference clock period is modified on the basis of maintaining the number of reference clock periods unchanged, so as to compensate for the advanced 0.1s. It should be noted that the logic of the phase lag is the same as that of the lead, and the magnitude of the reference clock period is modified to compensate for the lead or lag while maintaining the same number of reference clock periods for outputting pictures per frame.
Although the above process can realize synchronous output of pictures, since an MCU and a clock chip are additionally required, not only is the cost increased, but also the complexity of system control is increased. In order to solve the above problems, the present application proposes a new scheme: considering that the requirement of the input and output interface of the GENLOCK module on the system is not high, the time difference can be compensated by increasing or decreasing the number of the reference clock cycles instead of adjusting the size of the reference clock cycles in real time to compensate the time difference. The scheme reduces the hardware cost and the system control complexity under the condition of ensuring the input and output pictures to be synchronous, and simultaneously can ensure that the output pictures of the system are not black, not easy to flower and not flash.
In particular, the embodiments of the present application propose an embodiment of a method for outputting synchronously with a picture, it should be noted that the steps shown in the flowchart of the figure can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.
Fig. 3 is a method for outputting a picture synchronously according to an embodiment of the present application, as shown in fig. 3, the method at least includes steps S302-S308, wherein:
in step S302, a first input image and a first to-be-output image corresponding to the first input image are obtained.
The first input picture is an input one-frame or multi-frame picture, and generally, in order to accurately implement input and output picture synchronization, a phase difference needs to be detected frame by frame, so that the first input picture is preferably a frame picture; the first to-be-output picture is a picture expected to be output and determined according to the first output picture, and since the frame rate of the picture expected to be output by the user and the frame rate of the picture input by the user may be different, the frame rate of the picture input by the user needs to be adjusted, that is, the first to-be-output picture and the first input picture have the same content, but the frame rates are not necessarily the same.
Specifically, a first input picture with a first frame rate is acquired, and then a first to-be-output picture with a second frame rate is determined according to the first input picture with the first frame rate. The first frame rate and the second frame rate may be the same or different. For example, the frame rate of the first input screen is 60, and the frame rate of the first to-be-output screen may be 60, may be 30, and may be set by the user.
In step S304, the first output frame is output according to the first to-be-output frame, and a phase difference between the first to-be-output frame and the first output frame is determined.
Specifically, the first output picture at the third frame rate is output according to the first to-be-output picture at the second frame rate, wherein the first output picture is an actually output picture. It can be understood that, due to various reasons such as system delay, there may be a deviation between the frame rate of the actually output picture and the frame rate of the expected output picture, that is, there may be a phase difference between the first to-be-output picture and the first output picture, and the phase difference is detected by the GENLOCK module.
FIG. 4 is a schematic diagram of an alternative GENLOCK module input/output structure, in which the GENLOCK module receives an input frame and a to-be-output frame corresponding to the input frame, outputs an output frame according to the to-be-output frame, and detects a phase difference between the to-be-output frame and the output frame,
in some optional embodiments of the present application, since a clock chip is no longer introduced to adjust the size of the reference clock period, that is, the length of the reference clock period is a fixed value, the number of the reference clock periods may be used to reflect the phase difference between the picture to be output and the picture to be output.
Specifically, a second number of reference clock cycles corresponding to the first to-be-output picture may be determined according to the second frame rate; determining a third number of reference clock cycles corresponding to the first output picture according to a third frame rate; and determining the phase difference according to the second quantity and the third quantity.
For example, assume that a reference clock period is 0.1s, and the second frame rate of the first to-be-output picture is 1s and 1 frame of stable picture, corresponding to 10 reference clock periods; the third frame rate of the first output picture is 0.9 second and 1 frame of stable picture, and corresponds to 9 reference clock periods; the first output frame is advanced by 1 clock cycle compared to the first to-be-output frame by-1 clock cycle, i.e., -0.1s ("-" indicates advance and "+" indicates retard).
Step S306, a second input frame adjacent to the first input frame and a second to-be-output frame corresponding to the second input frame are obtained, and a first number of reference clock cycles corresponding to the second output frame is determined according to the second to-be-output frame and the phase difference.
In step S308, a second output picture is output within the first number of reference clock cycles.
After the phase difference between the first to-be-output picture and the first output picture is determined, the lead or lag of the picture can be compensated by adjusting the number of reference clock cycles corresponding to the second output picture of one or more frames adjacent to the first output picture.
Specifically, a fourth number of reference clock cycles corresponding to the second to-be-output picture may be determined; determining a fifth number of reference clock cycles corresponding to the phase difference; determining the first number according to the fourth number and the fifth number.
For example, the second to-be-output picture is still 1 frame stable picture in 1 second, and is generated by 10 reference clock cycles, that is, the fourth number is 10, and the phase difference is-1 reference clock cycle determined above, that is, the fifth number is-1, at this time, the first number of reference clock cycles corresponding to the second output picture can be determined to be 10- (-1) =11, that is, the second frame output picture is output within 11 reference clock cycles, and the previous picture advance can be compensated, so that the output picture and the to-be-output picture are phase-synchronized.
It can be understood that when the phase difference between the first to-be-output picture and the first output picture is small, the lead or lag of the picture can be compensated directly by increasing or decreasing the number of reference clock cycles of the next frame of image, and the picture effect of the actual output picture is not greatly influenced. When the phase difference between the first to-be-output picture and the first output picture is large, if the leading or lagging phase is compensated only in the next frame of picture, although the phase synchronization between the output picture and the to-be-output picture can be ensured, the difference between the number of the corresponding reference clock cycles of the two adjacent pictures is too large, and picture flicker or black screen is easy to occur. Therefore, when the phase difference between the first to-be-output picture and the first output picture is large, the leading or lagging phase is preferably compensated in the following continuous multi-frame pictures, so that the frame rate of the output picture can be normally identified by the rear-stage module, and the problems of screen flickering, screen blacking or screen blooming can not occur.
In some optional embodiments of the present application, the phase difference may be compared to a preset threshold; when the phase difference is smaller than a preset threshold value, determining that the second output picture is a next frame picture of the first output picture; and when the phase difference is greater than a preset threshold value, determining the frame number of the second output picture as a target frame number according to the phase difference, wherein the target frame number is not less than two. The preset threshold value can be determined through multiple tests, so that the target frame number is ensured to be as small as possible under the condition that the problems of screen flashing, screen blacking or screen splash and the like do not occur in the actually output picture.
Specifically, when the phase difference is smaller than the preset threshold, the second output picture is a frame, and the frame of the second output picture is output within the first number of reference clock cycles.
Taking fig. 5 as an example, assuming that the preset threshold is 3 reference clock cycles, the reference clock cycle corresponding to the to-be-output picture is an input stable cycle, the reference clock cycle corresponding to the output picture is an output stable cycle, and the frame rate of the to-be-output picture is 1, that is, 1 second 1 frame of stable picture, corresponding to 10 reference clock cycles, where only 0.9s is used for outputting the first frame of output picture, corresponding to 9 reference clock cycles, and at this time, the phase difference is 0.1s, that is, 1 reference clock cycle is advanced, and is less than the preset threshold, the first 1 reference clock cycle is directly compensated in the second frame of output picture, and it is determined that the number of reference clock cycles corresponding to the second frame of output picture is 11, that is, the second frame of output picture is output within 11 reference clock cycles (1.1 s), and picture synchronous output can be achieved.
When the phase difference is greater than the preset threshold, the second output picture is multiple frames, a sixth number of reference clock cycles corresponding to each frame in the second output picture needs to be determined according to the first number and the target frame number, and one frame in the second output picture is output in each sixth number of reference clock cycles.
Taking fig. 6 as an example, assuming that the preset threshold is 3 reference clock cycles, the reference clock cycle corresponding to the to-be-output picture is an input stable cycle, the reference clock cycle corresponding to the output picture is an output stable cycle, and the frame rate of the to-be-output picture is 1, that is, 1 second 1 frame stable picture, corresponding to 10 reference clock cycles, where only 0.6s is used for outputting the first frame output picture, corresponding to 6 reference clock cycles, and at this time, the phase difference is 0.4s, that is, 4 reference clock cycles are advanced, which is greater than the preset threshold, it is possible to compensate for 4 advanced reference clock cycles in the two subsequent adjacent frame images, adjust the number of reference clock cycles corresponding to the second frame output picture to 10, adjust the number of reference clock cycles corresponding to the third frame output picture to 14, so that the phase deviation between the two adjacent frame output pictures is 4 reference clock cycles, thereby ensuring that the frame rate of the output pictures can be normally recognized by the subsequent module, and output the second frame output picture in 1s, output the third frame output picture in 1.4s, and realize synchronous picture output, and no screen flicker or black screen flicker is possible.
In the embodiment of the application, a first input picture and a first to-be-output picture corresponding to the first input picture are obtained, a first output picture is output according to the first to-be-output picture, and a phase difference between the first to-be-output picture and the first output picture is determined; acquiring a second input picture adjacent to the first input picture and a second picture to be output corresponding to the second input picture, and determining a first number of reference clock cycles corresponding to the second output picture according to the second picture to be output and the phase difference; the second output picture is output for a first number of reference clock cycles. The phase difference between the first to-be-output picture and the first output picture is determined only through the GENLOCK module, under the condition that the size of the reference clock period is not changed, the number of the reference clock periods corresponding to the second output picture is correspondingly adjusted, picture synchronous output can be achieved, system control complexity is greatly reduced, and the technical problems that a single chip microcomputer and a clock chip are additionally introduced to maintain picture synchronous output in the related art, cost is high, and the control process is complex are solved.
Example 2
According to an embodiment of the present application, there is also provided a picture synchronization output apparatus for implementing the above picture synchronization output method, as shown in fig. 7, the apparatus includes an obtaining module 70, a first output module 72, a determining module 74 and a second output module 76, where:
the obtaining module 70 is configured to obtain a first input picture and a first to-be-output picture corresponding to the first input picture.
The first input picture is an input one-frame or multi-frame picture, and generally, in order to accurately implement input and output picture synchronization, a phase difference needs to be detected frame by frame, so that the first input picture is preferably a frame picture; the first to-be-output picture is a picture expected to be output and determined according to the first output picture, and since the frame rate of the picture expected to be output by the user and the frame rate of the picture input by the user may be different, the frame rate of the picture input by the user needs to be adjusted, that is, the first to-be-output picture and the first input picture have the same content, but the frame rates are not necessarily the same.
Specifically, a first input picture with a first frame rate is acquired, and then a first to-be-output picture with a second frame rate is determined according to the first input picture with the first frame rate. The first frame rate and the second frame rate may be the same or different.
A first output module 72, configured to output a first output picture according to the first to-be-output picture, and determine a phase difference between the first to-be-output picture and the first output picture;
specifically, the first output picture at the third frame rate is output according to the first to-be-output picture at the second frame rate, wherein the first output picture is an actually output picture. It can be understood that, due to various reasons such as system delay, there may be a deviation between the frame rate of the actually output picture and the frame rate of the expected output picture, that is, there may be a phase difference between the first to-be-output picture and the first output picture, and the phase difference is detected by the GENLOCK module.
In some optional embodiments of the present application, since a clock chip is no longer introduced to adjust the size of the reference clock period, that is, the length of the reference clock period is a fixed value, the number of the reference clock periods may be used to reflect the phase difference between the picture to be output and the picture to be output.
Specifically, the second number of reference clock cycles corresponding to the first to-be-output picture may be determined according to the second frame rate; determining a third number of reference clock cycles corresponding to the first output picture according to a third frame rate; and determining the phase difference according to the second quantity and the third quantity.
A determining module 74, configured to obtain a second input picture adjacent to the first input picture and a second to-be-output picture corresponding to the second input picture, and determine a first number of reference clock cycles corresponding to the second output picture according to the second to-be-output picture and the phase difference;
a second output module 76 for outputting a second output picture within the first number of reference clock cycles.
When the phase difference between the first to-be-output picture and the first output picture is determined, the lead or lag of the picture can be compensated by adjusting the number of reference clock cycles corresponding to the second output picture of one or more frames adjacent to the first output picture.
Specifically, a fourth number of reference clock cycles corresponding to the second to-be-output picture may be determined; determining a fifth number of reference clock cycles corresponding to the phase difference; determining the first number according to the fourth number and the fifth number.
It can be understood that when the phase difference between the first to-be-output picture and the first output picture is small, the lead or lag of the picture can be compensated directly by increasing or decreasing the number of reference clock cycles of the next frame of image, and the picture effect of the actual output picture is not greatly influenced. When the phase difference between the first to-be-output picture and the first output picture is large, if the leading or lagging phase is compensated only in the next frame of picture, although the phase synchronization between the output picture and the to-be-output picture can be ensured, the difference between the number of the corresponding reference clock cycles of the two adjacent pictures is too large, and picture flicker or black screen is easy to occur. Therefore, when the phase difference between the first to-be-output picture and the first output picture is large, the leading or lagging phase is preferably compensated in the following continuous multi-frame pictures, so that the frame rate of the output picture can be normally identified by the rear-stage module, and the problems of screen flickering, screen blacking or screen blooming can not occur.
In some optional embodiments of the present application, the phase difference may be compared to a preset threshold; when the phase difference is smaller than a preset threshold value, determining that the second output picture is a next frame picture of the first output picture; and when the phase difference is greater than a preset threshold value, determining the frame number of the second output picture as a target frame number according to the phase difference, wherein the target frame number is not less than two. The preset threshold value can be determined through multiple tests, so that the target frame number is ensured to be as small as possible under the condition that the problems of screen flashing, screen blacking or screen splash and the like do not occur in the actually output picture.
Specifically, when the phase difference is smaller than the preset threshold, the second output picture is a frame, and the frame of the second output picture is output within the first number of reference clock cycles. When the phase difference is greater than the preset threshold, the second output picture is multiple frames, a sixth number of reference clock cycles corresponding to each frame in the second output picture needs to be determined according to the first number and the target frame number, and one frame in the second output picture is output in each sixth number of reference clock cycles.
It should be noted that, in the embodiment of the present application, each module in the picture synchronization output apparatus corresponds to the implementation steps of the picture synchronization output method in embodiment 1 one to one, and since the detailed description is already performed in embodiment 1, some details that are not shown in this embodiment may refer to embodiment 1, and are not described herein again.
Example 3
According to an embodiment of the present application, there is also provided a picture synchronization output apparatus, including: a memory in which a computer program is stored, and a processor configured to execute the picture synchronization output method in embodiment 1 by the computer program.
Optionally, when the computer program is running, the processor performs the steps of: acquiring a first input picture and a first picture to be output corresponding to the first input picture; outputting a first output picture according to the first picture to be output, and determining a phase difference between the first picture to be output and the first output picture; acquiring a second input picture adjacent to the first input picture and a second picture to be output corresponding to the second input picture, and determining a first number of reference clock cycles corresponding to the second output picture according to the second picture to be output and the phase difference; the second output picture is output for a first number of reference clock cycles.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit may be a division of a logic function, and an actual implementation may have another division, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or may not be executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.
Claims (10)
1. A picture synchronous output method is characterized by comprising the following steps:
acquiring a first input picture and a first picture to be output corresponding to the first input picture;
outputting a first output picture according to the first picture to be output, and determining a phase difference between the first picture to be output and the first output picture;
acquiring a second input picture adjacent to the first input picture and a second picture to be output corresponding to the second input picture, and determining a first number of reference clock cycles corresponding to the second output picture according to the second picture to be output and the phase difference;
outputting the second output picture within the first number of reference clock cycles.
2. The method of claim 1, wherein obtaining a first input picture and a first to-be-output picture corresponding to the first input picture comprises:
acquiring the first input picture of a first frame rate;
and determining the first to-be-output picture at a second frame rate according to the first input picture at the first frame rate.
3. The method of claim 2, wherein outputting a first output picture according to the first to-be-output picture comprises:
and outputting the first output picture at a third frame rate according to the first to-be-output picture at the second frame rate.
4. The method of claim 3, wherein determining the phase difference between the first to-be-output picture and the first output picture comprises:
determining a second number of reference clock cycles corresponding to the first to-be-output picture according to the second frame rate;
determining a third number of reference clock cycles corresponding to the first output picture according to the third frame rate;
and determining the phase difference according to the second quantity and the third quantity.
5. The method of claim 1, wherein determining the first number of reference clock cycles corresponding to the second output picture according to the second to-be-output picture and the phase difference comprises:
determining a fourth number of reference clock cycles corresponding to the second picture to be output;
determining a fifth number of reference clock cycles corresponding to the phase difference;
determining the first number according to the fourth number and the fifth number.
6. The method of claim 1, wherein before determining the first number of reference clock cycles for the second output picture according to the second picture to be output and the phase difference, the method further comprises:
comparing the phase difference with a preset threshold value;
when the phase difference is smaller than the preset threshold value, determining that the second output picture is a next frame picture of the first output picture;
and when the phase difference is greater than the preset threshold value, determining the frame number of the second output image as a target frame number according to the phase difference, wherein the target frame number is not less than two.
7. The method of claim 6, wherein outputting the second output picture for the first number of reference clock cycles comprises:
outputting the second output picture within the first number of reference clock cycles when the second output picture is one frame;
and when the second output picture is a plurality of frames, determining a sixth number of reference clock cycles corresponding to each frame in the second output picture according to the first number and the target frame number, and outputting one frame in the second output picture in each reference clock cycle of the sixth number.
8. The method according to any of claims 1 to 7, wherein the reference clock cycle length is constant.
9. A picture synchronization output apparatus, comprising:
the device comprises an acquisition module, a display module and a display module, wherein the acquisition module is used for acquiring a first input picture and a first picture to be output corresponding to the first input picture;
the first output module is used for outputting a first output picture according to the first picture to be output and determining the phase difference between the first picture to be output and the first output picture;
the determining module is used for acquiring a second input picture adjacent to the first input picture and a second picture to be output corresponding to the second input picture, and determining a first number of reference clock cycles corresponding to the second output picture according to the second picture to be output and the phase difference;
a second output module for outputting the second output picture within the first number of reference clock cycles.
10. A picture synchronization output apparatus, characterized by comprising: a memory in which a computer program is stored, and a processor configured to execute the picture synchronization output method according to any one of claims 1 to 8 by the computer program.
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| CN202111108312.0A CN115842893A (en) | 2021-09-22 | 2021-09-22 | Picture synchronous output method, device and equipment |
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| CN202111108312.0A CN115842893A (en) | 2021-09-22 | 2021-09-22 | Picture synchronous output method, device and equipment |
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