CN114173166A - Image synchronous display system and method and display controller - Google Patents
Image synchronous display system and method and display controller Download PDFInfo
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/4104—Peripherals receiving signals from specially adapted client devices
- H04N21/4122—Peripherals receiving signals from specially adapted client devices additional display device, e.g. video projector
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4307—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/80—Generation or processing of content or additional data by content creator independently of the distribution process; Content per se
- H04N21/85—Assembly of content; Generation of multimedia applications
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- H04N21/8547—Content authoring involving timestamps for synchronizing content
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Abstract
The embodiment of the invention provides an image synchronous display system, an image synchronous display method and a display controller. The image synchronous display system comprises a plurality of display controllers and a plurality of displays respectively connected with the display controllers; the display controllers are in communication connection through a network; each display controller includes: port physical layer PHY chip, processor, and tunable oscillator. The PHY clocks of the display controllers are synchronized, the synchronized second pulse is used as a time reference of each display controller, and the clock frequency of the adjustable oscillator is adjusted to enable the reference signal and the synchronized second pulse to keep a preset time difference, so that image data to be displayed are synchronously displayed on the displays respectively connected with the display controllers when the images are displayed, the synchronization is realized without using a pre-designed IP core, and the limitation of hardware on the resolution ratio of the synchronously displayed images is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to an image synchronous display system, an image synchronous display method and a display controller.
Background
Currently, in many application scenarios, a plurality of display controllers are required to be capable of synchronously displaying image data sent by a server on a display connected to each display controller. However, each display controller is physically independent of the other, and in order to synchronize the display screens, the respective display controllers must synchronize their respective clocks.
Specifically, each display controller uses its own Field Programmable Gate Array (FPGA) to perform clock synchronization with FPGAs in other display controllers by using an accurate time synchronization protocol (IEEE1588), also called PTP protocol, so that each display controller outputs and displays image data at the same time.
However, in the image synchronous display method, each display controller uses an FPGA, and since an IP core in the FPGA is a functional module which is designed in advance and embedded in the FPGA, although clock synchronization can be achieved, parameter settings related to a clock in the IP core are fixed, and these parameters are decisive parameters of the resolution of the synchronously displayed image. When the resolution of the image to be displayed is changed, the parameter setting related to the clock in the IP core cannot be adjusted adaptively, so that the resolution of the synchronously displayed image is limited by using the FPGA to perform synchronous display.
Disclosure of Invention
An object of the embodiments of the present invention is to provide an image synchronous display system, method and image display device, so as to reduce the limitation of hardware on the resolution of synchronously displayed images. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present invention provides an image synchronous display system, including a plurality of display controllers and a plurality of displays respectively connected to the display controllers; the display controllers are connected through network communication;
each display controller includes: the system comprises a port physical layer (PHY) chip, a processor and an adjustable oscillator;
the PHY chip in each display controller is used for sending a pulse per second to the processor after the PHY clock is synchronized;
the processor in each display controller is used for carrying out PHY clock synchronization with processors in other display controllers in the image synchronous display system when the display controller is started, so that the PHY chip sends a pulse per second to the PHY chip after the PHY clocks are synchronized; when the pulse per second is monitored, sending a reference signal to a display connected with the display controller, and recovering the reference signal; calculating the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired; and when the time difference is not the preset standard time difference, adjusting the clock frequency of the adjustable oscillator until the time difference is the preset standard time difference.
Optionally, the reference signal is: a field sync signal, a High Definition Multimedia Interface (HDMI) signal, or a dedicated reference signal output at a fixed frequency.
Optionally, when the time difference is not a preset standard time difference, the processor in each display controller determines whether the time difference meets a preset condition; if so, calculating the adjustment quantity of the adjustable oscillator according to the difference value of the time difference and a preset standard time difference and a proportional-integral-derivative (PID) algorithm, and adjusting the clock frequency of the adjustable oscillator according to the adjustment quantity; and if not, the processor step-adjusts the clock frequency of the adjustable oscillator according to the preset adjustment quantity.
Optionally, the image synchronous display system further includes: a network switching device;
the processors in each display controller exchange clock synchronization messages with processors in other display controllers through the PHY chip connected with the processors and the network switching equipment connected with the PHY chip, so as to carry out PHY clock synchronization.
Optionally, the image synchronous display system further includes: a server; the server is in communication connection with the network switching equipment;
and the server is used for sending the image data to be displayed with the time stamp to each display controller through the network switching equipment, so that each display controller sends the image data to be displayed to the display connected with the display controller according to the time stamp to display the image.
In a second aspect, an embodiment of the present invention provides an image synchronous display method, which is applied to an image synchronous display system, where the system includes: a plurality of display controllers and a plurality of displays respectively connected to the display controllers; the display controllers are connected through network communication; each display controller includes: the system comprises a port physical layer (PHY) chip, a processor and an adjustable oscillator; the method comprises the following steps:
the server sends a clock synchronization instruction and image data to be displayed to each image display device;
the PHY chip in each image display device sends the clock synchronization instruction received from the server and the image data to be displayed to the CPU;
when the processor in each display controller is started, performing PHY clock synchronization with processors in other display controllers in the image synchronous display system to obtain a synchronous PHY clock;
the PHY chip in each display controller sends pulse per second to the processor after PHY clock synchronization;
when a processor in each display controller monitors pulse per second, sending a reference signal to a display connected with the display controller, and recovering the reference signal; calculating the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired; and when the time difference is not the preset standard time difference, adjusting the clock frequency of the adjustable oscillator until the time difference is the preset standard time difference.
Optionally, the reference signal is: a field sync signal, a High Definition Multimedia Interface (HDMI) signal, or a dedicated reference signal output at a fixed frequency.
Optionally, when the time difference is not the preset standard time difference, the step of adjusting the clock frequency of the crystal oscillator until the time difference is the preset standard time difference includes:
when the time difference is not a preset standard time difference, adjusting the clock frequency of the adjustable oscillator until the time difference is the preset standard time difference, including:
when the time difference is not a preset standard time difference, judging whether the time difference meets a preset condition; if so, calculating the adjustment quantity of the adjustable oscillator according to the difference value of the time difference and the preset time difference and a proportional-integral-derivative (PID) algorithm, and adjusting the clock frequency of the adjustable oscillator according to the adjustment quantity; and if not, the processor step-adjusts the clock frequency of the adjustable oscillator according to the preset adjustment quantity.
In a third aspect, an embodiment of the present invention provides a display controller, including a PHY chip, a processor, and an adjustable oscillator; the display controller is in communication connection with other display controllers through a network;
the PHY chip is used for sending pulse per second to the processor after PHY clock synchronization;
the processor is used for carrying out PHY clock synchronization with the processors in the other display controllers when the display controller is started, so that the PHY chip sends pulse per second to the processor after the PHY clocks are synchronized; when the pulse per second is monitored, sending a reference signal to a display connected with the display controller, and recovering the reference signal; calculating the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired; and when the time difference is not the preset standard time difference, adjusting the clock frequency of the adjustable oscillator until the time difference is the preset standard time difference.
Optionally, the reference signal is: a field sync signal, a High Definition Multimedia Interface (HDMI) signal, or a dedicated reference signal output at a fixed frequency.
Optionally, when the time difference is not a preset standard time difference, the processor in the display controller determines whether the time difference meets a preset condition; if so, calculating the adjustment quantity of the adjustable oscillator according to the difference value of the time difference and a preset standard time difference and a proportional-integral-derivative (PID) algorithm, and adjusting the clock frequency of the adjustable oscillator according to the adjustment quantity; and if not, the processor step-adjusts the clock frequency of the adjustable oscillator according to the preset adjustment quantity.
The image synchronous display system, the image synchronous display method and the display controller provided by the embodiment of the invention comprise a plurality of display controllers and a plurality of displays respectively connected with the display controllers, wherein the display controllers are in communication connection through a network. According to the embodiment of the invention, the PHY clocks of the display controllers are synchronized, the synchronized second pulse is used as the time reference of each display controller, and the reference signal and the synchronized second pulse are kept at the preset time difference by adjusting the clock frequency of the adjustable oscillator, so that the image data to be displayed are synchronously displayed on the displays respectively connected with the display controllers when the image is displayed, the synchronization is realized without using a pre-designed IP core, and the limitation of hardware on the resolution ratio of the synchronously displayed image is reduced.
Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1a is a schematic structural diagram of a synchronous image display system according to an embodiment of the present invention;
FIG. 1b is a schematic diagram of a display controller in the synchronous image display system shown in FIG. 1 a;
FIG. 2a is a schematic structural diagram of an image synchronization display system according to an embodiment of the present invention;
FIG. 2b is a schematic diagram of a display controller in the synchronous image display system shown in FIG. 2 a;
FIG. 3 is a schematic diagram illustrating a method for displaying images synchronously according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a process of adjusting the clock frequency of the tunable oscillator in the embodiment shown in fig. 3.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to reduce the limitation of hardware on the resolution of the image to be synchronously displayed, the embodiment of the invention provides an image synchronous display system, an image synchronous display method and a display controller.
As shown in fig. 1a, the image synchronization display system may include: a plurality of display controllers 110 and a plurality of displays 120 connected to the respective display controllers; the display controllers 110 are connected through network communication; as shown in fig. 1b, each display controller 110 may include: a PHY (Port Physical Layer) chip 111, a processor 112, and a tunable oscillator 113.
The PHY chip 111 in each display controller is configured to send a pulse per second to the processor after the PHY clock is synchronized;
the processor 112 in each display controller is configured to perform PHY clock synchronization with processors in other display controllers in the image synchronization display system when starting up, so that the PHY chip sends a pulse per second to itself after the PHY clock is synchronized; when the pulse per second is monitored, sending a reference signal to a display connected with a display controller, and recovering the reference signal; calculating the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired; and when the time difference is not the preset standard time difference, adjusting the clock frequency of the adjustable oscillator until the time difference is the preset standard time difference.
Specifically, the pulse per second is a pulse with a period of 1s, and its effective value may be a high level or a low level; the reference signal may be one of a field sync signal, an HDMI (High Definition Multimedia Interface) signal, or a dedicated reference signal output at a fixed frequency.
In this embodiment, when performing PHY clock synchronization, the processor in each display controller may select one PHY chip of the plurality of display controllers, and use a clock of the selected PHY chip as a master clock and clocks of other PHY chips as slave clocks; then based on PTP protocol, each processor realizes nanosecond-level accurate synchronization of PHY clocks in each display controller in a mode of receiving and transmitting messages.
It can be understood that the image synchronization display system provided by the embodiment of the present invention realizes synchronization of the whole system through two processes of synchronization of the PHY clock and adjustment of the clock frequency of the crystal oscillator in the display controller.
When the image synchronous display system is used for image synchronous display, each time the display connected with the display controller detects that the rising edge of the reference signal sent by the processor arrives, one frame of image is correspondingly displayed. For example, when the frequency of the reference signal is 60Hz, the display will detect 60 rising edges per second, i.e. 60 frames of image per second. Under the condition that PHY clocks of all the display controllers are synchronized, the second pulse sent by the PHY chips of all the display controllers are also synchronized, so that the processors of all the display controllers can synchronously send image data to the displays as long as the time difference between the second pulse monitored by all the display controllers and the time difference between the first reference signal acquired by the display controllers is a preset standard time difference, and the synchronous image display of the whole system is realized.
The image synchronous display system provided by the embodiment of the invention comprises a plurality of display controllers and a plurality of displays respectively connected with the display controllers; the display controllers are connected through network communication. The PHY clocks of the display controllers are synchronized, the synchronized second pulse is used as a time reference of each display controller, and the clock frequency of the adjustable oscillator is adjusted to enable the reference signal and the synchronized second pulse to keep a preset time difference, so that image data to be displayed are synchronously displayed on the displays respectively connected with the display controllers when the images are displayed, the synchronization is realized without using a pre-designed IP core, and the limitation of hardware on the resolution ratio of the synchronously displayed images is reduced.
Next, the image synchronization display system according to the embodiment of the present invention will be described in detail by using another embodiment.
As shown in fig. 2a, the image synchronization display system may include: a server 210, a network switching device 220, a plurality of display controllers 230, and a plurality of displays 240 respectively connected to the respective display controllers; the display controllers and the server and the network switching equipment are in communication connection through a network;
as shown in fig. 2b, each display controller 230 is connected to a display 240, and each display controller 230 may include: a power supply system 231, an RJ45 interface 232, a PHY chip 233, a CPU234, a DDR (Double Data Rate) memory 235, and a crystal oscillator 236.
And the server 210 is configured to send the image data to be displayed with the timestamp to each display controller through the network switching device, so that each display controller sends the image data to be displayed to the display connected thereto according to the timestamp to perform image display.
The processor in each display controller exchanges clock synchronization packets with the CPU in the other display controller via the PHY chip connected to itself and the network switching device 220 connected to the PHY chip, thereby performing PHY clock synchronization.
The power system 231 in the display controller is used for supplying power to the PHY chip 233, the CPU234, the DDR memory 235 and the crystal oscillator 236 in the display controller through a power bus;
an RJ45 interface 232 in the display controller is connected to the network switching device 220 through a twisted pair, and the network switching device 220 is connected to the server 210, and is configured to receive image data to be displayed with a timestamp sent by the server 210 through the network switching device 220, and send the image data to the PHY chip 233;
a PHY chip 233 for transmitting image data to be displayed received from the server 210 to the CPU 234; and sends a pulse-per-second to the CPU234 after the PHY clock is synchronized;
the CPU234 is configured to receive image data to be displayed with a timestamp sent by the server 210 when the image data to be displayed is started, and perform PHY clock synchronization with CPUs in other display controllers in the image synchronization display system, so that a PHY chip sends a pulse per second to the PHY chip after the PHY clock is synchronized; when the pulse per second is monitored, sending a reference signal and image data to be displayed to a display 240 connected with the display controller for image display, and acquiring the reference signal; calculating the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired; when the time difference is not the preset standard time difference, the clock frequency of the crystal oscillator 236 is adjusted until the time difference is the preset standard time difference.
And the DDR memory 235 is used for exchanging data of image data to be displayed with the CPU through a data bus.
And the display 240 is used for receiving image data to be displayed and displaying images.
A crystal oscillator 236 for providing a clock signal to the display controller. In the embodiment of the invention, an adjustable oscillator with adjustable frequency is adopted, such as: a high precision digitally controlled clock oscillator (DCXO).
Specifically, the PHY chip may be connected to an RJ45 interface; sending a pulse per second to the CPU through an I/O interface having an independent interrupt source; the image display device is connected with a Media Access Control (MAC) chip in a Central Processing Unit (CPU) through Reduced Gigabit Media Independent Interface (RGMII), and sends image data to be displayed to the CPU.
The CPU234 may send the reference signal and the image data to be displayed to the display 240 through the video output VO interface; the reference signal is acquired through the I/O interface; the crystal oscillator is connected through an I/O interface.
As can be seen from the embodiments shown in fig. 2a and 2b, in the embodiment of the present invention, PHY clocks of the display controllers are synchronized, then the synchronized pulse per second is used as a time reference of the display controllers, and a preset time difference is maintained between the reference signal and the synchronized pulse per second by adjusting a clock frequency of the crystal oscillator, so that image data to be displayed is synchronously displayed on the image display devices, synchronization is achieved without using a pre-designed IP core, and a limitation of hardware on a resolution of a synchronously displayed image is reduced.
Based on the image synchronous display system provided by the embodiment of the invention, the embodiment of the invention also provides an image synchronous display method. Referring to fig. 3, the method includes:
when the processor in each display controller is started, PHY clock synchronization is carried out on the processor in other display controllers in the image synchronous display system, and a synchronous PHY clock is obtained;
the PHY chip in each display controller sends pulse per second to the processor after the PHY clock is synchronous;
when a processor in each display controller monitors pulse per second, sending a reference signal to a display connected with the display controller, and acquiring the reference signal; calculating the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired; and when the time difference is not the preset standard time difference, adjusting the clock frequency of the adjustable oscillator until the time difference is the preset standard time difference.
It can be seen from the above process that, under the condition that the PHY clocks of the display controllers are synchronized, the synchronization of the second pulse sent by the PHY chips of the display controllers can be ensured, and further, as long as the difference between the time when the processor in each display controller monitors the second pulse and the time when the processor recovers the first reference signal is a preset standard time difference, the processor in each display controller can synchronously send image data to be displayed to the display, thereby realizing the image synchronous display of the whole system.
The process of the processor adjusting the clock frequency of the tunable oscillator is described in detail below. As shown in fig. 4, the method may specifically include the following steps:
s401, initializing a timer, a counter and each interrupt program.
S402, judging whether the synchronous state is started or not; if not, go to step S403; if so, step S405 is performed.
And S403, triggering a timed interrupt program by the pulse per second.
In steps S401 to S403, before system synchronization, a timer, a counter, and each interrupt program may be initialized, and whether the image synchronization display system is in a synchronization state is determined; if yes, setting the synchronization state value to be in an invalid state in the synchronization process of the PHY clock, and setting the synchronization state value to be in an valid state after the PHY clock is synchronized; if not, uploading the information of the unsynchronized pulse per second to a server, and triggering a timed interrupt program, wherein the timed interrupt program executes the following steps:
step one, opening a timer in a processor to start timing;
step two, judging whether the timer is up; if yes, the video output interface VO is started.
S404, clearing the timed interrupt program.
And S405, triggering an interrupt program for starting timing by the synchronized pulse per second.
Specifically, the interrupt routine for starting timing executes the following steps:
step one, the processor sends a reference signal and image data to be displayed to the display for image display, and starts a counter to start timing.
And step two, the reference signal is acquired, and the first reference signal after the pulse per second is monitored is obtained.
In this step, the processor may perform once extraction when the rising edge of the reference signal is detected, and receive the extracted reference signal through the I/O interface. For example, if the frequency of the reference signal is 60Hz, 60 rising edges of the reference signal will be detected within one second, i.e. 60 acquisitions will be made.
S406, judging whether the acquired signal is a first reference signal acquired or not; if not, executing step S407; if so, step S408 is performed.
S407, the interrupt routine for stopping the timing is cleared.
And S408, triggering an interruption program for stopping timing by the recovered first reference signal.
In this embodiment, the clock frequency of the adjustable oscillator is adjusted once per second, so that an interrupt program for stopping timing is triggered only when the first acquired reference signal after the pulse per second is monitored passes through the I/O interface, and the following steps are performed:
step one, closing a counter to stop timing.
And step two, reading the numerical value in the counter, and calculating and storing the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired.
In the second step, the processor can calculate and obtain the time difference between the monitored pulse per second and the first reference signal acquired according to the numerical value in the counter and the clock frequency of the counter.
S409, judging whether the time difference between the monitored pulse per second and the first reference signal meets a preset condition or not; if yes, go to step S410; if not, step S412 is performed.
In this embodiment, the preset standard time difference may be determined according to the frame rate when the images are synchronously displayed. Illustratively, if the video frame rate in this embodiment is 60Hz, the time interval between every two video frames is about 16ms, i.e. the time from the time when the processor sends the reference signal and the image data to be displayed to the display to the time when the first reference signal is acquired is 16 ms. Since this process is a round trip process, the preset standard time difference may be set to 16/2-8 ms.
Obviously, when the frame rate of the image synchronous display is changed, the preset standard time difference should be adjusted accordingly.
When judging whether the time difference meets the preset condition, the preset condition may be:
ΔT>|Tt|
that is, whether it satisfies the following formula:
ΔT>Tt||ΔT<-Tt
where Δ T represents the time difference between the time at which the pulse of seconds is detected and the time at which the first reference signal is recovered, TtRepresenting a preset standard time difference.
In order to adjust the time difference to the preset standard time difference, the processor needs to adjust the clock frequency of the adjustable oscillator multiple times. When the time difference calculated in step S408 satisfies the preset condition, a PID (proportional integral differential) algorithm may be used to accurately calculate the adjustment amount; when the calculated time difference does not meet the preset condition, the clock frequency of the adjustable oscillator can be quickly adjusted in a stepping mode according to the preset adjustment amount until the time difference meets the preset condition, and then the PID algorithm is used for carrying out accurate adjustment.
And S410, calculating the adjustment quantity of the adjustable oscillator by using a Proportional Integral Derivative (PID) algorithm.
When the PID algorithm is adopted to calculate the adjustment quantity of the adjustable oscillator, firstly, a trial and error method can be adopted to initialize a proportional parameter, an integral parameter and a differential parameter; then, according to the time difference determined in step S409, a difference between the time difference and a preset standard time difference is calculated, and an adjustment amount of the adjustable oscillator is calculated according to the following formula:
Δu(k)＝Kpe(k)+Kie(k-1)+Kde(k-2)
wherein Δ u (K) is the adjustment amount of the tunable oscillator at the K-th adjustment, Kp、Ki、KdRespectively are a proportional parameter, an integral parameter and a differential parameter, and e (k-1) and e (k-2) are respectively the difference value between the time difference and the preset standard time difference when the adjustment is performed for the k-1 th time and the adjustment is performed for the k-2 th time.
PID algorithm by Kp、Ki、KdThe combination of the three parameters controls the control quantity, i.e. the time difference in the present embodiment, byThe algorithm is simple and strong in robustness, so that the image synchronous display system can quickly adjust the clock frequency of the adjustable oscillator.
And S411, adjusting the clock frequency of the adjustable oscillator according to the calculated adjustment amount.
And S412, adjusting the clock frequency of the adjustable oscillator step by step according to the preset adjustment amount.
Specifically, the adjustable oscillator may be a high-precision digitally controlled clock oscillator, and the step value is a frequency value when the clock frequency is adjusted each time. In this embodiment, a SIT3907 high-precision digitally controlled clock oscillator may be selected, and the step value parameter thereof is adjusted to 1ppb (part per billion), that is: the frequency value of each adjustment is one billionth of the clock frequency of the high-precision digitally controlled clock oscillator.
As can be seen from the process shown in fig. 4, the image synchronous display system corrects the time delay of each display controller by using the pulse per second, and then uses the synchronized pulse per second as a time reference, so that the time of each display controller and the time of the pulse per second monitored by the processor are kept fixed, thereby realizing synchronous display of images, solving the problems of image flicker, image tearing and the like caused by network delay or clock desynchronization of different display controllers, and bringing better viewing experience to users; meanwhile, the image synchronous display method provided by the embodiment of the invention does not need to use an FPGA (field programmable gate array), so that the limitation of an IP (Internet protocol) kernel in the FPGA on the resolution of the synchronously displayed image during design is avoided.
An embodiment of the present invention further provides a display controller, as shown in fig. 1b, including: port physical layer PHY chip 111, processor 112, and tunable oscillator 113; the display controller is in communication connection with other display controllers through a network;
and the PHY chip 111 is configured to send a pulse per second to the processor after the PHY clock is synchronized.
The processor 112 is configured to perform PHY clock synchronization with processors in other display controllers when the display controller is started, so that the PHY chip sends a pulse per second to the PHY chip after the PHY clock synchronization; when the pulse per second is monitored, sending a reference signal to a display connected with a display controller, and extracting the reference signal; calculating the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired; when the time difference is not the preset standard time difference, the clock frequency of the adjustable oscillator 113 is adjusted until the time difference is the preset standard time difference.
Optionally, the reference signal is: a field sync signal, a High Definition Multimedia Interface (HDMI) signal, or a dedicated reference signal output at a fixed frequency.
Optionally, the processor in the display controller determines whether the time difference meets a preset condition when the time difference is not a preset standard time difference; if so, calculating the adjustment quantity of the adjustable oscillator according to the difference value of the time difference and the preset standard time difference and a proportional-integral-derivative (PID) algorithm, and adjusting the clock frequency of the oscillator according to the adjustment quantity; and if not, the processor adjusts the clock frequency of the adjustable oscillator step by step according to the preset adjustment quantity.
The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
In another embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, and the computer program, when executed by a processor, implements the steps of any one of the image synchronous display methods described above.
In yet another embodiment of the present invention, there is also provided a computer program product containing instructions which, when run on a computer, cause the computer to perform any of the image synchronization display methods of the above embodiments.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the device embodiment, since it is substantially similar to the system embodiment, the description is simple, and the relevant points can be referred to the partial description of the system embodiment.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (11)
1. An image synchronous display system is characterized by comprising a plurality of display controllers and a plurality of displays respectively connected with the display controllers; the display controllers are connected through network communication;
each display controller includes: the system comprises a port physical layer (PHY) chip, a processor and an adjustable oscillator;
the PHY chip in each display controller is used for sending a pulse per second to the processor after the PHY clock is synchronized;
the processor in each display controller is used for carrying out PHY clock synchronization with processors in other display controllers in the image synchronous display system when the display controller is started, so that the PHY chip sends a pulse per second to the PHY chip after the PHY clocks are synchronized; when the pulse per second is monitored, sending a reference signal to a display connected with the display controller, and recovering the reference signal; calculating the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired; and when the time difference is not the preset standard time difference, adjusting the clock frequency of the adjustable oscillator until the time difference is the preset standard time difference.
2. The system of claim 1,
the reference signal is: a field sync signal, a High Definition Multimedia Interface (HDMI) signal, or a dedicated reference signal output at a fixed frequency.
3. The system of claim 1,
when the time difference is not a preset standard time difference, a processor in each display controller judges whether the time difference meets a preset condition; if so, calculating the adjustment quantity of the adjustable oscillator according to the difference value of the time difference and a preset standard time difference and a proportional-integral-derivative (PID) algorithm, and adjusting the clock frequency of the adjustable oscillator according to the adjustment quantity; and if not, the processor step-adjusts the clock frequency of the adjustable oscillator according to the preset adjustment quantity.
4. The system of claim 1, wherein the image-synchronized display system further comprises: a network switching device;
the processors in each display controller exchange clock synchronization messages with processors in other display controllers through the PHY chip connected with the processors and the network switching equipment connected with the PHY chip, so as to carry out PHY clock synchronization.
5. The system of claim 4, wherein the image-synchronized display system further comprises: a server; the server is in communication connection with the network switching equipment;
and the server is used for sending the image data to be displayed with the time stamp to each display controller through the network switching equipment, so that each display controller sends the image data to be displayed to the display connected with the display controller according to the time stamp to display the image.
6. An image synchronous display method is characterized by being applied to an image synchronous display system, and the system comprises the following components: a plurality of display controllers and a plurality of displays respectively connected to the display controllers; the display controllers are connected through network communication; each display controller includes: the system comprises a port physical layer (PHY) chip, a processor and an adjustable oscillator;
the method comprises the following steps:
when the processor in each display controller is started, performing PHY clock synchronization with processors in other display controllers in the image synchronous display system to obtain a synchronous PHY clock;
the PHY chip in each display controller sends pulse per second to the processor after PHY clock synchronization;
when a processor in each display controller monitors pulse per second, sending a reference signal to a display connected with the display controller, and recovering the reference signal; calculating the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired; and when the time difference is not the preset standard time difference, adjusting the clock frequency of the adjustable oscillator until the time difference is the preset standard time difference.
7. The method of claim 6, wherein the reference signal is: a field sync signal, a High Definition Multimedia Interface (HDMI) signal, or a dedicated reference signal output at a fixed frequency.
8. The method of claim 6,
when the time difference is not a preset standard time difference, adjusting the clock frequency of the adjustable oscillator until the time difference is the preset standard time difference, including:
when the time difference is not a preset standard time difference, judging whether the time difference meets a preset condition; if so, calculating the adjustment quantity of the adjustable oscillator according to the difference value of the time difference and the preset time difference and a proportional-integral-derivative (PID) algorithm, and adjusting the clock frequency of the adjustable oscillator according to the adjustment quantity; and if not, the processor step-adjusts the clock frequency of the adjustable oscillator according to the preset adjustment quantity.
9. A display controller, comprising a PHY chip, a processor, and a tunable oscillator; the display controller is in communication connection with other display controllers through a network;
the PHY chip is used for sending pulse per second to the processor after PHY clock synchronization;
the processor is used for carrying out PHY clock synchronization with the processors in the other display controllers when the display controller is started, so that the PHY chip sends pulse per second to the processor after the PHY clocks are synchronized; when the pulse per second is monitored, sending a reference signal to a display connected with the display controller, and recovering the reference signal; calculating the time difference between the time when the pulse per second is monitored and the time when the first reference signal is acquired; and when the time difference is not the preset standard time difference, adjusting the clock frequency of the adjustable oscillator until the time difference is the preset standard time difference.
10. The controller of claim 9, wherein the reference signal is: a field sync signal, a High Definition Multimedia Interface (HDMI) signal, or a dedicated reference signal output at a fixed frequency.
11. The controller of claim 9,
the processor in the display controller judges whether the time difference meets a preset condition or not when the time difference is not a preset standard time difference; if so, calculating the adjustment quantity of the adjustable oscillator according to the difference value of the time difference and a preset standard time difference and a proportional-integral-derivative (PID) algorithm, and adjusting the clock frequency of the adjustable oscillator according to the adjustment quantity; and if not, the processor step-adjusts the clock frequency of the adjustable oscillator according to the preset adjustment quantity.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116261002A (en) * | 2023-05-15 | 2023-06-13 | 广州美凯信息技术股份有限公司 | Display synchronization system for video spelling control |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101815177A (en) * | 2010-03-11 | 2010-08-25 | 广东威创视讯科技股份有限公司 | Synchronous displaying device, synchronous displaying method and superposition splice displaying system |
| CN104506888A (en) * | 2014-12-31 | 2015-04-08 | 广东威创视讯科技股份有限公司 | Clock synchronizing device, method and system |
| KR20170016424A (en) * | 2017-02-03 | 2017-02-13 | 한화테크윈 주식회사 | Digital image transmitting/receiving system based on ethernet |
| CN106412633A (en) * | 2016-10-12 | 2017-02-15 | 北京蓝拓扑电子技术有限公司 | Screen mapping method and display clock synchronization control method and system of distributed multi-screen splicing controller |
| CN106982383A (en) * | 2017-04-26 | 2017-07-25 | 威盛电子股份有限公司 | Distributed video shows system, control device and control method |
-
2020
- 2020-09-10 CN CN202010946350.2A patent/CN114173166A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101815177A (en) * | 2010-03-11 | 2010-08-25 | 广东威创视讯科技股份有限公司 | Synchronous displaying device, synchronous displaying method and superposition splice displaying system |
| CN104506888A (en) * | 2014-12-31 | 2015-04-08 | 广东威创视讯科技股份有限公司 | Clock synchronizing device, method and system |
| CN106412633A (en) * | 2016-10-12 | 2017-02-15 | 北京蓝拓扑电子技术有限公司 | Screen mapping method and display clock synchronization control method and system of distributed multi-screen splicing controller |
| KR20170016424A (en) * | 2017-02-03 | 2017-02-13 | 한화테크윈 주식회사 | Digital image transmitting/receiving system based on ethernet |
| CN106982383A (en) * | 2017-04-26 | 2017-07-25 | 威盛电子股份有限公司 | Distributed video shows system, control device and control method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116261002A (en) * | 2023-05-15 | 2023-06-13 | 广州美凯信息技术股份有限公司 | Display synchronization system for video spelling control |
| CN116261002B (en) * | 2023-05-15 | 2023-11-10 | 广州美凯信息技术股份有限公司 | Display synchronization system for video spelling control |
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