CN113453053B - Distributed video synchronous display system, video synchronous display method and storage medium - Google Patents
Distributed video synchronous display system, video synchronous display method and storage medium Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4307—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen
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- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/80—Generation or processing of content or additional data by content creator independently of the distribution process; Content per se
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Abstract
The embodiment of the application provides a distributed video synchronous display system, a video synchronous display method and a storage medium, synchronous timestamps recorded by input nodes and output nodes are synchronized by utilizing a preset precise clock synchronization protocol, the synchronous timestamps are discretized for synchronous timestamp management, the output nodes calculate target difference values of a first synchronous timestamp and a second synchronous timestamp, and received target video frames are cut into blocks to be displayed on a screen under the condition that the target difference values are equal to a preset difference value threshold value, so that the synchronism of output images of the output nodes in the distributed system is increased. The system frequency is configured through the adjustable crystal oscillator, the clock frequency synchronization of the output node system is kept, the deviation is prevented, the PID control algorithm can be used for rapidly and effectively converging to obtain the phase deviation, the VS signal phase adjustment is carried out, and therefore the synchronism of the output images of all the output nodes is further improved.
Description
Technical Field
The present application relates to the field of image processing technologies, and in particular, to a distributed video synchronous display system, a video synchronous display method, and a storage medium.
Background
In a centralized video synchronous display system, in order to ensure that respective videos of each output node can be output to a spliced screen for synchronous display, a unified clock source is generally adopted, so that the clocks of each output node are ensured to be consistent and have the same frequency and the same phase, and therefore each output node can synchronously output and display at an appointed time according to the unified clock source. Although each output node can use the same reference clock through network timing, certain errors exist in network timing due to the conditions of network stability factors, time delay and the like, so that the clock error of each output node reaches a millisecond level or more, and the same frame of image output by each output node at the same time cannot be ensured.
Disclosure of Invention
An object of the embodiments of the present application is to provide a distributed video synchronous display system, a video synchronous display method, and a storage medium, so as to increase the synchronicity of output images in the distributed system. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a distributed video synchronous display system, including:
the system comprises at least one input node and a plurality of output nodes, wherein one input node is connected with at least two output nodes;
the input node is configured to acquire a first synchronization timestamp when a frequency division interrupt is triggered for each target video frame slice of a same video frame to be currently sent, and send each target video frame slice carrying the first synchronization timestamp to a corresponding output node, respectively, where the frequency of the frequency division interrupt trigger is the same as the frame rate of a video, the video includes the video frame, the corresponding output node is an output node connected to the input node, and one target video frame slice is sent to one corresponding output node;
the output node is used for acquiring a second synchronization timestamp when the current frequency division interrupt is triggered when the next output interrupt trigger after the target video frame carrying the first synchronization timestamp is cut into blocks is received, and determining the difference value between the second synchronization timestamp and the first synchronization timestamp to obtain a target difference value; under the condition that the target difference value is equal to a preset difference value threshold value, the received target video frame is cut into blocks and displayed on a screen, wherein the preset difference value threshold value is an integral multiple of the time length represented by the frequency triggered by the interruption;
the clock synchronization is carried out between the at least one input node and the plurality of output nodes through a preset precise clock synchronization protocol, the frequency division interrupt trigger period of the input node and the frequency division interrupt trigger period of each output node are in the same frequency and phase, and the output interrupt trigger period of each output node is in the same frequency and phase.
In a possible implementation manner, the output node is further configured to discard the received target video frame block if the target difference is greater than a preset difference threshold; and/or waiting for the next output interruption trigger under the condition that the target difference is smaller than a preset difference threshold.
In a possible implementation manner, the output node is further configured to reset the output function of the output node after a preset delay time period elapses from the time of the pulse-per-second interrupt trigger, where the preset delay time period is smaller than a time period represented by the frequency of the frequency-division interrupt trigger.
In a possible implementation manner, the output node is further configured to obtain a vertical synchronization signal of a video frame slice output by the output node, and adjust a clock frequency output by an adjustable crystal oscillator of the output node according to a phase deviation of the vertical synchronization signal and a pulse per second interrupt signal, so that an error between the phase deviation and a preset target deviation is within a preset error range.
In a possible implementation manner, the output node is specifically configured to calculate a correction time offset through a preset PID control algorithm according to a vertical synchronization signal and a pulse per second interrupt signal, and adjust a clock frequency output by an adjustable crystal oscillator of the output node according to the correction time offset.
In a possible implementation manner, the system further includes a plurality of display screens, and the display screens correspond to the output nodes one to one, wherein a spliced screen is formed by the plurality of display screens.
In a second aspect, an embodiment of the present application provides a distributed video synchronous display method, which is applied to a distributed video synchronous display system, where the distributed video synchronous display system includes at least one input node and a plurality of output nodes, and one input node is connected to at least two output nodes;
the method comprises the following steps:
the input node acquires a first synchronization timestamp when a current frequency division interruption is triggered aiming at each target video frame block of the same video frame to be sent currently, and sends each target video frame block carrying the first synchronization timestamp to a corresponding output node respectively, wherein the frequency of the frequency division interruption trigger is the same as the frame rate of a video, the video comprises the video frame, the corresponding output node is an output node connected with the input node, and one target video frame block is sent to one corresponding output node;
the output node acquires a second synchronization timestamp when the current frequency division interruption is triggered when receiving the next output interruption trigger after the target video frame carrying the first synchronization timestamp is cut into blocks, and determines the difference value between the second synchronization timestamp and the first synchronization timestamp to obtain a target difference value; under the condition that the target difference value is equal to a preset difference value threshold value, the received target video frame is cut into blocks and displayed on a screen, wherein the preset difference value threshold value is an integral multiple of the time length represented by the frequency triggered by the interruption;
the clock synchronization is carried out between the at least one input node and the plurality of output nodes through a preset precise clock synchronization protocol, the frequency division interrupt trigger period of the input node and the frequency division interrupt trigger period of each output node are in the same frequency and phase, and the output interrupt trigger period of each output node is in the same frequency and phase.
In one possible embodiment, the method further comprises:
under the condition that the target difference value is larger than a preset difference value threshold value, the output node blocks and discards the received target video frame; and/or
And waiting for the next output interruption trigger under the condition that the target difference is smaller than a preset difference threshold.
In one possible embodiment, the method further comprises:
and when a preset delay time length passes from the moment of triggering the second pulse interruption, resetting the output function of the output node by the output node, wherein the preset delay time length is less than the time length represented by the frequency triggered by the frequency division interruption.
In one possible embodiment, the method further comprises:
the output node acquires a vertical synchronization signal of a video frame block output by the output node, and adjusts the clock frequency output by the adjustable crystal oscillator of the output node according to the phase deviation of the vertical synchronization signal and the second pulse interrupt signal, so that the error between the phase deviation and a preset target deviation is within a preset error range.
In one possible embodiment, the adjusting the clock frequency of the tunable crystal oscillator output of the output node according to the phase deviation of the vertical synchronization signal and the pulse per second interrupt signal includes:
and the output node calculates a correction time offset through a preset PID control algorithm according to the vertical synchronous signal and the pulse per second interrupt signal, and adjusts the clock frequency output by the adjustable crystal oscillator of the output node according to the correction time offset.
In a possible implementation manner, the system further includes a plurality of display screens, and the display screens correspond to the output nodes one to one, wherein the plurality of display screens form a spliced screen.
In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements the distributed video synchronous display method described in any of the present application.
The embodiment of the application has the following beneficial effects:
the distributed video synchronous display system provided by the embodiment of the application comprises at least one input node and a plurality of output nodes, wherein one input node is connected with at least two output nodes; the system comprises an input node, a corresponding output node and a frequency division interrupt processing node, wherein the input node is used for acquiring a first synchronization timestamp when a current frequency division interrupt is triggered aiming at each target video frame block of the same video frame to be sent currently, and sending each target video frame block carrying the first synchronization timestamp to the corresponding output node respectively, wherein the frequency of the frequency division interrupt trigger is the same as the frame rate of the video, the video comprises the video frames, the corresponding output node is an output node connected with the input node, and one target video frame block is sent to one corresponding output node; the output node is used for acquiring a second synchronous time stamp when the current frequency division interrupt is triggered when the next output interrupt trigger after the target video frame carrying the first synchronous time stamp is cut into blocks is received, and determining the difference value between the second synchronous time stamp and the first synchronous time stamp to obtain a target difference value; under the condition that the target difference value is equal to a preset difference value threshold value, the received target video frame is cut into blocks and displayed on a screen, wherein the preset difference value threshold value is an integral multiple of the time length represented by the frequency triggered by interruption; the clock synchronization is carried out between at least one input node and a plurality of output nodes through a preset precise clock synchronization protocol, the frequency division interrupt trigger period of the input node and the frequency division interrupt trigger period of each output node are in the same frequency and phase, and the output interrupt trigger period of each output node is in the same frequency and phase.
The synchronous timestamps recorded by all input nodes and output nodes are synchronized by utilizing a preset precise clock synchronization protocol, the synchronous timestamps are discretized for management, the output nodes calculate the target difference value of the first synchronous timestamp and the second synchronous timestamp, and the received target video frames are cut into blocks to be displayed on a screen under the condition that the target difference value is equal to a preset difference value threshold value, so that the synchronism of the output images of all the output nodes in the distributed system is improved. Of course, not all advantages described above need to be achieved at the same time in the practice of any one product or method of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a first schematic diagram of a distributed video synchronization display system according to an embodiment of the present application;
FIG. 2a is a second schematic diagram of a distributed video synchronization display system according to an embodiment of the present application;
FIG. 2b is a third schematic diagram of a distributed video synchronization display system according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating an operation process of the distributed video synchronization display system according to the embodiment of the present application;
FIG. 4 is a schematic diagram illustrating an output module reset process according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a corresponding relationship between a frequency division interrupt trigger time and an output interrupt trigger time according to an embodiment of the present application;
fig. 6 is another schematic diagram of a correspondence relationship between a frequency division interrupt trigger time and an output interrupt trigger time according to an embodiment of the present application;
FIG. 7 is a diagram illustrating the hardware principle of an output node according to an embodiment of the present application;
FIG. 8 is a schematic diagram illustrating a principle of adjusting a clock frequency of an adjustable crystal oscillator output in an output node according to an embodiment of the present application;
fig. 9 is a schematic diagram illustrating a process of determining a correction time offset in adjusting a clock frequency output by an adjustable crystal oscillator in an output node according to an embodiment of the present application;
FIG. 10 is a first schematic diagram of a process for adjusting a clock frequency of an adjustable crystal oscillator output in an output node according to an embodiment of the present application;
FIG. 11 is a second schematic diagram of a process for adjusting the clock frequency of the tunable crystal output in the output node according to an embodiment of the present application;
fig. 12 is a schematic diagram of a distributed video synchronous display method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the description herein are intended to be within the scope of the present disclosure.
First, terms in the present application are explained:
distributed: compared with a centralized system, the distributed video synchronous display system can be a distributed system with a full-network architecture, all nodes in the system are connected through network paths, all nodes are communicated through a network, and each node has an independent clock source;
IEEE 1588: the Precision clock synchronization Protocol standard of the network measurement and control system adopts PTP (Precision Time Protocol), and periodically corrects and synchronizes the clocks of all nodes in the network through a synchronizing signal, so that the Ethernet-based distributed system can achieve the accurate synchronization of sub-microsecond level, and the standard aims to accurately synchronize the clocks which are dispersed and independently run in the measurement and control system;
PPS (Pulse Per Second): pulse signals with the period of 1 second are generated by a network PHY (Port Physical Layer) chip supporting the 1588 function and input to each distributed node, and the PPS signals can be ensured to be completely in the same frequency and phase after IEEE1588 is synchronized;
VS: (Vertical Synchronization), indicating the end of the previous frame of the video signal and the start of a new frame, can be extracted from the standard video signal, and the video output can be synchronized by means of the Synchronization VS;
interrupting: the signal received by the processor from hardware or software is processed by the processor according to the signals sent by different interrupt sources. In the present application, various interrupt signals are involved, and in one example, the pulse interrupt trigger may be a PPS interrupt trigger, which is triggered by an interrupt signal generated by a PPS signal of a PHY chip; the frequency division interrupt trigger (also called interrupt trigger of the synchronization time stamp module) is triggered by a PPS frequency division interrupt signal and is used for recording a synchronization time stamp; the output interrupt trigger (also called interrupt trigger of output node) is a soft interrupt signal generated in the output node, and the output node starts to process the output of the video frame when triggered; the input interrupt is an interrupt signal generated by triggering a video input source; the VS interrupt is an interrupt signal generated by triggering of a video VS signal;
DCXO (Digitally controlled programmable oscillator): the digital frequency pulling signal can be received, and the crystal oscillator is driven to output a corrected clock frequency signal;
PPM/PPB: parts per million/billion, which is used to express the unit of crystal oscillator precision error;
PID: a proportional (proportional) integral (integral) derivative (differential) control algorithm is an abbreviation of a closed-loop control algorithm, and is corrected according to output feedback of a controlled object, and the deviation of the controlled object can be effectively corrected through proportional, integral and derivative, so that the controlled object can reach a stable state.
In order to increase the synchronicity of output images in a distributed system, an embodiment of the present application provides a distributed video synchronization display system, which, referring to fig. 1, includes:
at least one input node 11 and a plurality of output nodes 12, wherein one input node 11 is connected with at least two output nodes 12;
the input node 11 is configured to obtain, for each target video frame slice of the same video frame to be currently sent, a first synchronization timestamp when a frequency division interrupt is triggered, and send each target video frame slice carrying the first synchronization timestamp to a corresponding output node, respectively, where a frequency of the frequency division interrupt trigger is the same as a frame rate of a video, the video includes the video frame, the corresponding output node is an output node connected to the input node, and one target video frame slice is sent to one corresponding output node.
And the synchronous time stamps carried by the target video frame blocks of the same video frame are the same.
The output node 12 is configured to, when receiving a next output interrupt trigger after a target video frame carrying a first synchronization timestamp is cut into blocks, obtain a second synchronization timestamp when a current frequency division interrupt is triggered, and determine a difference between the second synchronization timestamp and the first synchronization timestamp to obtain a target difference; and under the condition that the target difference is equal to a preset difference threshold, cutting the received target video frame into blocks and displaying the blocks on a screen, wherein the preset difference threshold is an integral multiple of the time length represented by the frequency triggered by the interruption.
The clock synchronization is carried out between the at least one input node and the plurality of output nodes through a preset precise clock synchronization protocol, the frequency division interrupt trigger period of the input node and the frequency division interrupt trigger period of each output node are in the same frequency and phase, and the output interrupt trigger period of each output node is in the same frequency and phase.
In the distributed video synchronous display system of the embodiment of the application, the nodes are communicated with each other through a network, clocks of the nodes are different, an input node acquires a current video frame to be output from a video source, and splits the video frame into n video frame blocks, wherein n is the number of output nodes connected with the input node, and the n video frame blocks can be combined into the video frame; the input nodes respectively send corresponding video frame blocks to each output node, and the output nodes display the video frame blocks received by the output nodes on a screen. The same frequency and same phase in the embodiment of the present application mean that both the frequency and the phase are the same, for example, the same frequency and same phase are triggered by the output interrupt of each output node, which means that both the frequency and the phase are the same for the output interrupt of each output node. It is understood that in practical implementation, the phases or frequencies of different nodes may not be identical, and may be considered identical as long as the error is within a preset range.
The number of the input nodes and the number of the output nodes can be set in a user-defined mode according to actual conditions. In one example, as shown in fig. 2a, the distributed video synchronous display system includes an input node and four output nodes, a video frame is divided into four video frame blocks, and each output node is responsible for the on-screen display of one video frame block. In a possible implementation manner, the system further includes a plurality of display screens, and the display screens correspond to the output nodes one to one, wherein the plurality of display screens form a spliced screen. In one example, as shown in fig. 2b, the distributed video synchronous display system includes two input nodes and four output nodes, each input node is connected to two output nodes, the signal source splits the same video frame into two parts, and each input node receives one part; for each input node, the input node divides a received video frame part into two video frame blocks, and respectively sends the two video frame blocks to the corresponding output node connected with the input node, and the output node displays the video frame blocks received by the output node on a screen.
Clocks among nodes (including input nodes and output nodes) need to be kept synchronous, specifically, the clocks of the nodes can be synchronized through a preset precise clock synchronization protocol, in one example, the preset precise clock synchronization protocol may be IEEE1588, a protocol function of IEEE1588 can be realized by a network PHY chip, and a PTP clock is used as a synchronization timestamp. The clock in the whole system can be divided into a master clock and a slave clock according to the communication relation by utilizing IEEE1588, and the slave clock establishes synchronization with the master clock by exchanging a synchronization message with the master clock; the synchronous message received and transmitted by the network contains a timestamp, and the receiving node can calculate the clock error and the time delay of the receiving node in the network so as to correct the time.
In one example, a Linux system is running on each node, and the IEEE1588 protocol functions are specifically supported by corresponding PHY drivers, for example, PTP4l open source tools may be used to synchronize PTP clocks of each node. PTP4l is open source code for the IEEE1588 v2 PTP protocol stack. The PTP4l tool runs in the background at the two ends of the master clock and the slave clock respectively, and the slave clock is automatically established and kept synchronous with the master clock. Besides the function of realizing PTP clock synchronization, the PHY chip also provides PPS hardware interruption, PPS signals input to each node have the same frequency and phase, and the interruption signals used for recording the synchronization timestamp after frequency division can be ensured to have the same frequency and phase. The specific manner of clock calibration of IEEE1588 can be referred to related IEEE1588 protocol, and is not described herein again.
When receiving the frequency division interrupt signal, the node triggers frequency division interrupt, namely frequency division interrupt triggering. The transmission frequency of the frequency division interrupt signal (i.e., the frequency of the frequency division interrupt trigger) is the same as the frame rate of the currently output video, and in one example, the frequency division may be performed by using a PPS signal generated synchronously by a preset precision clock synchronization protocol (e.g., IEEE 1588).
The synchronous time stamps are discretely recorded at the triggering moment of frequency division interruption, and the time stamps of the input node and the output node are the time stamps with fixed time intervals, so that the purpose of quantitative comparison is facilitated. Since different output nodes receive different video frame blocks of the same video frame at different times, if the continuous time is directly used as the time stamp, comparison needs to be performed within a time range, and the range is difficult to determine. And the clock frequency of the input node is not completely consistent with the clock frequency of the output node, and the video input interrupt trigger of the input node is driven by an input source, so that a fixed phase relation with the interrupt trigger of the synchronous time stamp module or the interrupt trigger of the output module cannot be ensured, and a critical condition also exists even if a time range is used for comparison.
In a possible implementation manner, the output node is further configured to discard the received target video frame block if the target difference is greater than a preset difference threshold; and/or waiting for the next output interruption trigger under the condition that the target difference is smaller than a preset difference threshold.
When next output interruption trigger after a target video frame is cut into blocks is received, an output node acquires a second synchronization timestamp when the current frequency division interruption trigger is received, and a target difference value is obtained by determining the difference value between the second synchronization timestamp and a first synchronization timestamp; under the condition that the target difference value is equal to a preset difference value threshold value, the received target video frame is cut into blocks and displayed on a screen within a time period corresponding to the current output interruption; under the condition that the target difference value is larger than a preset difference value threshold value, the received target video frame is cut into blocks and discarded; and under the condition that the target difference value is smaller than the preset difference value threshold value, judging again after waiting for the next output interruption trigger.
The time stamp comparison process is to apply the same time stamp, i.e. the first synchronization time stamp, to each video frame block of the same video frame at the input node, and then compare the first synchronization time stamp with the current second synchronization time stamp at the output node, so as to determine whether to output the current video frame block, and the process may include the following steps:
And 2, the input node marks the latest synchronization time stamp t0 of the current node on the video frame block of each frame image.
And 3, acquiring the video frame blocks by the output node, and subtracting t0 from the current latest synchronous time stamp t1 to obtain delta t when the actual output module processes the video frame blocks, namely when the next output interruption trigger after the video frame is received.
And step 4, comparing the delta t with a preset difference threshold value, determining whether to output the current frame, outputting when the delta t is equal to an empirical value, waiting when the delta t is smaller than the empirical value, and discarding when the delta t is larger than the empirical value.
The preset difference threshold is an empirical value, is an integral multiple of the interval duration between video frames, namely, the integral multiple of the duration represented by the frequency triggered by the interruption, needs to be determined according to the network delay condition of each node, and can generally select the normal maximum delay; taking four output nodes as an example, the network delays from the input node to the four output nodes of the video frame segment are a1, a2, a3 and a4 respectively, wherein a3 is the largest, the interval duration between the video frames is b, a preset difference threshold nb is selected to satisfy (n-1) b < a3 < nb, and n is a positive integer.
The following is illustrated by way of example in FIG. 3:
1. each node in the system runs a synchronization timestamp management module, and continuously records and updates the latest synchronization timestamp T of the current node when frequency division interruption is triggeredn，Tn+1，Tn+2……；
2. The n frame video frame of the input node is cut into blocks and is provided with a synchronization time stamp T0 which is the latest synchronization time stamp TnI.e. T0 ═ Tn；
3. After receiving the n-th frame of video frame and the block, the output node 1 compares the time of interrupt processing of the next video output module, i.e. the output interrupt trigger time, with the current latest synchronization time timestamp T1, where T1 is T ═ Tn+1To obtain Δ T ═ Tn+1-T n1 frame interval duration;
4. similarly, the nth frame video frames of output node 2 and output node 4 are cut into blocks: Δ T ═ Tn+2-T n2 frame interval duration;
5. the output node 3 receives the n-th frame video frame slice Δ T ═ Tn+3-Tn Frame interval duration 3;
6. the preset difference threshold is 2 x frame interval duration, the comparison result is that the nth frame of the output node 1 waits to be output when receiving the next output interrupt trigger after the nth frame, the nth frames of the output node 2 and the output node 4 are directly output when receiving the next output interrupt trigger after the nth frame, and the nth frame of the node 3 is discarded when receiving the next output interrupt trigger after the nth frame.
Under normal conditions, the maximum delay is about two frames, so the preset difference threshold is selected to be 2 x frame interval duration, only the nth frame of the node 3 has abnormal delay, and if the condition that most video frames of a certain output node have larger transmission delay occurs, the adjustment of the empirical value needs to be considered.
In order to output images synchronously at the same time by each output node, the video output modules of each node should be kept synchronous. In the centralized system, a synchronous interrupt can be issued from the main control to each output subsystem, and the output module is reset after the subsystems receive the interrupt, so that the output module can be synchronized. Then, because the clock sources of the nodes in the distributed system are independent, and the clock signals of the respective crystal oscillators are not in the same frequency and phase, it is not possible to ensure that the output modules can keep synchronization even if running for a long time, and under the condition that the clock signals of the output modules are not synchronized, a frame difference condition may occur in a critical condition.
In order to solve the problem, in a possible embodiment, the output node is further configured to reset the output function of the output node after a preset delay time period elapses from the time when the pulse-per-second interrupt signal occurs, where the preset delay time period is less than a time period represented by the frequency of the divided interrupt trigger.
Each output node resets the output module based on the PPS interrupt signal, i.e., resets the output function, and in one example, the reset flow of the output module may be as shown in fig. 4 as follows: when output synchronization is needed, setting vo _ ctrl _ flag to 1, and resetting the output function, including resetting programs related to the output function, the output frame rate, the mosaic picture layout, and the like, can affect the video output synchronization. vo _ stat indicates disabling or enabling the output module, which is equivalent to completing one output module reset after disabling.
Since the interrupt trigger of the synchronization timestamp module and the interrupt trigger of the output module are both based on the PPS signal, there may be a case where the time point of updating the synchronization timestamp coincides with the time point processed by the output module, and the compared synchronization timestamp is just at the critical point, as shown in fig. 5 below, which may cause an error in obtaining the corresponding relationship between the frequency division interrupt trigger time and the output interrupt trigger time. The delay function can be completed by adopting a high-precision timer of a Linux kernel, the precision can be microsecond, and the hrtimer _ func in fig. 4 is a timer processing function and is responsible for resetting the output function after delay.
The clock source of each node in the distributed system is independent, the crystal oscillator providing the clock has inherent frequency precision error, and the problem of clock frequency and phase deviation can be caused inevitably after long-time operation, so that the nodes are asynchronous. The input node mainly marks a synchronization timestamp taking a PPS signal as a reference on a video frame, and the PPS signal can ensure the same frequency and phase after being synchronized by IEEE1588, so that the clock frequency of the input node has no influence even if the clock frequency of the input node has deviation. However, if the frequency and phase of the output node are shifted, the output node will not process the video and the final video will not be synchronized.
In order to solve the problem, in a possible implementation manner, the output node is further configured to obtain a VS signal (vertical synchronization signal) of a video frame slice output by the output node, and adjust a clock frequency output by the adjustable crystal oscillator of the output node according to a phase deviation of the vertical synchronization signal and the second pulse interrupt signal, so that an error between the phase deviation and a preset target deviation is within a preset error range.
The VS signals in the video frame blocks can be utilized to return to the output node, then the DCXO on the output node is adjusted according to the phase deviation of the VS signals, and the aim of consistent clock frequency and phase among the output nodes is achieved through synchronizing the VS signals. The hardware principle of the Interface can be shown IN fig. 7, wherein IO represents an output/output Interface, CLK _ IN represents a clock signal Interface, HDMI represents a high-definition multimedia Interface, RGMII is fully called Reduced Gigabit Media Independent Interface IN english, and represents a Gigabit Media Independent Interface.
The VS signal, which may be extracted from the standard video signal, for different output node processors, or generated internally by the output node itself, is a signal associated with the system clock, and the offset of the VS signal reflects the offset of the system clock. The adjustable crystal oscillator defaults to input a clock signal with a specific frequency, such as 24MHz, and in fact, an error within +/-400 PPM may exist, for a clock with the frequency of 24MHz, 1PPM is 24Hz, and the frequency of +/-400 PPM deviation output by the crystal oscillator can be adjusted through a digital signal.
The preset target deviation can be an empirical value, or one phase deviation can be selected from the phase deviations of each output node as the preset target deviation, and the clock frequency output by the adjustable crystal oscillator is adjusted according to the phase deviation of the VS signal and the PPS interrupt signal, so that the effect of VS phase deviation is realized, and the VS signals of each output node can be synchronized. For example, in fig. 8, Frame time (Frame generation time, corresponding phase deviation, which is a time difference between the PPS interrupt signal and the vertical synchronization signal) counted on the output node is calibrated by using Target time (preset Target deviation) as a reference, that is, interval time (time interval) is corrected to be within a preset error range, so as to achieve synchronization. It is understood that the frequency-divided interrupt signal is obtained by frequency-dividing the PPS signal, and therefore the VS signal may also be compared with the frequency-divided interrupt signal, which is within the scope of the present application.
Because only the clock frequency of the DCXO can be adjusted and the clock phase cannot be directly controlled, generally, no fixed frequency can keep the phase stable, and the phase shifts due to the increase or decrease of the frequency, so that the adjustment of the crystal frequency is a repeated adjustment process, and the purpose of keeping the phase stable and shifting is achieved through frequency control.
In a possible implementation manner, the output node is specifically configured to calculate a correction time offset through a preset PID control algorithm according to the vertical synchronization signal and the PPS interrupt signal, and adjust the clock frequency output by the adjustable crystal oscillator of the output node according to the correction time offset.
In order to enable the phase deviation to converge to the preset target deviation quickly and effectively, the correction time offset may be calculated by a PID closed-loop control algorithm, for example, as shown in fig. 9, where the preset target deviation r is a target time, the output value y is a frame time, the deviation e is y-r is an interval time, and the correction time offset u to be corrected is obtained after the input PID closed-loop control algorithm module is subjected to proportional-integral-derivative calculation. Because how many offsets can be corrected by adjusting 1PPM of the crystal oscillator is in a fixed corresponding relation, the adjusting range of the PPM can be determined according to the offsets, so that the controlled object adjusts the phase of VS by configuring the PPM of the crystal oscillator, and a new output value obtained during the next PPS and VS processing enters the next PID again.
The operation of the VS signal synchronization function can be directly completed in a Linux kernel driver layer, the driver design is as shown in fig. 10 and fig. 11, and a timer is used for counting the time deviation of signals, so that the timer is reset firstly in PPS interruption, the PPS _ flag is set to be 1, the crystal oscillator is adjusted only according to the first VS signal after the PPS, and the PPS _ flag is set to be 0 again after the first VS interruption is completed.
In the embodiment of the application, synchronization timestamps recorded by each input node and each output node are synchronized by utilizing IEEE1588 synchronization, and the synchronization timestamp management is discretized, so that the synchronism of the output images of each output node in a distributed system is increased; the system frequency is configured through the adjustable crystal oscillator, the clock frequency synchronization of the output node system is kept, the deviation is prevented, the PID control algorithm can be used for rapidly and effectively converging to obtain the phase deviation, the VS signal phase adjustment is carried out, and therefore the synchronism of the output images of all the output nodes is further improved.
The embodiment of the application also provides a distributed video synchronous display method, which is applied to a distributed video synchronous display system, wherein the distributed video synchronous display system comprises at least one input node and a plurality of output nodes, and one input node is connected with at least two output nodes; referring to fig. 12, the method includes:
s101, the input node acquires a first synchronization timestamp when a current frequency division interruption is triggered aiming at each target video frame block of the same video frame to be sent currently, and sends each target video frame block carrying the first synchronization timestamp to a corresponding output node respectively, wherein the frequency of the frequency division interruption trigger is the same as the frame rate of a video, the video comprises the video frame, the corresponding output node is an output node connected with the input node, and one target video frame block is sent to one corresponding output node;
s102, when receiving the next output interruption trigger after the target video frame carrying the first synchronization timestamp is cut into blocks, the output node acquires a second synchronization timestamp when the current frequency division interruption trigger is carried out, and determines the difference value between the second synchronization timestamp and the first synchronization timestamp to obtain a target difference value; under the condition that the target difference value is equal to a preset difference value threshold value, the received target video frame is cut into blocks and displayed on a screen, wherein the preset difference value threshold value is an integral multiple of the time length represented by the frequency triggered by the interruption;
the clock synchronization is carried out between the at least one input node and the plurality of output nodes through a preset precise clock synchronization protocol, the frequency division interrupt trigger period of the input node and the frequency division interrupt trigger period of each output node are in the same frequency and the same phase, and the output interrupt trigger period of each output node is in the same frequency and the same phase.
In one possible embodiment, the method further comprises:
under the condition that the target difference value is larger than a preset difference value threshold value, the output node blocks and discards the received target video frame; and/or
And waiting for the next output interruption trigger under the condition that the target difference is smaller than a preset difference threshold.
In one possible embodiment, the method further comprises:
and when a preset delay time length passes from the moment of triggering the second pulse interruption, resetting the output function of the output node by the output node, wherein the preset delay time length is less than the time length represented by the frequency triggered by the frequency division interruption.
In one possible embodiment, the method further comprises:
the output node acquires a vertical synchronization signal of a video frame block output by the output node, and adjusts the clock frequency output by the adjustable crystal oscillator of the output node according to the phase deviation of the vertical synchronization signal and the second pulse interrupt signal, so that the error between the phase deviation and a preset target deviation is within a preset error range.
In one possible embodiment, the adjusting the clock frequency of the tunable crystal oscillator output of the output node according to the phase deviation of the vertical synchronization signal and the pulse per second interrupt signal includes:
and the output node calculates a correction time offset through a preset PID control algorithm according to the vertical synchronous signal and the pulse per second interrupt signal, and adjusts the clock frequency output by the adjustable crystal oscillator of the output node according to the correction time offset.
In a possible implementation manner, the system further includes a plurality of display screens, and the display screens correspond to the output nodes one to one, wherein the plurality of display screens form a spliced screen.
An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method for synchronously displaying videos in the present application is implemented.
In yet another embodiment provided by the present application, there is also provided a computer program product containing instructions which, when run on a computer, cause the computer to perform the video synchronization display method described in any of the above embodiments.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It should be noted that, in this document, the technical features in the various alternatives can be combined to form the scheme as long as the technical features are not contradictory, and the scheme is within the scope of the disclosure of the present application. Relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for embodiments of the method, the computer program product and the storage medium, since they are substantially similar to the system embodiments, the description is relatively simple, and in relation to the description, reference may be made to some of the description of the system embodiments.
The above description is only for the preferred embodiment of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims (13)
1. A distributed video synchronized display system, comprising:
the system comprises at least one input node and a plurality of output nodes, wherein one input node is connected with at least two output nodes;
the input node is configured to acquire a first synchronization timestamp when a frequency division interrupt is triggered for each target video frame slice of a same video frame to be currently sent, and send each target video frame slice carrying the first synchronization timestamp to a corresponding output node, respectively, where the frequency of the frequency division interrupt trigger is the same as the frame rate of a video, the video includes the video frame, the corresponding output node is an output node connected to the input node, and one target video frame slice is sent to one corresponding output node;
the output node is used for acquiring a second synchronization timestamp when the current frequency division interrupt is triggered when the next output interrupt trigger after the target video frame carrying the first synchronization timestamp is cut into blocks is received, and determining the difference value between the second synchronization timestamp and the first synchronization timestamp to obtain a target difference value; under the condition that the target difference value is equal to a preset difference value threshold value, the received target video frame is cut into blocks and displayed on a screen, wherein the preset difference value threshold value is an integral multiple of the time length represented by the frequency triggered by the frequency division interruption;
the clock synchronization is carried out between the at least one input node and the plurality of output nodes through a preset precise clock synchronization protocol, the frequency division interrupt trigger period of the input node and the frequency division interrupt trigger period of each output node are in the same frequency and phase, and the output interrupt trigger period of each output node is in the same frequency and phase.
2. The system according to claim 1, wherein said output node is further configured to discard the received target video frame block if the target difference is greater than a preset difference threshold; and/or waiting for the next output interruption trigger under the condition that the target difference is smaller than a preset difference threshold.
3. The system of claim 1, wherein the output node is further configured to reset the output function of the output node after a preset delay time period has elapsed from the time of the pulse-per-second interrupt trigger, wherein the preset delay time period is less than a time period represented by the frequency of the divided interrupt trigger.
4. The system according to claim 1, wherein the output node is further configured to obtain a vertical synchronization signal of a video frame slice output by the output node, and adjust a clock frequency output by the adjustable crystal oscillator of the output node according to a phase deviation of the vertical synchronization signal and the pulse per second interrupt signal, so that an error between the phase deviation and a preset target deviation is within a preset error range.
5. The system according to claim 4, wherein the output node is specifically configured to calculate a correction time offset by using a preset PID control algorithm according to the vertical synchronization signal and the pulse per second interrupt signal, and adjust the clock frequency output by the tunable crystal oscillator of the output node according to the correction time offset.
6. The system according to any one of claims 1-5, further comprising a plurality of display screens, the display screens corresponding to the output nodes one-to-one, wherein the plurality of display screens form a tiled screen.
7. A distributed video synchronous display method is characterized in that the method is applied to a distributed video synchronous display system, the distributed video synchronous display system comprises at least one input node and a plurality of output nodes, wherein one input node is connected with at least two output nodes;
the method comprises the following steps:
the input node acquires a first synchronization timestamp when a current frequency division interruption is triggered aiming at each target video frame block of the same video frame to be sent currently, and sends each target video frame block carrying the first synchronization timestamp to a corresponding output node respectively, wherein the frequency of the frequency division interruption trigger is the same as the frame rate of a video, the video comprises the video frame, the corresponding output node is an output node connected with the input node, and one target video frame block is sent to one corresponding output node;
the output node acquires a second synchronization timestamp when the current frequency division interruption is triggered when receiving the next output interruption trigger after the target video frame carrying the first synchronization timestamp is cut into blocks, and determines the difference value between the second synchronization timestamp and the first synchronization timestamp to obtain a target difference value; under the condition that the target difference value is equal to a preset difference value threshold value, the received target video frame is cut into blocks and displayed on a screen, wherein the preset difference value threshold value is an integral multiple of the time length represented by the frequency triggered by the frequency division interruption;
the clock synchronization is carried out between the at least one input node and the plurality of output nodes through a preset precise clock synchronization protocol, the frequency division interrupt trigger period of the input node and the frequency division interrupt trigger period of each output node are in the same frequency and phase, and the output interrupt trigger period of each output node is in the same frequency and phase.
8. The method of claim 7, further comprising:
under the condition that the target difference value is larger than a preset difference value threshold value, the output node blocks and discards the received target video frame; and/or
And waiting for the next output interruption trigger under the condition that the target difference is smaller than a preset difference threshold.
9. The method of claim 7, further comprising:
and when a preset delay time length passes from the moment of triggering the second pulse interruption, resetting the output function of the output node by the output node, wherein the preset delay time length is less than the time length represented by the frequency triggered by the frequency division interruption.
10. The method of claim 7, further comprising:
the output node acquires a vertical synchronization signal of a video frame block output by the output node, and adjusts the clock frequency output by the adjustable crystal oscillator of the output node according to the phase deviation of the vertical synchronization signal and the second pulse interrupt signal, so that the error between the phase deviation and a preset target deviation is within a preset error range.
11. The method of claim 10, wherein adjusting the clock frequency of the tunable crystal output of the output node according to the phase offset of the vertical synchronization signal and the pulse-per-second interrupt signal comprises:
and the output node calculates a correction time offset through a preset PID control algorithm according to the vertical synchronous signal and the pulse per second interrupt signal, and adjusts the clock frequency output by the adjustable crystal oscillator of the output node according to the correction time offset.
12. The method of any one of claims 7-11, wherein the system further comprises a plurality of display screens, the display screens corresponding to the output nodes one-to-one, wherein the plurality of display screens form a tiled screen.
13. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, implements the distributed video synchronous display method according to any one of claims 7 to 12.
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| CN115065861A (en) * | 2022-02-28 | 2022-09-16 | 山东中维世纪科技股份有限公司 | Video synchronous splicing display method and system for distributed decoder |
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