CN115459871A - Time synchronization method, network device and storage medium - Google Patents
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Abstract
The embodiment of the invention provides a time synchronization method, network equipment and a storage medium, and belongs to the technical field of communication. The method comprises the following steps: acquiring a time deviation value between a slave clock and a master clock; performing deviation compensation on the time deviation value to obtain the time deviation value after deviation compensation; and adjusting the time of the slave clock according to the time deviation value after deviation compensation so as to realize time synchronization of the slave clock and the master clock. According to the technical scheme of the embodiment of the invention, the time deviation value between the slave clock and the master clock is subjected to deviation compensation, so that the time synchronization precision of the slave clock is effectively improved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a time synchronization method, a network device, and a storage medium.
Background
With the development of communication technology, data transmission speed is faster and faster, and the requirement on time synchronization precision is higher and higher. In a distributed network, the time synchronization is mainly realized by adopting the precision clock synchronization protocol standard IEEE1588 of a network measurement and control system. In the process of realizing the time synchronization of the slave clock and the master clock according to the IEEE1588 protocol standard, the uplink transmission delay is required to be equal to the downlink transmission delay; however, in an actual environment, due to the fact that the network is not completely symmetrical, the uplink transmission delay is not completely equal to the downlink transmission delay, the calculated time deviation value is not accurate enough, and the time synchronization precision of the slave clock is reduced.
Therefore, how to improve the time synchronization accuracy of the slave clock becomes a problem to be solved urgently.
Disclosure of Invention
Embodiments of the present invention provide a time synchronization method, a network device, and a storage medium, which effectively improve the time synchronization accuracy of a slave clock by performing offset compensation on a time offset value between the slave clock and a master clock.
In a first aspect, an embodiment of the present invention provides a time synchronization method, including:
acquiring a time deviation value between a slave clock and a master clock; performing deviation compensation on the time deviation value to obtain the time deviation value after deviation compensation; and adjusting the time of the slave clock according to the time deviation value after deviation compensation so as to realize time synchronization between the slave clock and the master clock.
In a second aspect, an embodiment of the present invention further provides a network device, where the network device includes a slave clock, a processor, a memory, a computer program stored on the memory and executable by the processor, and a data bus for implementing connection communication between the processor and the memory, where the slave clock is used for time synchronization with a master clock in a master controller, and the computer program, when executed by the processor, implements the time synchronization method as described above.
In a third aspect, an embodiment of the present invention further provides a storage medium for a computer-readable storage, where the storage medium stores one or more programs, and the one or more programs are executable by one or more processors to implement any of the steps of the time synchronization method provided in the present specification.
The embodiment of the invention provides a time synchronization method, network equipment and a storage medium, wherein a time deviation value between a slave clock and a master clock is obtained, and deviation compensation is carried out on the time deviation value, so that the time deviation value after deviation compensation can be obtained, and the accuracy of the time deviation value is improved; the time of the slave clock is adjusted according to the time deviation value after the deviation compensation, so that the time synchronization of the slave clock and the master clock can be realized, and the time synchronization precision of the slave clock is effectively improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a time synchronization system according to an embodiment of the present invention;
fig. 2 is a schematic block diagram of a network device according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart diagram of a time synchronization method provided by an embodiment of the present invention;
FIG. 4 is a schematic flow chart diagram illustrating the substeps of determining an actual time bias value provided by an embodiment of the present invention;
fig. 5 is a schematic diagram of time synchronization between a slave clock and a master clock according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The flowcharts shown in the figures are illustrative only and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution order may be changed according to the actual situation.
It is to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Embodiments of the present invention provide a time synchronization method, a network device, and a storage medium, where the time synchronization method may be applied to a network device, and may effectively improve time synchronization accuracy of a slave clock by performing offset compensation on a time offset value between the slave clock and a master clock.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a time synchronization system according to an embodiment of the present invention. As shown in fig. 1, the time synchronization system includes a master clock and at least one slave clock. Wherein each slave clock can be time-synchronized with the master clock.
Illustratively, the slave clock may be a clock in the network device, and the master clock may be a clock in the master controller.
Illustratively, the slave clock and the master clock may be clocks in the same network device.
It should be noted that the network devices may include, but are not limited to, devices such as repeaters, bridges, routers, gateways, firewalls, and switches. In a distributed network, the slave clock in the network device may be periodically time-synchronized with the master clock in the master controller (master controller) to keep the time of the slave clock as consistent as possible with the time of the master clock.
In some embodiments, the network device may obtain a time offset value between the slave clock and the master clock; performing deviation compensation on the time deviation value to obtain a time deviation value after deviation compensation; and adjusting the time of the slave clock according to the time deviation value after deviation compensation so as to realize time synchronization of the slave clock and the master clock.
Referring to fig. 2, fig. 2 is a schematic block diagram of a network device according to an embodiment of the present invention.
Referring to fig. 2, the network device 1000 may include a processor 1001, a memory 1002, and a slave clock 1003, wherein the processor 1001 and the memory 1002 may be connected by a bus, such as any suitable bus, for example, an I2C (Inter-integrated Circuit) bus.
The memory 1002 may include, among other things, non-volatile storage media and internal memory. The non-volatile storage medium may store an operating system and a computer program. The computer program includes program instructions that, when executed, cause a processor to perform any of the time synchronization methods.
The slave clock 1003 is used for time synchronization with the master clock in the master controller.
The processor 1001 is used to provide computing and control capabilities, among other things, to support the operation of the overall network device 1000.
In an embodiment, the processor 1001 is configured to run a computer program stored in the memory 1002 and when executing the computer program, to implement the following steps:
acquiring a time deviation value between a slave clock and a master clock; performing deviation compensation on the time deviation value to obtain the time deviation value after deviation compensation; and adjusting the time of the slave clock according to the time deviation value after deviation compensation so as to realize time synchronization of the slave clock and the master clock.
In one embodiment, the processor 1001 is further configured to implement:
acquiring transmission delay between the slave clock and the master clock; carrying out delay compensation on the transmission delay to obtain the transmission delay after delay compensation;
in one embodiment, the processor 1001 is configured to, when performing bias compensation on the time bias value to obtain the time bias value after the bias compensation, perform:
determining a deviation compensation value corresponding to the time deviation value based on the transmission delay after delay compensation; and carrying out deviation compensation on the time deviation value according to the deviation compensation value to obtain the time deviation value after deviation compensation.
In one embodiment, when implementing the delay compensation for the transmission delay, the processor 1001 is configured to implement:
and determining a delay compensation value corresponding to the transmission delay, and performing delay compensation on the transmission delay according to the delay compensation value.
In one embodiment, before implementing the determining of the delay compensation value corresponding to the transmission delay, the processor 1001 is further configured to implement:
and determining the actual time deviation value when the slave clock is time-synchronized with the slave clock in the same time synchronization period.
In one embodiment, the processor 1001 is further configured to determine a delay compensation value corresponding to the transmission delay, and further configured to:
and determining the delay compensation value according to the time deviation value and the actual time deviation value.
In one embodiment, processor 1001, in enabling determining an actual time offset value when the slave clock is time synchronized with the slave clock, is configured to enable:
determining the number of interaction times when the slave clock and the master clock perform time synchronization in the time synchronization period; determining at least one first frequency deviation value corresponding to the slave clock according to the sending time point and the receiving time point corresponding to each two groups of adjacent synchronous messages in the time synchronization period, wherein the first frequency deviation value is a frequency deviation value when the slave clock and the master clock perform time synchronization in the time synchronization period; determining at least one first time deviation value corresponding to the slave clock based on a precision time protocol, wherein the first time deviation value is a time deviation value when the slave clock and the master clock are time-synchronized in the time synchronization period; and determining the actual time deviation value according to all the first frequency deviation values, the interaction times and all the first time deviation values.
In one embodiment, when the processor 1001 determines the offset compensation value corresponding to the time offset value based on the transmission delay compensated by the delay compensation, it is configured to:
controlling the slave clock and the master clock to carry out time synchronization according to the transmission delay after delay compensation, and determining corresponding second frequency deviation values of the slave clock in every two adjacent time synchronization periods; and determining the deviation compensation value according to all the second frequency deviation values and preset deviation compensation times.
In one embodiment, the two adjacent time synchronization periods comprise a first time synchronization period and a second time synchronization period; the processor 1001, in enabling determining the corresponding second frequency deviation values of the slave clock in each two adjacent time synchronization periods, is configured to enable:
determining a corresponding first actual time deviation value of the slave clock in the first time synchronization period; determining a second actual time deviation value corresponding to the slave clock in the second time synchronization period; and determining the second frequency offset value according to the first actual time offset value and the second actual time offset value.
In one embodiment, the processor 1001, when determining the deviation compensation value according to all of the second frequency deviation values and a preset deviation compensation number, is configured to:
determining a frequency deviation total value corresponding to all the second frequency deviation values; determining a corresponding frequency deviation average value according to the deviation compensation times and the frequency deviation total value; and determining the deviation compensation value according to the frequency deviation average value.
The Processor 1001 may be a Central Processing Unit (CPU), and may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments and features of the embodiments described below can be combined with each other without conflict.
Referring to fig. 3, fig. 3 is a schematic flowchart of a time synchronization method according to an embodiment of the present invention. The time synchronization method can be applied to network equipment, realizes deviation compensation of the time deviation value between the slave clock and the master clock, and can effectively improve the time synchronization precision of the slave clock. The time synchronization method includes steps S10 to S30.
And step S10, acquiring a time deviation value between the slave clock and the master clock.
For example, the time synchronization method provided by the embodiment of the present invention may be applied to time synchronization scenarios such as a distributed ethernet system clock synchronization system, an IEEE1588 protocol clock synchronization system, ultra-high precision clock synchronization, and base station clock synchronization, and the like, so as to implement deviation compensation on a time deviation value of a slave clock when the slave clock and a master clock perform time synchronization, so as to improve the time synchronization precision of the slave clock.
It should be noted that, the time synchronization between the slave clock and the master clock can be realized by adopting the precision clock synchronization protocol standard IEEE1588 of the network measurement and control system. The IEEE1588 Protocol standard basically keeps all slave clocks and master clocks synchronized in a distributed network, and defines a Precision Time Protocol (PTP) to implement Time synchronization.
Illustratively, the time synchronization process between the slave clock and the master clock, based on the precision time protocol PTP, may include a skew measurement phase and a delay measurement phase. The deviation measuring stage is to measure the time deviation amount between the master clock and the slave clock and eliminate the time deviation amount on the slave clock. And the delay measurement stage is used for determining the transmission delay of the message between the master clock and the slave clock. It is understood that the time offset refers to the time offset that exists when the master clock and the slave clock are time synchronized. The time offset is denoted as offset. The transmission delay refers to a delay time generated by the transmission of the message in the network, and is denoted by delay.
For example, the time offset amount offset may include a downlink time offset value offset ↓ and an uplink time offset value offset ℃ ↓ where the downlink time offset value offset ↓ represents a time offset value between the slave clock and the master clock when the master clock sends the synchronization message to the slave clock; the uplink time offset value offset ≈ ≈ represents a time offset value between the slave clock and the master clock when the slave clock transmits the delay request message to the master clock.
Illustratively, the transmission delay includes downlink transmission delay ↓ and uplink transmission delay ↓. The downlink transmission delay ↓ refers to the delay time of network transmission between the master clock and the slave clock; the upstream transmission delay ↓ refers to a delay time of network transmission between the slave clock and the master clock.
In some embodiments, the time synchronization method provided in the embodiments of the present invention may further include: and acquiring the transmission delay between the slave clock and the master clock. It should be noted that the transmission delay may be obtained when the time offset value between the slave clock and the master clock is obtained.
Acquiring a time offset value between the slave clock and the master clock may include: based on a precise time protocol, acquiring synchronous message sending time, synchronous message receiving time, delay request message sending time and delay request message receiving time when a slave clock and a master clock are synchronously interacted; and if the uplink time deviation value is equal to the downlink time deviation value and the uplink transmission delay is equal to the downlink transmission delay, determining the time deviation value according to the synchronous message sending time, the synchronous message receiving time, the delay request message sending time and the delay request message receiving time.
The obtaining of the transmission delay between the slave clock and the master clock may include: and if the uplink time deviation value is equal to the downlink time deviation value and the uplink transmission delay is equal to the downlink transmission delay, determining the transmission delay according to the synchronous message sending time, the synchronous message receiving time, the delay request message sending time and the delay request message receiving time.
Illustratively, the time offset value between the slave clock and the master clock and the propagation delay may be obtained based on a precision time protocol. For example, in the biasIn the phase of difference measurement, the master clock can send a synchronous message to the slave clock at intervals and record the sending time of the synchronous message as t 1 (ii) a When the slave clock receives the synchronous message, the receiving time of the synchronous message is recorded as t 2 . Wherein, the sending time t of the synchronous message is 1 The slave clock may be sent by the master clock via a follow message. In the delay measurement stage, the slave clock sends a delay request message to the master clock, and records the current time t while sending the message 3 Wherein, t 3 The time is the time of delaying the transmission of the request message. When the master clock receives the delay request message, recording the receiving time of the delay request message as t 4 And receiving the delay request message by the delay response message for a time t 4 To the slave clock.
Illustratively, according to the precision time protocol, the relationship between the time offset value and the transmission delay can be derived as follows:
t 2 -t 1 ＝delay↓+offset↓
t 4 -t 3 ＝delay↑-offset↑
in some embodiments, when the downlink time offset value offset ↓ is equal to the uplink time offset value offset ↓ and the uplink transmission delay time delay ↓ is equal to the downlink transmission delay time delay ↓, the time offset value offset and the transmission delay are as follows:
delay＝[(t 2 -t 1 )+(t 4 -t 3 )]/2
offset＝[(t 2 -t 1 )-(t 4 -t 3 )]/2
in some embodiments, to ensure the validity of the data, the time offset value and the transmission delay may be de-extremized or averaged when the time offset value and the transmission delay between the slave clock and the master clock are obtained.
By acquiring the transmission delay and the time deviation value between the slave clock and the master clock, delay compensation can be carried out on the transmission delay and deviation compensation can be carried out on the time deviation value subsequently, so that the synchronization error between the slave clock and the master clock is reduced, and the time synchronization precision of the slave clock is effectively improved.
And S20, performing deviation compensation on the time deviation value to obtain the time deviation value after deviation compensation.
It should be noted that, the condition of the obtained time offset value offset and the transmission delay is that the downlink time offset value offset ↓ is equal to the uplink time offset value offset ↓ ] and the downlink transmission delay ↓ ] is equal to the uplink transmission delay ℃ ↓. However, in an actual environment, due to the asymmetry of network transmission, for example, the downlink transmission delay ↓ and the uplink transmission delay ↓ ] may be affected by the intermediate device policy, the network load, the asymmetry of the transceiving path, and the like, therefore, the downlink transmission delay ↓ is not equal to the uplink transmission delay ↓. Further, the downlink time offset value offset ↓ is not equal to the uplink time offset value offset ↓ due to the influence of the state characteristic of the clock, for example, the state characteristic of the crystal type, the frequency stability, the temperature characteristic, and the like of the clock. In the embodiment of the invention, the transmission delay and the time deviation value need to be compensated so as to improve the time synchronization precision of the slave clock. It should be noted that the delay compensation is one of the processes of compensating the deviation of the time deviation value.
For example, the delay compensation may be performed on the transmission delay first to obtain the transmission delay after the delay compensation; and then, performing deviation compensation on the time deviation value based on the transmission delay after the delay compensation to obtain the time deviation value after the deviation compensation. Therefore, the time of the slave clock can be adjusted according to the time deviation value after deviation compensation, so that the time synchronization of the slave clock and the master clock is realized, and the time synchronization precision of the slave clock is effectively improved. In the embodiment of the present invention, how to perform delay compensation on the transmission delay and perform offset compensation on the time offset value will be described in detail.
It will be appreciated that the delay compensation for the transmission delay and the offset compensation for the time offset value are both performed in order to reduce the synchronization error between the slave clock and the master clock. For example, delay compensation and skew compensation may be performed periodically to gradually reduce the synchronization error between the slave clock and the master clock.
In some embodiments, after the transmission delay between the slave clock and the master clock is obtained, delay compensation may be performed on the transmission delay, so as to obtain the delay-compensated transmission delay. The performing delay compensation on the transmission delay may include: and determining a delay compensation value corresponding to the transmission delay, and performing delay compensation on the transmission delay according to the delay compensation value.
For example, before determining the delay compensation value corresponding to the transmission delay, the actual time deviation value of the slave clock when time-synchronizing with the slave clock can also be determined in the same time synchronization period. It should be noted that, within a time synchronization period, multiple interactions of synchronization messages may be performed between the slave clock and the master clock; and calculating the current time deviation value during each synchronous message interaction. The actual time deviation value is obtained by averaging a plurality of time deviation values generated in the same time synchronization period. The synchronous message is generated in the deviation measurement stage and the delay measurement stage.
Referring to fig. 4, fig. 4 is a schematic flowchart illustrating a sub-step of determining an actual time offset value according to an embodiment of the present invention, which may specifically include the following steps S201 to S204.
Step S201, determining the number of interactions when the slave clock and the master clock perform time synchronization in the time synchronization period.
For example, the number of interactions when the slave clock is time synchronized with the master clock in the same time synchronization period may be determined. Wherein the number of interactions may be denoted as n. The number of interactions n may be determined according to actual conditions, for example, according to clock frequencies of the slave clock and the master clock, and specific values are not limited herein.
Step S202, determining at least one first frequency deviation value corresponding to the slave clock according to the sending time and the receiving time corresponding to each two groups of adjacent synchronization packets in the time synchronization period, where the first frequency deviation value is a frequency deviation value when the slave clock and the master clock perform time synchronization in the time synchronization period.
It should be noted that each two sets of phasesThe adjacent synchronization messages may include the ith synchronization message and the (i-1) th synchronization message within the time synchronization period. Wherein, each time of time synchronization includes a deviation measurement stage and a delay measurement stage. Thus, the transmission time includes the sync message transmission time t 1 And time t of sending delay request message 3 (ii) a The receiving time includes recording the receiving time t of the synchronous message 2 And the receiving time t of the delay request message 4 。
Illustratively, when the ith synchronization packet is interacted, according to the precision time protocol PTP, the relationship between the time offset value and the transmission delay may be obtained as follows:
because the interaction time of the two adjacent synchronous messages is extremely short, the downlink transmission delay ↓andthe uplink transmission delay ↓ are invariable, so the downlink transmission delay ↓ and the uplink transmission delay Δ ↓ in each two groups of adjacent synchronous messages have the following relationship:
delay i-1 ↓＝delay i ↓
delay i-1 ↑＝delay i ↑
accordingly, at least one first frequency deviation value corresponding to the slave clock may be determined as follows:
in the formula,. DELTA.t i The frequency offset value is indicated.
At least one first frequency deviation value corresponding to the slave clock can be determined according to the sending time and the receiving time corresponding to each two groups of adjacent synchronous messages in the time synchronization period.
Step S203, determining at least one first time offset value corresponding to the slave clock based on a precision time protocol, where the first time offset value is a time offset value when the slave clock and the master clock perform time synchronization in the time synchronization period.
Illustratively, based on the precision time protocol, at least one first time offset value corresponding to the slave clock is determined, wherein the first time offset value can be expressed as an offset i . First time offset value offset i Can be obtained from the following equation:
offset i ＝T d +Δt i +θ i
in the formula, offset i Representing the time deviation value of the ith message interaction; theta i Indicating other types of accidental errors; t is d Representing the actual time offset value within a time synchronization period.
Step S204, determining the actual time deviation value according to all the first frequency deviation values, the interaction times and all the first time deviation values.
Note that θ is due to an accidental error i Occasional error theta with increasing number of interactions i Is close to 0, and therefore the accidental error theta i Can be ignored.
Illustratively, the actual time offset value is determined based on all of the first frequency offset values, the number of interactions, and all of the first time offset values, as follows:
by the formula, the actual time deviation value T can be calculated d 。
According to all the first frequency deviation values, the interaction times and all the first time deviation values, the actual time deviation value corresponding to the slave clock in the same time synchronization period can be accurately determined.
In an embodiment of the present invention, a slave is determinedActual time deviation value T when time synchronization is carried out between clock and slave clock d Then, the actual time deviation value T can be used d And determining a delay compensation value corresponding to the transmission delay.
In some embodiments, determining a delay compensation value corresponding to the transmission delay may include: and determining a delay compensation value according to the time deviation value and the actual time deviation value.
Illustratively, the delay compensation value may be denoted as C 1 Delay compensation value C 1 Can be calculated from the following formula:
C 1 ＝offset-T d
in the formula, offset represents a time offset value; delay compensation value C 1 The unit of (d) may be ns.
Illustratively, the compensation value C is based on the delay time 1 And carrying out delay compensation on the transmission delay to obtain the transmission delay after the delay compensation. The delay compensated transmission delay may be represented as Tdelay, as follows:
Tdelay＝delay+C 1
according to the delay compensation value C 1 After delay compensation for the transmission delay, the time offset between the slave clock and the master clock can be denoted as Toffset. It will be appreciated that delay compensation refers to reducing the synchronization error between the slave and master clocks by C 1 (ii) a After the delay compensation, the time offset value Toffset is equal to the actual time offset value T d 。
By carrying out delay compensation on the transmission delay, the precision of the transmission delay can be effectively improved, and the time synchronization precision of the slave clock is further improved.
In the embodiment of the present invention, after the delay compensation is performed on the transmission delay, in order to further improve the time synchronization precision of the slave clock, the deviation compensation is also performed on the time deviation value.
In some embodiments, the offset compensation of the time-offset value may include: determining a deviation compensation value corresponding to the time deviation value based on the transmission delay after the delay compensation; and carrying out deviation compensation on the time deviation value according to the deviation compensation value to obtain the time deviation value after deviation compensation.
It should be noted that after performing delay compensation on the transmission delay, it may be determined that the uplink transmission delay is equal to the downlink transmission delay. Therefore, in the embodiment of the invention, the deviation compensation value corresponding to the time deviation value is determined under the condition that the transmission delay is kept unchanged.
In some embodiments, determining a deviation compensation value corresponding to the time deviation value based on the delay compensated transmission delay may include: controlling the slave clock and the master clock to carry out time synchronization according to the transmission delay after the delay compensation, and determining corresponding second frequency deviation values of the slave clock in every two adjacent time synchronization periods; and determining a deviation compensation value according to all the second frequency deviation values and the preset deviation compensation times.
Since the frequency stability of the crystal oscillator of the clock affects the frequency of the clock, it is necessary to consider the influence of the frequency deviation value of the slave clock on the synchronization error. By determining the deviation compensation value according to the frequency deviation value, the influence of the frequency stability of the crystal oscillator on the time synchronization can be eliminated, and the time synchronization precision of the slave clock can be improved.
Illustratively, the slave clock and the master clock may be controlled to perform time synchronization for multiple times based on the delay compensated transmission delay, and the actual time deviation value within the same time synchronization period may be calculated. Since the actual time offset value is Toffset after the time delay compensation, the actual time offset value calculated during the j-th time synchronization is Toffset j 。
Illustratively, the two adjacent time synchronization periods include a first time synchronization period and a second time synchronization period.
For example, when determining the corresponding second frequency deviation values of the slave clock in every two adjacent time synchronization periods, the corresponding first actual time deviation values of the slave clock in the first time synchronization period may be determined; then, determining a second actual time deviation value corresponding to the slave clock in a second time synchronization period; and determining a second frequency offset value according to the first actual time offset value and the second actual time offset value.
For example, in the first time synchronization period, the calculated first actual time deviation value is Toffset j-1 (ii) a In a second time synchronization period, the calculated second actual time deviation value is Toffset j . For a detailed description of determining the actual time deviation value when the slave clock performs time synchronization with the slave clock in the above embodiment, details of the calculation of the first actual time deviation value and the second actual time deviation value are not described herein.
In some embodiments, to ensure the validity of the calculated actual time deviation values, extreme values or an average value may be removed from the calculated actual time deviation values when calculating the actual time deviation values in the same time synchronization period.
Illustratively, the second frequency deviation value is determined by the following equation:
ΔO j ＝Toffset j -Toffset j-1
in the formula,. DELTA.O j And indicating a second frequency deviation value corresponding to the j time synchronization. In the implementation of the present invention, the second frequency offset values corresponding to the time synchronization periods can be calculated to obtain a plurality of second frequency offset values.
In some embodiments, determining the deviation compensation value according to all the second frequency deviation values and the preset deviation compensation times may include: determining the frequency deviation total value corresponding to all the second frequency deviation values; determining a corresponding frequency deviation average value according to the deviation compensation times and the frequency deviation total value; and determining a deviation compensation value according to the average value of the frequency deviation.
Illustratively, the preset deviation compensation times are denoted by m, and the deviation compensation times m can be determined according to practical situations, and specific values are not limited herein.
In the embodiment of the present invention, the offset compensation value may be determined by the following equation:
in the formula (I), the compound is shown in the specification,
representing the total frequency deviation value corresponding to all the second frequency deviation values;
representing the mean value of the frequency deviation, i.e. deviation compensation value C 2 . Wherein the deviation compensation value C 2 The unit of (d) may be ns.
After the deviation compensation value corresponding to the time deviation value is determined, deviation compensation can be performed on the time deviation value according to the deviation compensation value, and the time deviation value after deviation compensation is obtained. For example, the offset compensated time offset value is determined from the sum of the offset compensation value and the real time offset value. It will be appreciated that after the delay compensation, the current time offset value is equal to the true time offset value.
For example, the offset-compensated time offset value may be expressed as offset', which is obtained by the following equation:
offset′＝Toffset+C 2
in the formula, toffset denotes a real time deviation value.
And performing deviation compensation on the time deviation value according to the deviation compensation value by determining the deviation compensation value corresponding to the time deviation value to obtain the time deviation value after the deviation compensation.
And S30, adjusting the time of the slave clock according to the time deviation value after deviation compensation so as to realize time synchronization between the slave clock and the master clock.
For example, after the offset-compensated time offset value offset 'is obtained, the time of the slave clock may be adjusted according to the time offset value offset'. For example, the time of the slave clock is increased by C 2 So that the synchronization error between the slave clock and the master clock is reduced by C 2 。
The time of the slave clock is adjusted according to the time deviation value after deviation compensation, so that the time synchronization of the slave clock and the master clock is realized, the synchronization error between the slave clock and the master clock can be reduced, and the time synchronization precision of the slave clock is effectively improved.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a slave clock and a master clock performing time synchronization according to an embodiment of the present invention. As shown in fig. 5, at time T1, the synchronization error between the slave clock and the master clock is E; at time T2, e.g. after delay compensation, the synchronization error between the slave and master clocks is E-C 1 (ii) a At time T3, e.g. after skew compensation, the synchronization error between the slave and master clocks is E-C 1 -C 2 . Since the synchronization error between the slave clock and the master clock is gradually reduced, the time synchronization accuracy of the slave clock can be improved.
In the embodiment of the invention, after the time of the slave clock is adjusted according to the time deviation value after deviation compensation, new delay compensation C can be periodically calculated 1 And offset compensation C 2 And compensating C according to the new delay 1 And offset compensation C 2 The time of the slave clock is adjusted. So that the time synchronization accuracy of the slave clock can be maintained.
By acquiring the transmission delay and the time deviation value between the slave clock and the master clock, the time synchronization method, the network device and the storage medium provided by the embodiment can perform delay compensation on the transmission delay and perform deviation compensation on the time deviation value in the following process, so as to reduce the synchronization error between the slave clock and the master clock, and effectively improve the time synchronization precision of the slave clock; determining at least one first frequency deviation value corresponding to the slave clock according to the sending time and the receiving time corresponding to each two groups of adjacent synchronous messages in the time synchronization period; according to all the first frequency deviation values, the interaction times and all the first time deviation values, the actual time deviation value corresponding to the slave clock in the same time synchronization period can be accurately determined; by carrying out delay compensation on the transmission delay, the precision of the transmission delay can be effectively improved, and the time synchronization precision of the slave clock is further improved; the influence of the frequency stability of the crystal oscillator on the time synchronization can be eliminated by determining the deviation compensation value according to the frequency deviation value, so that the time synchronization precision of the slave clock can be improved; by determining a deviation compensation value corresponding to the time deviation value, performing deviation compensation on the time deviation value according to the deviation compensation value to obtain a time deviation value after deviation compensation; the time of the slave clock is adjusted according to the time deviation value after deviation compensation, so that the time synchronization of the slave clock and the master clock is realized, the synchronization error between the slave clock and the master clock can be reduced, and the time synchronization precision of the slave clock is effectively improved.
Embodiments of the present invention also provide a storage medium for a computer-readable storage, where the storage medium stores one or more programs, and the one or more programs are executable by one or more processors to implement the steps of any one of the time synchronization methods provided in the description of the embodiments of the present invention.
For example, the program is loaded by a processor and may perform the following steps:
acquiring a time deviation value between a slave clock and a master clock; performing deviation compensation on the time deviation value to obtain the time deviation value after deviation compensation; and adjusting the time of the slave clock according to the time deviation value after deviation compensation so as to realize time synchronization between the slave clock and the master clock.
The storage medium may be an internal storage unit of the network device described in the foregoing embodiment, for example, a hard disk or a memory of the network device. The storage medium may also be an external storage device of the network device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, provided on the network device.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware embodiment, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
It should be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments. While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method of time synchronization, the method comprising:
acquiring a time deviation value between a slave clock and a master clock;
performing deviation compensation on the time deviation value to obtain the time deviation value after deviation compensation;
and adjusting the time of the slave clock according to the time deviation value after deviation compensation so as to realize time synchronization between the slave clock and the master clock.
2. The method for time synchronization of claim 1, further comprising:
acquiring transmission delay between the slave clock and the master clock;
carrying out delay compensation on the transmission delay to obtain the transmission delay after delay compensation;
the performing deviation compensation on the time deviation value to obtain the time deviation value after deviation compensation includes:
determining a deviation compensation value corresponding to the time deviation value based on the transmission delay after delay compensation;
and carrying out deviation compensation on the time deviation value according to the deviation compensation value to obtain the time deviation value after deviation compensation.
3. The method of claim 2, wherein the compensating for the transmission delay comprises:
and determining a delay compensation value corresponding to the transmission delay, and performing delay compensation on the transmission delay according to the delay compensation value.
4. The method according to claim 3, wherein before determining the delay compensation value corresponding to the transmission delay, the method further comprises:
determining an actual time deviation value when the slave clock and the slave clock are in time synchronization in the same time synchronization period;
the determining a delay compensation value corresponding to the transmission delay includes:
and determining the delay compensation value according to the time deviation value and the actual time deviation value.
5. The method according to claim 4, wherein the determining the actual time deviation value when the slave clock is time-synchronized with the slave clock comprises:
determining the number of interaction times when the slave clock and the master clock perform time synchronization in the time synchronization period;
determining at least one first frequency deviation value corresponding to the slave clock according to the sending time point and the receiving time point corresponding to each two groups of adjacent synchronous messages in the time synchronization period, wherein the first frequency deviation value is a frequency deviation value when the slave clock and the master clock perform time synchronization in the time synchronization period;
determining at least one first time deviation value corresponding to the slave clock based on a precision time protocol, wherein the first time deviation value is a time deviation value when the slave clock and the master clock are time-synchronized in the time synchronization period;
and determining the actual time deviation value according to all the first frequency deviation values, the interaction times and all the first time deviation values.
6. The method according to claim 2, wherein the determining a deviation compensation value corresponding to the time deviation value based on the transmission delay compensated by the delay compensation comprises:
controlling the slave clock and the master clock to carry out time synchronization according to the transmission delay after delay compensation, and determining corresponding second frequency deviation values of the slave clock in every two adjacent time synchronization periods;
and determining the deviation compensation value according to all the second frequency deviation values and preset deviation compensation times.
7. The time synchronization method according to claim 6, wherein the two adjacent time synchronization periods comprise a first time synchronization period and a second time synchronization period;
the determining a corresponding second frequency deviation value of the slave clock in every two adjacent time synchronization periods comprises:
determining a corresponding first actual time deviation value of the slave clock in the first time synchronization period;
determining a second actual time deviation value corresponding to the slave clock in the second time synchronization period;
determining the second frequency offset value based on the first actual time offset value and the second actual time offset value.
8. The method of claim 6, wherein the determining the deviation compensation value according to all the second frequency deviation values and a preset deviation compensation number comprises:
determining a frequency deviation total value corresponding to all the second frequency deviation values;
determining a corresponding frequency deviation average value according to the deviation compensation times and the frequency deviation total value;
and determining the deviation compensation value according to the frequency deviation average value.
9. A network device comprising a processor, a memory, a slave clock;
the memory is used for storing programs;
the slave clock is used for carrying out time synchronization with a master clock in a master control machine;
the processor for executing the program and implementing the time synchronization method according to any one of claims 1 to 8 when executing the program.
10. A storage medium for readable storage, wherein the storage medium stores one or more programs, the one or more programs being executable by one or more processors to implement the time synchronization method of any one of claims 1 to 8.
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| CN202110640535.5A CN115459871A (en) | 2021-06-08 | 2021-06-08 | Time synchronization method, network device and storage medium |
| PCT/CN2022/070570 WO2022257447A1 (en) | 2021-06-08 | 2022-01-06 | Time synchronization method, network device, and storage medium |
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| CN115996459B (en) * | 2023-03-23 | 2023-06-30 | 西安羚控电子科技有限公司 | Unmanned aerial vehicle cluster clock synchronization method |
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| CN106533600B (en) * | 2016-10-14 | 2018-09-28 | 瑞斯康达科技发展股份有限公司 | A kind of clock synchronizing method and equipment |
| CN108023723B (en) * | 2016-11-04 | 2021-07-09 | 华为技术有限公司 | Method for frequency synchronization and slave clock |
| CN107395307B (en) * | 2017-07-12 | 2019-04-19 | 瑞斯康达科技发展股份有限公司 | A kind of clock synchronizing method and equipment |
| CN110662284B (en) * | 2018-06-28 | 2021-05-11 | 华为技术有限公司 | Method and device for correcting time information |
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