CN101950265A - Method for CPU board card program downloading and hardware online detection and plug-in connector - Google Patents
Method for CPU board card program downloading and hardware online detection and plug-in connector Download PDFInfo
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Abstract
The invention relates to a method for CPU board card program downloading and hardware online detection and a plug-in connector, which is developed mainly aiming at simplifying a series of complex links such as set-up program writing in, hardware circuit detection and application program updating in the actual production and operation process of a CPU board card in the embedded-type system containing an Ethernet interface. The main technical main point lies in the automation and high efficiency of the program downloading and hardware board card test. The technical scheme realizes automatic download of the board card program by using the special circuit design and the flow program and finishes online automatic detection function of a hardware circuit of the board card per se. The CPU board by using the technical scheme can effectively solve or avoid a plurality of problems in the batch production and fully improve the production efficiency and quality of the product.
Description
Technical field
The application that the present invention relates to: have all embedded systems that The Ethernet Interface Design, CPU program need guide or guide by the SPI interface by outside parallel bus.
Background technology
Along with the electronic devices and components development of technology, embedded system and ethernet technology also develop rapidly, and the embedded ethernet system is widely used in the automated system of a lot of industries.And along with the mass marketed of most embedded ethernet products, the program burn writing of its production link and hardware testing become the weak link in the production, are not good at if handle, and are easy to influence production efficiency of products and quality.
At present, program download and hardware detection mode commonly used have following two kinds:
1. directly use the FLASH chip (Chip Packaging is the plug-in mounting form) of burned program to be installed on the chip pad on the integrated circuit board, finish program production; Realize detecting by changing the different different test procedures of program chip operation; Indicate integrated circuit board whether by test by the pilot lamp that designs in advance on integrated circuit board.
2. download start-up routine (being called BOOTROM usually) by BDI or JTAG, pass through port down load application program or test procedure again in the FLASH chip; Indicate integrated circuit board whether by test by pilot lamp or man-machine interface (as the liquid crystal panel of device).
All there is certain shortcoming in above dual mode, as: 1. mode along with the raising of integrated circuit board integrated level, is used placing components to be used as procedure stores in a large number and more and more is not suitable for; And exist placing components to contact insecure risk with the base existence; 2. mode needs the work of loaded down with trivial details repetitions such as producers often use that BDI or JTAG instrument " are plugged-write a program-pull up " on different integrated circuit boards, and also will move test procedure afterwards carries out the integrated circuit board hardware testing, also will write application program at last.
Summary of the invention
The objective of the invention is: the new method that the download of a kind of program of CPU board efficiently, renewal and hardware integrated circuit board online automatic detection are provided.
1.CPU the integrated circuit board program is downloaded and the new method of the online detection of hardware, comprises step:
1) will insert on the chip carrier of CPU board with the guiding scratch pad memory of boot, finish the automatic control of CPU scratch pad memory with CPU/ scratch pad memory plug-in unit;
2) described CPU board is connected with PC, constitutes Ethernet;
3) CPU board is downloaded test procedure automatically;
4) PC sticks into capable on-line testing to CPU board;
5) generate test report,, then CPU board is sticked into the row maintenance if report is unusual, if report is normal, down load application program then;
6) finish;
Described CPU/ scratch pad memory plug-in unit comprises two kinds of parallel communications plug-in unit and serial communication plug-in, and its hardware circuit is described below:
A) to come guiding CPU to download the BOOT program by outside parallel bus be boot to the parallel communications plug-in unit, its circuit comprises: comprise logical AND gate, coding chip and switch, realize that function is when switch closes and during the GPIO port of CPU output high level, scratch pad memory is a boot state, under other situation, scratch pad memory is the program download state;
The first input end of logical AND gate connects high level by switch, and second input end connects the GPIO port of CPU; The first input end of logical AND gate also connects low level by pull down resistor, and second input end also connects high level by pull-up resistor;
Sheet choosing end A, the B of the sheet choosing end of coding chip are connected the non-gate output terminal of logical and, low level and low level respectively with C; The sheet that the Enable Pin 1,2 and the E3 of coding chip is connected the BOOT chip respectively selects pin, low level and high level; The output terminal Y0 of coding chip is connected the guiding Enable Pin of scratch pad memory respectively with Y1 and the program of scratch pad memory is downloaded Enable Pin; Coding chip true value relation table 1,
Table 1:
B) to come guiding CPU to download the BOOT program by the SPI structure be boot to serial communication plug-in, and its circuit comprises: comprise logical and not gate, logic sum gate and switch; , realizing that function is when switch closes and during the GPIO port of CPU output high level, scratch pad memory is a boot state, under other situation, scratch pad memory is not to be in boot state;
The first input end of logical and not gate connects high level by switch, and second input end connects the GPIO port of CPU; The first input end of logical and not gate also pull down resistor connects low level, and second input end also connects high level by pull-up resistor;
The first input end of described logic sum gate connects the output terminal of logical and not gate, and second input end connects the reset terminal of CPU, and output terminal connects the SPI start-up mode Enable Pin of scratch pad memory.
Described scratch pad memory is FLASH, and described switch is a wire jumper.
The present invention mainly for simplify CPU board in the embedded system that contains Ethernet interface be stuck in need to carry out in the actual production operation process such as start-up routine write, a series of loaded down with trivial details links such as hardware circuit detections, application program update develop, its main technical points is robotization and the high efficiency that program is downloaded and the hardware integrated circuit board is tested.The technical program mainly is to realize the automatic download of integrated circuit board program by the program step of the circuit design of special use and procedure, and finishes the online automatic detection function of integrated circuit board self hardware circuit; The CPU board that adopts the technical program to design can solve or avoid the problems in batch process effectively, thereby has improved production efficiency of products and quality fully.
The present invention has a mind to effect: adopt the present invention, not only improved production efficiency, also improved the confidence level of product test.
Description of drawings
Fig. 1 is applied to the circuit design synoptic diagram that outside parallel bus guides,
Fig. 2 is applied to the circuit design synoptic diagram that the SPI interface guides,
Fig. 3 is a process flow diagram of realizing the automatic on-line measuring ability of hardware plug by the step of procedure.
Embodiment
The invention will be further described below in conjunction with accompanying drawing and embodiment:
The embodiment of the technical program is:
(1) realizes the automatic control of CPU by the hardware circuit of design specialized to the FLASH program space, physical circuit figure such as Fig. 1 and Fig. 2 (Fig. 1, be to be applied to the circuit design that outside parallel bus guides, Fig. 2 is applied to the circuit design that the SPI interface guides);
(2) step by procedure realizes the automatic on-line measuring ability of hardware plug, and its flow process as shown in Figure 3;
A, with the hardware circuit that outside parallel bus guides, the principle of work of circuit shown in Figure 1 is as follows, divides three kinds of situations to describe:
JP1 is the wire jumper when selecting the integrated circuit board test, jumps onto expression and powers on for the first time and at first test; U1 is a logical AND gate; U2 is a coding chip; R1, R2 connect fixed level, initial affirmation level are arranged after making U1 power on; The CPU-GPIO signal connects the IO pin of CPU, / CPU-CS-BOOT signal connects the pin of CPU, the sheet that the #BOOT-FLASH signal connects the FLASH chip of plug-in mounting encapsulation selects pin, and the sheet that the #CODE-FLASH signal connects the FLASH chip of using when integrated circuit board normally moves selects pin.
1) when CPU just powered on, CPU-GPIO was defaulted as high-impedance state, was defaulted as high level after drawing on the resistance; The JP1 wire jumper is jumped onto; Be output as high level with door U1 this moment.When CPU powers on, gating starts the CS pin (/CPU-CS-BOOT is a low level) of BOOT chip (being the described FLASH chip that contains boot), this moment, #BOOT-FLASH was selected, the FLASH chip of plug-in mounting encapsulation just is selected, CPU is by reading code wherein, and CPU moves.
2) when CPU program after externally operation is got up among the RAM, drag down (CPU-GPIO is a low level) by CPU-GPIO, make and be output as low level with door U1, then chosen #CODE-FLASH during CPU visit this moment BOOT space, read-write operation is carried out (as writing the BOOT program in the FLASH space that CPU uses in the time of just can normally moving integrated circuit board, application program, test procedure or the like).
When 3) CPU card normally uses, the JP1 wire jumper is taken off, be output as low level with door U1 this moment.When CPU powered on, gating started the CS pin (/CPU-CS-BOOT is a low level) of BOOT, and #CODE-FLASH is selected, and the FLASH that normal operation is used is selected, and CPU is by reading code wherein, and CPU normally moves.
Annotate: be in the effect of guiding FLASH in its tangible total system of #BOOT_FLASH.
B, with the hardware circuit that the SPI interface guides, the principle of work of circuit shown in Figure 2 is as follows, is divided into three kinds of situations and describes:
JP1 is the wire jumper when selecting the integrated circuit board test, jumps onto expression and powers on for the first time and at first test; U1 is the logical and not gate; U2 is a logic sum gate; R1, R2, R3 connect fixed level, initial affirmation level are arranged after making U1 power on; The CPU-GPIO signal connects the IO pin of CPU, and the sheet that/BOOT-SPI signal connects the SPI FLASH of plug-in mounting encapsulation selects pin, and the sheet that/BOOT-MODE signal connects the FLASH chip of using when integrated circuit board normally moves selects pin.
1) when CPU just powered on, CPU_GPIO was defaulted as high-impedance state, was defaulted as high level after drawing on the resistance; The JP1 wire jumper is jumped onto; This moment Sheffer stroke gate U1 /the BOOT-MODE pin is output as low level.In the cpu chip reseting procedure ,/BOOT-MODE and/RST or the door U2 control under ,/BOOT-SPI enables the SPI start-up mode; CPU reads wherein code by SPI FLASH, and CPU moves.
2) when CPU program after externally operation is got up among the RAM, drag down (for low level) by CPU_BOOT-GPIO, make Sheffer stroke gate U1 /the BOOT_MODE pin is output as high level, at this moment/BOOT-SPI closes the SPI start-up mode, read-write operation is carried out (as writing the BOOT program in the FLASH space that CPU uses in the time of just can normally moving integrated circuit board, application program, test procedure or the like).
When 3) the PU plug-in unit normally uses, the JP1 wire jumper is taken off, this moment Sheffer stroke gate U1 /the BOOT-MODE pin is output as high level.At this moment/BOOT-SPI closes the SPI start-up mode, enables other Starting mode.CPU then reads code and starts operation from the FLASH space that normal operation is used the time, CPU normally moves.
Just can finish the automatic control of CPU by any the operation of above dual mode to program FLASH; In addition, again plug-in unit is linked to each other with netting twine with PC, just can realize application program and the test procedure automatic download function on the CPU board card, also realized the online measuring ability of CPU card hardware simultaneously easily.
With reference to figure 3, its main flow process is as follows:
According to the design of the technical program, CPU card debugging producers' groundwork will become more easily simple, and operation steps mainly contains:
1) will insert with the BOOT FLASH of boot BOOTROM on the chip carrier of CPU board;
2) the JP1 wire jumper is jumped onto;
3) netting twine (data connect with) is connected to PC;
4) plug-in unit powers on, (this software is identical with burning program software function of the prior art by the application software on the PC then, be easy to realize, so further do not limited) to finish BOOTTROM automatically erasable, the online detection of integrated circuit board hardware circuit, examining report generates and application program (CPU work required program, be stored among the FLASH) download;
5) hardware testing of checking integrated circuit board on PC is reported:
Show that as test report plug-in unit is unusual, then the attached test report of plug-in unit is changeed helpdesk's processing;
Show that as test report plug-in unit is normal, then the down load application program is taken off JP1 and BOOT FLASH after finishing, and plug-in unit can normally use.
Claims (5)
1. a CPU board card program is downloaded and the hardware on-line detection method, it is characterized in that comprising step:
1) will insert on the chip carrier of CPU board with the guiding scratch pad memory of boot, finish the automatic control of CPU scratch pad memory with CPU/ scratch pad memory plug-in unit;
2) described CPU board is connected with PC, constitutes Ethernet;
3) CPU board is downloaded test procedure automatically;
4) PC sticks into capable on-line testing to CPU board;
5) generate test report,, then CPU board is sticked into the row maintenance if report is unusual, if report is normal, down load application program then;
6) finish;
Described CPU/ scratch pad memory plug-in unit comprises two kinds of parallel communications plug-in unit and serial communication plug-in;
A) to come guiding CPU to download the BOOT program by outside parallel bus be boot to the parallel communications plug-in unit, its circuit comprises: comprise logical AND gate, coding chip and switch, realize that function is when switch closes and during the GPIO port of CPU output high level, scratch pad memory is a boot state, under other situation, scratch pad memory is the program download state;
The first input end of logical AND gate connects high level by switch, and second input end connects the GPIO port of CPU; The first input end of logical AND gate also connects low level by pull down resistor, and second input end also connects high level by pull-up resistor;
Sheet choosing end A, the B of the sheet choosing end of coding chip are connected the non-gate output terminal of logical and, low level and low level respectively with C; The sheet that the Enable Pin 1,2 and the E3 of coding chip is connected the BOOT chip respectively selects pin, low level and high level; The output terminal Y0 of coding chip is connected the guiding Enable Pin of scratch pad memory respectively with Y1 and the program of scratch pad memory is downloaded Enable Pin; Coding chip true value relation table 1,
Table 1:
B) to come guiding CPU to download the BOOT program by the SPI structure be boot to serial communication plug-in, and its circuit comprises: comprise logical and not gate, logic sum gate and switch; , realizing that function is when switch closes and during the GPIO port of CPU output high level, scratch pad memory is a boot state, under other situation, scratch pad memory is not to be in boot state;
The first input end of logical and not gate connects high level by switch, and second input end connects the GPIO port of CPU; The first input end of logical and not gate also pull down resistor connects low level, and second input end also connects high level by pull-up resistor;
The first input end of described logic sum gate connects the output terminal of logical and not gate, and second input end connects the reset terminal of CPU, and output terminal connects the SPI start-up mode Enable Pin of scratch pad memory.
2. CPU board card program according to claim 1 is downloaded and the hardware on-line detection method, it is characterized in that described scratch pad memory is FLASH.
3. CPU board card program according to claim 1 is downloaded and the hardware on-line detection method, it is characterized in that described switch is a wire jumper.
4. CPU/ scratch pad memory plug-in unit of realizing the described method of claim 1, it is characterized in that CPU/ scratch pad memory plug-in unit is the parallel communications mode, circuit comprises: comprise logical AND gate, coding chip and switch, realize that function is when switch closes and during the GPIO port of CPU output high level, scratch pad memory is a boot state, under other situation, scratch pad memory is the program download state;
The first input end of logical AND gate connects high level by switch, and second input end is used for connecting the GPIO port of CPU; The first input end of logical AND gate also connects low level by pull down resistor, and second input end also connects high level by pull-up resistor;
Sheet choosing end A, the B of the sheet choosing end of coding chip are connected the non-gate output terminal of logical and, low level and low level respectively with C; The sheet that the Enable Pin 1,2 and the E3 of coding chip is used for being connected the BOOT chip respectively selects pin, low level and high level; The output terminal Y0 of coding chip is used for being connected the guiding Enable Pin of scratch pad memory respectively with Y1 and the program of scratch pad memory is downloaded Enable Pin; Coding chip true value relation table 1,
Table 1:
。
5. a CPU/ scratch pad memory plug-in unit of realizing the described method of claim 1 is characterized in that CPU/ scratch pad memory plug-in unit is a serial communication mode, and circuit comprises: comprise logical and not gate, logic sum gate and switch; , realizing that function is when switch closes and during the GPIO port of CPU output high level, scratch pad memory is a boot state, under other situation, scratch pad memory is not to be in boot state;
The first input end of logical and not gate connects high level by switch, and second input end connects the GPIO port of CPU; The first input end of logical and not gate also connects low level by pull down resistor, and second input end also connects high level by pull-up resistor;
The first input end of described logic sum gate connects the output terminal of logical and not gate, and second input end is used for connecting the reset terminal of CPU, and output terminal is used for connecting the SPI start-up mode Enable Pin of scratch pad memory.
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Cited By (6)
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| CN102565671A (en) * | 2011-12-16 | 2012-07-11 | 电子科技大学 | Dynamic allocation method for on-line programming of integrated circuit tester |
| CN104314379A (en) * | 2014-08-26 | 2015-01-28 | 北京精密机电控制设备研究所 | Unlocking control circuit for locking mechanism |
| CN106708770A (en) * | 2015-11-12 | 2017-05-24 | 中车大连电力牵引研发中心有限公司 | Program downloading device |
| CN108319441A (en) * | 2018-01-02 | 2018-07-24 | 广东美的制冷设备有限公司 | Control method, device, system, processor and the storage medium that audio plays |
| CN109656756A (en) * | 2018-11-12 | 2019-04-19 | 南京南瑞继保电气有限公司 | Multi-core CPU board adjustment method and device, mobile memory medium |
| CN111175632A (en) * | 2018-11-13 | 2020-05-19 | 南京南瑞继保电气有限公司 | Single board testing system based on python |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102565671A (en) * | 2011-12-16 | 2012-07-11 | 电子科技大学 | Dynamic allocation method for on-line programming of integrated circuit tester |
| CN102565671B (en) * | 2011-12-16 | 2013-12-11 | 电子科技大学 | Dynamic allocation method for on-line programming of integrated circuit tester |
| CN104314379A (en) * | 2014-08-26 | 2015-01-28 | 北京精密机电控制设备研究所 | Unlocking control circuit for locking mechanism |
| CN106708770A (en) * | 2015-11-12 | 2017-05-24 | 中车大连电力牵引研发中心有限公司 | Program downloading device |
| CN108319441A (en) * | 2018-01-02 | 2018-07-24 | 广东美的制冷设备有限公司 | Control method, device, system, processor and the storage medium that audio plays |
| CN108319441B (en) * | 2018-01-02 | 2021-07-16 | 广东美的制冷设备有限公司 | Audio playing control method, device, system, processor and storage medium |
| CN109656756A (en) * | 2018-11-12 | 2019-04-19 | 南京南瑞继保电气有限公司 | Multi-core CPU board adjustment method and device, mobile memory medium |
| CN109656756B (en) * | 2018-11-12 | 2022-05-17 | 南京南瑞继保电气有限公司 | Multi-core CPU board debugging method and device and mobile storage medium |
| CN111175632A (en) * | 2018-11-13 | 2020-05-19 | 南京南瑞继保电气有限公司 | Single board testing system based on python |
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Effective date of registration: 20231024 Address after: 510620, No. two, No. 2, Tianhe South Road, Guangzhou, Guangdong, Tianhe District Patentee after: Guangzhou Power Supply Bureau of Guangdong Power Grid Co.,Ltd. Address before: 510620, No. two, No. 2, Tianhe South Road, Guangzhou, Guangdong, Tianhe District Patentee before: Guangzhou Power Supply Bureau of Guangdong Power Grid Co.,Ltd. Patentee before: NR ELECTRIC Co.,Ltd. Effective date of registration: 20231024 Address after: 510620, No. two, No. 2, Tianhe South Road, Guangzhou, Guangdong, Tianhe District Patentee after: Guangzhou Power Supply Bureau of Guangdong Power Grid Co.,Ltd. Patentee after: NR ELECTRIC Co.,Ltd. Address before: 510000 No. 2 Tianhe Second Road, Tianhe District, Guangzhou City, Guangdong Province Patentee before: GUANGZHOU POWER SUPPLY Co.,Ltd. Patentee before: NR ELECTRIC Co.,Ltd. |