CN108319441B - Audio playing control method, device, system, processor and storage medium - Google Patents

Audio playing control method, device, system, processor and storage medium Download PDF

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CN108319441B
CN108319441B CN201810010132.0A CN201810010132A CN108319441B CN 108319441 B CN108319441 B CN 108319441B CN 201810010132 A CN201810010132 A CN 201810010132A CN 108319441 B CN108319441 B CN 108319441B
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audio
audio data
chip
interface
flash chip
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CN108319441A (en
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叶雄斌
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Midea Group Co Ltd
GD Midea Air Conditioning Equipment Co Ltd
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Midea Group Co Ltd
GD Midea Air Conditioning Equipment Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/16—Sound input; Sound output
    • G06F3/162—Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Audiology, Speech & Language Pathology (AREA)
  • General Health & Medical Sciences (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Acoustics & Sound (AREA)
  • Signal Processing (AREA)
  • Circuit For Audible Band Transducer (AREA)

Abstract

The invention discloses a control method of audio playing, which is applied to a Zigbee microprocessor, wherein the Zigbee microprocessor is connected with a Flash chip based on a preset SPI (serial peripheral interface) and simulates I (input/output) based on the SPI2The S interface is connected with an audio DAC chip and comprises: zigbee microprocessor reads audio data stored in Flash chip based on SPI interface and bases the audio data on I2The S interface outputs the audio data to the audio DAC chip, the audio DAC chip converts the audio data into corresponding analog audio signals, the analog audio signals are subjected to power amplification processing and then drive the loudspeaker to play corresponding audio, namely the Flash chip and the audio DAC chip multiplex the SPI interface, and audio playing is completed. The invention also discloses a control device, a system, a processor and a storage medium for audio playing. The invention achieves the effect of giving consideration to both cost and quality when realizing audio playing based on the Zigbee microprocessor.

Description

Audio playing control method, device, system, processor and storage medium
Technical Field
The present invention relates to the technical field of Zigbee (Zigbee protocol), and in particular, to a method, an apparatus, a system, a processor, and a storage medium for controlling audio playback.
Background
The ZigBee technology is a short-distance two-way wireless communication technology, has the advantages of low complexity, low power consumption and low cost, and is gradually and widely applied to networking communication of intelligent home appliances. Since the initial positioning of the ZigBee technology is applied to data monitoring and simple data transmission, and advanced media applications such as audio are not considered, the ZigBee microprocessor is generally not provided with an I for audio transmission2And an S (Inter-IC Sound, audio bus built in integrated circuit) interface. Therefore, audio playing is realized based on the ZigBee microprocessor, or an additional voice playing module is expanded, and the voice playing module is adopted to take the proxy of all voice playing logic processing; or a mask voice chip is externally connected, corresponding audio to be played is preset in the mask voice chip, and the preset audio is played back by triggering the mask voice chip.
However, since the voice playing module is usually a complete embedded system, at least a microprocessor, a Flash memory chip for audio storage, an audio power amplifier, and the like need to be included, and an independent software module needs to be re-developed, which results in higher development cost. The preset audio in the mask voice chip cannot be updated, and the code rate of audio playing is low and fixed, so that the audio output through the mask voice chip has poor expandability and audio quality. Therefore, cost and quality problems cannot be considered in the mode of realizing audio playing based on the ZigBee microprocessor at present.
Disclosure of Invention
The invention mainly aims to provide a method, a device, a system, a processor and a storage medium for controlling audio playing, and aims to solve the technical problem that the cost and the quality cannot be considered at the same time when the audio playing is realized based on a ZigBee microprocessor in the prior art.
In order to achieve the above object, the present invention provides an audio playing control method, which is applied to a Zigbee microprocessor, the Zigbee microprocessor is connected to a Flash memory chip based on a preset SPI serial peripheral interface, and simulates an I based on the SPI interface2The S integrated circuit is internally provided with an audio bus interface connected with an audio DAC digital-to-analog conversion chip, and the audio playing control method comprises the following steps:
the Zigbee microprocessor reads the audio data stored in the Flash chip based on the SPI interface;
basing the audio data on the I2And the S interface outputs the audio DAC chip so that the audio DAC chip converts the audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio.
Preferably, the Zigbee microprocessor further includes a first IO input/output interface, the CS chip select signal pin of the Flash chip is connected based on the first IO interface, and the step of the Zigbee microprocessor reading the audio data stored in the Flash chip based on the SPI interface includes:
the Zigbee microprocessor enables a CS signal pin of the Flash chip based on the first IO interface, and sends a reading command to the Flash chip so that the Flash chip feeds back corresponding audio data when receiving the reading command;
and receiving the audio data fed back by the Flash chip by the MISO input data line based on the SPI interface.
Preferably, the Zigbee microprocessor further includes a second IO interface, the WS word selection signal pin of the audio DAC chip is connected based on the second IO interface, and the audio data is based on the I2Before the step of outputting the interface S to the audio DAC chip, the method further comprises the following steps:
the Zigbee microprocessor adopts a timer to overturn the IO signal of the second IO interface to generate a PWM (pulse width modulation) signal so as to simulate a WS signal according to the PWM signal;
and carrying out phase synchronization on the simulated WS signal based on a preset PWM synchronization matching value.
Preferably, said basing said audio data on said I2Before the step of outputting the interface S to the audio DAC chip, the method further comprises the following steps:
acquiring audio information contained in a frame header of the audio data;
and configuring the working frequency of the Zigbee microprocessor according to the audio information.
Preferably, the Zigbee microprocessor further includes a first buffer and a second buffer, and after the step of the Zigbee microprocessor reading the audio data stored in the Flash chip based on the SPI interface, the method further includes:
buffering the audio data in the first buffer and the second buffer;
the audio data is based on the I2The step of outputting the S interface to the audio DAC chip comprises the following steps:
sequentially basing the audio data buffered in the first buffer and the second buffer on the I2And the S interface outputs the audio DAC chip.
Preferably, the buffer space of the first buffer and the second buffer is set to 4 KB.
Preferably, the method for controlling audio playing includes:
continuously sending two reading commands to the Flash chip so that the Flash chip can feed back the first two audio data segments of the audio data;
respectively caching the first two sections of audio data in the first buffer area and the second buffer area;
outputting the currently cached audio data segment in the first buffer to the audio DAC chip;
when the output of the currently cached audio data segment in the first buffer area is finished, judging whether the reading of the audio data is finished;
if not, sending a reading command to the Flash chip so that the Flash chip can feed back the next audio data segment of the audio data;
outputting the currently cached audio data segment in the second buffer area to the audio DAC chip; buffering the audio data segment fed back by the Flash chip in the first buffer area;
when the output of the currently cached audio data segment in the second buffer area is finished, judging whether the reading of the audio data is finished;
if not, sending a reading command to the Flash chip so that the Flash chip can feed back the next audio data segment of the audio data; and continuing to return to the step of outputting the currently cached audio data segment in the first buffer area to the audio DAC chip until the audio data is completely read and the output of the audio data segments cached in the first buffer area and the second buffer area is completed.
Preferably, before the step of reading the audio data stored in the Flash chip based on the SPI interface, the Zigbee microprocessor further includes:
when an audio playing instruction is received, data processing of a Zigbee protocol stack is suspended;
the audio data is based on the I2The S interface is output to the audio DAC chip so that the audio DAC chip can convert the audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding soundsAfter the step of frequency, the method further comprises the following steps:
and when the audio playing is finished, recovering the data processing of the Zigbee protocol stack.
In addition, in order to achieve the above object, the present invention further provides a control device for audio playback, including: the audio playing control program is stored on the memory and can be run on the processor, and when being executed by the processor, the audio playing control program realizes the steps of the control method of the audio playing.
In addition, in order to achieve the above object, the present invention further provides a Zigbee microprocessor including the control device for audio playing as described above.
In addition, in order to achieve the above object, the present invention further provides an audio playing control system, where the audio playing control system includes a Zigbee microprocessor, a Flash chip, and an audio DAC chip, and the Zigbee microprocessor is connected to the Flash chip based on a preset SPI interface, and is based on an I simulated by the SPI interface2The S interface is connected with the audio DAC chip, wherein:
the Flash chip is used for feeding back corresponding audio data to the Zigbee microprocessor when receiving a reading command sent by the Zigbee microprocessor;
the Zigbee microprocessor is used for sending a reading command to the Flash chip; when the audio data fed back by the Flash chip are received, the audio data are output to the audio DAC chip;
and the audio DAC chip is used for converting the audio data into corresponding analog audio signals when receiving the audio data, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio.
Furthermore, to achieve the above object, the present invention further provides a computer readable storage medium, which stores thereon an audio playback control program, which when executed by a processor, implements the steps of the control method for audio playback as described above.
In the scheme provided by the invention, the Zigbee microprocessor is connected with the Flash chip based on the preset SPI interface and simulates I based on the SPI interface2The S interface is connected with the audio DAC chip, the Zigbee microprocessor reads audio data stored in the Flash chip based on the SPI interface and bases the audio data on the analog I2And the S interface outputs the audio data to an audio DAC chip, the audio DAC chip converts the received audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio. Because the hardware resources and the processing capacity of the Zigbee microprocessor are utilized, a complete embedded system (a voice playing module) does not need to be additionally expanded and an independent software module does not need to be re-developed, so the cost is reduced; and because the Flash chip is adopted to store the audio data, the updating and the expansion of the audio data are realized, and the quality of the audio output through the audio DAC chip is high, namely the effect of giving consideration to both cost and quality is achieved.
Drawings
Fig. 1 is a schematic structural diagram of a hardware operating environment of a Zigbee microprocessor according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a first embodiment of a method for controlling audio playback according to the present invention;
FIG. 3 is a timing diagram of the SPI;
FIG. 4 is I2A timing diagram of S;
FIG. 5 is a diagram of a hardware connection framework of an alternative audio playback system according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating a second embodiment of a method for controlling audio playback according to the present invention;
fig. 7 is a schematic flow chart of an alternative audio playing according to an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The solution of the embodiment of the invention is mainly as follows: zigbee microprocessor connects Flash chip based on preset SPI interface and simulates I based on SPI interface2The S interface is connected with the audio DAC chip, the Zigbee microprocessor reads audio data stored in the Flash chip based on the SPI interface and bases the audio data on the analog I2And the S interface outputs the audio data to an audio DAC chip, the audio DAC chip converts the received audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio. By the technical scheme of the embodiment of the invention, the problem that the cost and the quality can not be considered at the same time when the audio playing is realized based on the ZigBee microprocessor is solved.
The embodiment of the invention provides a Zigbee microprocessor.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a hardware operating environment of a Zigbee microprocessor according to an embodiment of the present invention.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.
As shown in fig. 1, the Zigbee microprocessor may include: a processor 1001, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface). The memory 1005 may be a high-speed RAM memory or a non-volatile memory (e.g., a magnetic disk memory). The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the Zigbee microprocessor architecture shown in fig. 1 does not constitute a limitation of Zigbee microprocessors, and may include more or fewer components than shown, or some components in combination, or a different arrangement of components.
As shown in fig. 1, a memory 1005, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and an audio playback control program.
The processor 1001 and the memory 1005 of the Zigbee microprocessor of the present invention may be arranged in a control device for audio playing, where the control device for audio playing calls an audio playing control program stored in the memory 1005 through the processor 1001, and executes the following operations:
the Zigbee microprocessor reads audio data stored in the Flash chip based on the SPI interface;
basing the audio data on I2And the S interface outputs the audio data to an audio DAC chip so that the audio DAC chip converts the audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio.
Further, the processor 1001 may call the audio playback control program stored in the memory 1005, and also perform the following operations:
the Zigbee microprocessor enables a CS signal pin of the Flash chip based on a first IO interface, and sends a reading command to the Flash chip so that the Flash chip feeds back corresponding audio data when receiving the reading command;
and receiving the audio data fed back by the Flash chip by the MISO input data line based on the SPI interface.
Further, the processor 1001 may call the audio playback control program stored in the memory 1005, and also perform the following operations:
the Zigbee microprocessor adopts a timer to overturn an IO signal of a second IO interface to generate a PWM (pulse width modulation) signal so as to simulate a WS (WS) signal according to the PWM signal;
and carrying out phase synchronization on the simulated WS signal based on a preset PWM synchronization matching value.
Further, the processor 1001 may call the audio playback control program stored in the memory 1005, and also perform the following operations:
acquiring audio information contained in a frame header of the audio data;
and configuring the working frequency of the Zigbee microprocessor according to the audio information.
Further, the processor 1001 may call the audio playback control program stored in the memory 1005, and also perform the following operations:
buffering the audio data in a first buffer and a second buffer;
sequentially basing the audio data buffered in the first buffer and the second buffer on the I2And the S interface outputs the audio DAC chip.
Further, the processor 1001 may call the audio playback control program stored in the memory 1005, and also perform the following operations:
continuously sending two reading commands to the Flash chip so that the Flash chip can feed back the first two audio data segments of the audio data;
respectively caching the first two sections of audio data in the first buffer area and the second buffer area;
outputting the currently cached audio data segment in the first buffer to the audio DAC chip;
when the output of the currently cached audio data segment in the first buffer area is finished, judging whether the reading of the audio data is finished;
if not, sending a reading command to the Flash chip so that the Flash chip can feed back the next audio data segment of the audio data;
outputting the currently cached audio data segment in the second buffer area to the audio DAC chip; buffering the audio data segment fed back by the Flash chip in the first buffer area;
when the output of the currently cached audio data segment in the second buffer area is finished, judging whether the reading of the audio data is finished;
if not, sending a reading command to the Flash chip so that the Flash chip can feed back the next audio data segment of the audio data; and continuing to return to the step of outputting the currently cached audio data segment in the first buffer area to the audio DAC chip until the audio data is completely read and the output of the audio data segments cached in the first buffer area and the second buffer area is completed.
Further, the processor 1001 may call the audio playback control program stored in the memory 1005, and also perform the following operations:
when an audio playing instruction is received, data processing of a Zigbee protocol stack is suspended;
and when the audio playing is finished, recovering the data processing of the Zigbee protocol stack.
According to the scheme, the Zigbee microprocessor is connected with the Flash chip based on the preset SPI interface and simulates I based on the SPI interface2The S interface is connected with the audio DAC chip, the Zigbee microprocessor reads audio data stored in the Flash chip based on the SPI interface and bases the audio data on the analog I2And the S interface outputs the audio data to an audio DAC chip, the audio DAC chip converts the received audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio. Because the hardware resources and the processing capacity of the Zigbee microprocessor are utilized, a complete embedded system (a voice playing module) does not need to be additionally expanded and an independent software module does not need to be re-developed, so the cost is reduced; and because the Flash chip is adopted to store the audio data, the updating and the expansion of the audio data are realized, and the quality of the audio output through the audio DAC chip is high, namely the effect of giving consideration to both cost and quality is achieved.
Based on the above hardware structure, an embodiment of the control method for audio playing of the present invention is provided.
Referring to fig. 2, fig. 2 is a flowchart illustrating a control method for audio playing according to a first embodiment of the present invention.
In a first embodiment, the method for controlling audio playback includes the following steps:
step S10, the Zigbee microprocessor reads the audio data stored in the Flash chip;
and step S20, outputting the audio data to an audio DAC chip so that the audio DAC chip converts the audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio.
In the present invention, the control method of audio playing is preferably applied to the Zigbee microprocessor. The Zigbee microprocessor is preset with an SPI (Serial Peripheral Interface), which is a high-speed, full-duplex, synchronous communication bus and generally has four lines, namely a CS (chip select) line, a CLK (clock) line, a MISO (input data) line, and a MOSI (output data) line. The SPI interface is often used for external Flash (Flash) chips. In this embodiment, the Zigbee microprocessor is connected to a corresponding Flash chip based on a preset SPI interface thereof, and the Flash chip stores corresponding audio data.
I2The S (Inter-IC Sound, audio bus built in integrated circuit) interface is usually used for accessing a high-quality multimedia audio DAC (Digital to analog converter) chip, I2S also typically includes four lines, a BCLK (bit clock) line, an MCLK (master clock) line, a WS (word select signal) line, and an SDATA (data) line, respectively.
As shown in FIGS. 3 and 4, SPI and I2The clock of S is basically consistent with the logic of the data line, and the output direction is I2S is one WS word select signal and one MCLK main clock signal more than SPI. Among them, some audio DAC chips may automatically generate a matched MCLK main clock signal from a BCLK bit clock signal through an internal PLL (phase locked loop, which is commonly used for a frequency multiplication process of a clock signal) for the MCLK main clock signal, and thus may not supply the MCLK main clock signal. For WS word selection signals, which are used for distinguishing left and right channels of audio data, WS signals can be simulated by using a common IO port through a certain software synchronization means. Therefore, in this embodiment, the SPI interface preset by the Zigbee microprocessor is used to simulate the I2S interface is connected with corresponding audio DAC chipI of Zigbee microprocessor through SPI interface simulation2And the S interface outputs audio data to the audio DAC chip. That is, in this embodiment, the Flash chip and the audio DAC chip are accessed simultaneously through the SPI interface multiplexing. Specifically, the CLK and MOSI pins of the SPI interface are connected to both the Flash chip and the audio DAC chip. In addition, the MISO pin of the SPI interface is independently connected to the Flash chip and used for reading the audio data stored in the Flash chip.
Since the CLK clock of the SPI interface maintains a working state, and the CS chip selection of the SPI interface cannot be used, in this embodiment, the Zigbee microprocessor is further provided with a corresponding ordinary IO (input output) interface, and for convenience of description, the IO interface is hereinafter referred to as a first IO interface, and the first IO interface is used to simulate the enabled CS chip selection of the Flash chip. Specifically, the Zigbee microprocessor is connected to the CS chip select signal pin of the Flash chip based on the first IO interface, and simulates the CS chip select signal of the Flash chip. In addition, the Zigbee microprocessor is further provided with another common IO interface, for convenience of description, the another IO interface is hereinafter referred to as a second IO interface, and the second IO interface is adopted to connect a WS word selection signal pin of the audio DAC chip and simulate a WS word selection signal.
Fig. 5 is a schematic diagram of an optional hardware connection structure of the audio playing system according to this embodiment. The Zigbee microprocessor is simultaneously connected with the Flash chip and the audio DAC chip, and the audio DAC chip is connected with the loudspeaker through the corresponding power amplifier.
When audio needs to be played, the Zigbee microprocessor first reads corresponding audio data stored in the Flash chip connected to the Zigbee microprocessor, and optionally, the step S10 includes:
step a, enabling a CS signal pin of the Flash chip by the Zigbee microprocessor based on the first IO interface, and sending a reading command to the Flash chip so that the Flash chip feeds back corresponding audio data when receiving the reading command;
and b, receiving the audio data fed back by the Flash chip based on the MISO input data line of the SPI.
Optionally, when the audio needs to be played, the Zigbee microprocessor enables the CS signal pin of the Flash chip based on the first IO interface, and sends a read command to the Flash chip. When the Flash chip receives the read command, the Flash chip feeds back corresponding audio data to the Zigbee microprocessor. The Zigbee microprocessor receives the audio data fed back by the Flash chip based on the MISO data line of the SPI interface.
And then, the Zigbee microprocessor outputs the read audio data to the audio DAC chip connected with the Zigbee microprocessor. Optionally, before the step S20, the method further includes:
step c, obtaining audio information contained in a frame header of the audio data;
and d, configuring the working frequency of the Zigbee microprocessor according to the audio information.
Optionally, because the corresponding code rate, data size, and other audio information of different audio data may be different, before audio playing is performed, the operating frequency of the Zigbee microprocessor is configured first. Specifically, the frame header of the audio data includes audio information such as an audio code rate, channel information, and a data size of the audio data. After the Zigbee microprocessor reads the audio data, the audio information included in the frame header of the audio data is acquired, and then, according to the audio information, the operating frequency of the Zigbee microprocessor is configured to match the playback code rate of the audio data and the switching between the left and right channels.
Optionally, before the step S20, the method further includes:
step e, the Zigbee microprocessor adopts a timer to overturn the IO signal of the second IO interface to generate a PWM (pulse width modulation) signal so as to simulate a WS signal according to the PWM signal;
and f, carrying out phase synchronization on the simulated WS signal based on a preset PWM synchronization matching value.
Optionally, before playing audio, the Zigbee microprocessor pair simulates I2The WS signal of S is phase synchronized. Specifically, since the WS signal waveform is very simple, and the high and low levels are the same time when the number of bits of the left and right channels is the same, the WS signal waveform can be considered as a 50-50 duty cycle PWM (Pulse Wi)dth Modulation) signal waveform. Therefore, in this embodiment, the IO signal of the second IO interface is inverted by using the timer to generate the PWM signal, so as to simulate the WS signal according to the PWM signal. And performing phase synchronization on the simulated WS signal based on a preset PWM synchronization matching value.
As shown in the timing chart of SPI in fig. 3, when SCK is at the rising edge and LSB (Least Significant Bit) is sent, exactly 16 SCK clock cycles have elapsed, and at the same time, the PWM signal needs to be flipped. I.e., the analog WS signal toggles when the rising edge of the LSB bit is transmitted. But I2The WS signal of the S request needs to be flipped half SCK period ahead, i.e. on the falling edge of SCK. Therefore, a PWM synchronization matching value is set so that PWM is synchronized with SPI, that is, phase synchronization of the analog WS signal is achieved.
Optionally, the PWM synchronous matching value is set according to the following preset formula:
the PWM synchronous matching value is equal to the matching value of a timer, half SCK clock number and asynchronous starting time difference;
the timer matching value needs to be obtained by calculation according to the code rate of the output audio, the asynchronous starting time difference refers to the relative time delay of the actual PWM starting and the SPI starting, and needs to be formulated according to a specific program compiling environment, and under the condition that the consistency of hardware environments is ensured, the universal purpose can be achieved.
After the operating frequency of the Zigbee microprocessor is configured and the phase synchronization of the analog WS signal is completed, the Zigbee microprocessor outputs the read audio data to the audio DAC chip.
When the audio DAC chip receives audio data output by the Zigbee microprocessor, the audio data is subjected to digital-to-analog signal conversion processing, the audio data is converted into corresponding analog audio signals, then the generated analog audio signals are transmitted to a power amplifier, and the power amplifier is used for carrying out signal amplification processing and then driving a loudspeaker to play corresponding audio.
In this embodiment, the hardware resources and the processing capability of the Zigbee microprocessor are used, and it is not necessary to additionally extend a complete embedded system (voice playing module) and redevelop a set of independent software modules, so that the cost is reduced. In addition, the Flash chip is adopted to store the audio data, so that the audio data can be updated and expanded, and the quality of the audio output through the audio DAC chip is high, thereby greatly improving the user experience.
In the solution provided by this embodiment, the Zigbee microprocessor connects the Flash chip based on the preset SPI interface, and simulates I based on the SPI interface2The S interface is connected with the audio DAC chip, the Zigbee microprocessor reads audio data stored in the Flash chip based on the SPI interface and bases the audio data on the analog I2And the S interface outputs the audio data to an audio DAC chip, the audio DAC chip converts the received audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio. Because the hardware resources and the processing capacity of the Zigbee microprocessor are utilized, a complete embedded system (a voice playing module) does not need to be additionally expanded and an independent software module does not need to be re-developed, so the cost is reduced; and because the Flash chip is adopted to store the audio data, the updating and the expansion of the audio data are realized, and the quality of the audio output through the audio DAC chip is high, namely the effect of giving consideration to both cost and quality is achieved.
Further, based on the first embodiment, a second embodiment of the audio playing control method of the present invention is provided, in this embodiment, the Zigbee microprocessor further includes a first buffer and a second buffer, as shown in fig. 6, and after the step S10, the method further includes:
step S30, buffering the audio data in the first buffer and the second buffer;
the step S20 includes:
step S21, sequentially basing the audio data buffered in the first buffer area and the second buffer area on the I2And the S interface outputs the audio DAC chip.
In this embodiment, the Zigbee microprocessor is configured with two corresponding buffers, and for convenience of description, the two buffers are referred to as a first buffer and a second buffer hereinafterA buffer area. Optionally, the buffer space of the first buffer and the second buffer is set to 4 KB. Those skilled in the art will understand that the buffer spaces of the first buffer and the second buffer may also be set to other values according to the actual application scenario, and the embodiment is not limited in this embodiment. After the Zigbee microprocessor reads the audio data from the Flash chip, the audio data is cached in the first buffer area and the second buffer area. Then, the audio data buffered in the first buffer area and the second buffer area are sequentially based on I2The S interface is output to the audio DAC chip, the audio DAC chip converts the audio DAC chip into an analog audio signal, and the analog audio signal is amplified by a power amplifier and then drives a loudspeaker to play corresponding audio.
Optionally, before the step S10, the method further includes:
when an audio playing instruction is received, data processing of a Zigbee protocol stack is suspended;
after the step S20, the method further includes:
and when the audio playing is finished, recovering the data processing of the Zigbee protocol stack.
When the user triggers an audio playing condition, such as clicking a preset audio playing control, a corresponding audio playing instruction is triggered. When the Zigbee microprocessor receives the audio playing instruction, the Zigbee protocol stack data processing is suspended, and the above audio data reading and output operation is executed, thereby realizing audio playing. And then, when the audio playing is finished, restoring the Zigbee protocol stack data processing.
Optionally, in order to ensure continuous reading and outputting of the audio data, a first buffer and a second buffer are used for reading and outputting the audio data in a ping-pong mode. Specifically, the control method for audio playing includes:
step g, continuously sending two reading commands to the Flash chip so that the Flash chip can feed back the first two audio data segments of the audio data;
step h, respectively caching the first two sections of audio data segments in the first buffer area and the second buffer area;
step i, outputting the audio data segment currently cached in the first buffer area to the audio DAC chip;
j, judging whether the audio data is read completely or not when the output of the audio data segment currently cached in the first buffer area is finished;
step k, if not, sending a reading command to the Flash chip so that the Flash chip can feed back the next section of the audio data;
step l, outputting the currently cached audio data segment in the second buffer area to the audio DAC chip; buffering the audio data segment fed back by the Flash chip in the first buffer area;
step m, when the output of the audio data segment currently cached in the second buffer area is finished, judging whether the reading of the audio data is finished;
step n, if not, sending a reading command to the Flash chip so that the Flash chip can feed back the next section of the audio data; and continuing to return to the step of outputting the currently cached audio data segment in the first buffer area to the audio DAC chip until the audio data is completely read and the output of the audio data segments cached in the first buffer area and the second buffer area is completed.
Specifically, in this embodiment, as shown in fig. 7, when the Zigbee microprocessor receives an audio playing instruction, data processing of the Zigbee protocol stack is suspended, and after the Zigbee microprocessor enables CS chip selection on the Flash chip, the Zigbee microprocessor continuously sends two reading commands to the Flash chip. And when the Flash chip receives the reading command, feeding back the first two audio data segments corresponding to the audio data. Optionally, in a case that the buffer space size of the first buffer and the second buffer is 4KB, the read command is a corresponding 4KB sector read command, and the Zigbee microprocessor continuously sends the 4KB sector read command to the Flash chip twice. When the Flash chip receives the 4KB sector read command, the corresponding 4KB sector audio data segment is fed back to the Zigbee microprocessor.
When the Zigbee microprocessor receives the first two audio data segments fed back by the Flash chip, the first two audio data segments are respectively cached in the first buffer area and the second buffer area.
Then, the Zigbee microprocessor acquires the audio information contained in the frame header from the frame header of the audio data contained in the cached audio data segment, and configures the operating frequency of the Zigbee microprocessor according to the audio information, so as to match the playback code rate of the audio data and the switching between the left and right channels. And a timer is used to complete the phase synchronization of the analog WS signal, and the specific operation is as described in the first embodiment, which is not described herein again.
And then, the Zigbee microprocessor outputs the currently cached audio data segment in the first buffer area to the audio DAC chip, so that the audio DAC chip outputs corresponding audio. And when the output of the audio data segment currently cached in the first buffer area is finished, judging whether the reading of the audio data is finished. For example, the size of the audio data in the audio information contained in the frame header and the total size of the audio data segments that have been currently output are obtained, and whether the difference between the size of the audio data and the total size of the audio data segments is smaller than the size of the buffer space of the buffer is compared. For example, if the buffer space size of the first buffer and the second buffer is 4KB, it is determined whether the difference between the size of the audio data and the total size of the audio data segments is less than 4 KB. If yes, judging that the audio data is completely read; otherwise, if the difference between the size of the audio data and the total size of the audio data segments is larger than the size of the buffer space of the buffer area, it is determined that the audio data is not completely read. It will be understood by those skilled in the art that the audio data can be judged whether the reading is completed in other ways, and the judgment is not limited to the above-mentioned one.
When the Zigbee microprocessor judges that the audio data reading is completed, the audio data segment currently cached in the second buffer area is output to the audio DAC chip, so that the audio DAC chip outputs a corresponding audio, and the audio data output is completed. Otherwise, when the audio data is judged not to be completely read, the Zigbee microprocessor suspends the audio output, the read command is sent to the Flash chip again based on the SPI, and when the Flash chip receives the read command again, the Flash chip feeds back the next audio data segment of the audio data to the Zigbee microprocessor.
And after the Zigbee microprocessor sends the reading command to the Flash chip again, restarting audio output and outputting the currently cached audio data segment in the second buffer area to the audio DAC chip. And when the next audio data segment fed back by the Flash chip is received, the audio data segment is cached in the first buffer area. When the output of the currently cached audio data segment in the second buffer area is finished, the Zigbee microprocessor again determines whether the reading of the audio data is finished.
When the Zigbee microprocessor judges that the audio data reading is completed, the audio data segment currently cached in the first buffer area is output to the audio DAC chip, so that the audio DAC chip outputs a corresponding audio, and the audio data output is completed. Otherwise, when the audio data is judged not to be completely read, the Zigbee microprocessor suspends the audio output, the read command is sent to the Flash chip again based on the SPI, and when the Flash chip receives the read command again, the Flash chip feeds back the next audio data segment of the audio data to the Zigbee microprocessor.
And after the Zigbee microprocessor sends the reading command to the Flash chip again, restarting audio output and outputting the currently cached audio data segment in the first buffer area to the audio DAC chip. And when the next audio data segment fed back by the Flash chip is received, the audio data segment is cached in the second buffer area. When the output of the currently cached audio data segment in the first buffer area is finished, the Zigbee microprocessor judges whether the reading of the audio data is finished again. And the Zigbee microprocessor executes the operations in a circulating way until the audio data is read completely, and the output of the audio data segments cached in the first buffer area and the second buffer area is finished. And then, the Zigbee microprocessor restores the data processing of the Zigbee protocol stack.
Therefore, in the audio output mode, when the audio data in one of the buffer areas is exhausted, the Zigbee microprocessor sends a read instruction to the Flash chip, and then recovers audio output and outputs the audio data cached in the other buffer area, and the process is extremely short in time, can be guaranteed to be completed within ms-level time, and basically does not cause a user to generate auditory difference. And the Zigbee microprocessor caches the audio data segment read from the Flash chip in the buffer area depleted by the current audio data. When the audio data buffered in the buffer area being output is exhausted again, the reading operation of the audio data is executed again, and the process is repeated circularly, so that the audio data section is ensured to be output continuously.
In the solution provided in this embodiment, the Zigbee microprocessor includes a first buffer area and a second buffer area, when one of the first buffer area and the second buffer area is currently performing audio output, the other buffer area buffers audio data segments to be output next, which are read from the Flash chip, and the two buffer areas cyclically execute the above processes until the audio data output is completed. The audio data is output through the ping-pong mode, so that the continuous stream output of the audio data is ensured, and the user experience is greatly improved.
In addition, the embodiment of the invention also provides a control system for audio playing.
In this embodiment, the audio playing control system includes a Zigbee microprocessor, a Flash chip, and an audio DAC chip, where the Zigbee microprocessor is connected to the Flash chip based on a preset SPI interface, and is based on an I simulated by the SPI interface2The S interface is connected with the audio DAC chip, wherein:
the Flash chip is used for feeding back corresponding audio data to the Zigbee microprocessor when receiving a reading command sent by the Zigbee microprocessor;
the Zigbee microprocessor is used for sending a reading command to the Flash chip; when the audio data fed back by the Flash chip are received, the audio data are output to the audio DAC chip;
and the audio DAC chip is used for converting the audio data into corresponding analog audio signals when receiving the audio data, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio.
In this embodiment, the Zigbee microprocessor is preset with an SPI (Serial Peripheral Interface), which is a high-speed, full-duplex, synchronous communication bus and generally includes four lines, namely a CS (chip select) line, a CLK (clock) line, a MISO (input data) line, and a MOSI (output data) line. The SPI interface is often used for external Flash (Flash) chips. In this embodiment, the Zigbee microprocessor is connected to a corresponding Flash chip based on a preset SPI interface thereof, and the Flash chip stores corresponding audio data.
I2The S (Inter-IC Sound, audio bus built in integrated circuit) interface is usually used for accessing a high-quality multimedia audio DAC (Digital to analog converter) chip, I2S also typically includes four lines, a BCLK (bit clock) line, an MCLK (master clock) line, a WS (word select signal) line, and an SDATA (data) line, respectively.
As shown in FIGS. 3 and 4, SPI and I2The clock of S is basically consistent with the logic of the data line, and the output direction is I2S is one WS word select signal and one MCLK main clock signal more than SPI. Among them, some audio DAC chips may automatically generate a matched MCLK main clock signal from a BCLK bit clock signal through an internal PLL (phase locked loop, which is commonly used for a frequency multiplication process of a clock signal) for the MCLK main clock signal, and thus may not supply the MCLK main clock signal. For WS word selection signals, which are used for distinguishing left and right channels of audio data, WS signals can be simulated by using a common IO port through a certain software synchronization means. Therefore, in this embodiment, the SPI interface preset by the Zigbee microprocessor is used to simulate the I2The S interface is connected with a corresponding audio DAC chip, and the Zigbee microprocessor simulates I through the SPI interface2And the S interface outputs audio data to the audio DAC chip. That is, in this embodiment, the Flash chip and the audio DAC chip are accessed simultaneously through the SPI interface multiplexing. Specifically, the CLK and MOSI pins of the SPI interface are connected to both the Flash chip and the audio DAC chip. In addition, the MISO pin of the SPI interface is independently connected to the Flash chip and used for reading the audio data stored in the Flash chip.
Since the CLK clock of the SPI interface maintains a working state, and the CS chip selection of the SPI interface cannot be used, in this embodiment, the Zigbee microprocessor is further provided with a corresponding ordinary IO (input output) interface, and for convenience of description, the IO interface is hereinafter referred to as a first IO interface, and the first IO interface is used to simulate the enabled CS chip selection of the Flash chip. Specifically, the Zigbee microprocessor is connected to the CS chip select signal pin of the Flash chip based on the first IO interface, and simulates the CS chip select signal of the Flash chip. In addition, the Zigbee microprocessor is further provided with another common IO interface, for convenience of description, the another IO interface is hereinafter referred to as a second IO interface, and the second IO interface is adopted to connect a WS word selection signal pin of the audio DAC chip and simulate a WS word selection signal.
Fig. 5 is a schematic diagram of an optional hardware connection structure of the audio playing system according to this embodiment. The Zigbee microprocessor is simultaneously connected with the Flash chip and the audio DAC chip, and the audio DAC chip is connected with the loudspeaker through the corresponding power amplifier.
When audio needs to be played, the Zigbee microprocessor first reads corresponding audio data stored in the Flash chip connected to the Zigbee microprocessor. Optionally, the Zigbee microprocessor enables the CS signal pin of the Flash chip based on the first IO interface, and sends the read command to the Flash chip. When the Flash chip receives the read command, the Flash chip feeds back corresponding audio data to the Zigbee microprocessor. The Zigbee microprocessor receives the audio data fed back by the Flash chip based on the MISO data line of the SPI interface.
And then, the Zigbee microprocessor outputs the read audio data to the audio DAC chip connected with the Zigbee microprocessor. Optionally, because the corresponding code rate, data size, and other audio information of different audio data may be different, before audio playing is performed, the operating frequency of the Zigbee microprocessor is configured first. Specifically, the frame header of the audio data includes audio information such as an audio code rate, channel information, and a data size of the audio data. After the Zigbee microprocessor reads the audio data, the audio information included in the frame header of the audio data is acquired, and then, according to the audio information, the operating frequency of the Zigbee microprocessor is configured to match the playback code rate of the audio data and the switching between the left and right channels.
Optionally, before playing audio, the Zigbee microprocessor pair simulates I2The WS signal of S is phase synchronized. In particular, the amount of the solvent to be used,since the WS signal waveform is very simple, and the high level and the low level have the same time when the number of bits of the left and right channels is the same, the WS signal waveform can be regarded as a 50-50 duty cycle PWM (Pulse Width Modulation) signal waveform. Therefore, in this embodiment, the IO signal of the second IO interface is inverted by using the timer to generate the PWM signal, so as to simulate the WS signal according to the PWM signal. And performing phase synchronization on the simulated WS signal based on a preset PWM synchronization matching value.
As shown in the timing chart of SPI in fig. 3, when SCK is at the rising edge and LSB (Least Significant Bit) is sent, exactly 16 SCK clock cycles have elapsed, and at the same time, the PWM signal needs to be flipped. I.e., the analog WS signal toggles when the rising edge of the LSB bit is transmitted. But I2The WS signal of the S request needs to be flipped half SCK period ahead, i.e. on the falling edge of SCK. Therefore, a PWM synchronization matching value is set so that PWM is synchronized with SPI, that is, phase synchronization of the analog WS signal is achieved.
Optionally, the PWM synchronous matching value is set according to the following preset formula:
the PWM synchronous matching value is equal to the matching value of a timer, half SCK clock number and asynchronous starting time difference;
the timer matching value needs to be obtained by calculation according to the code rate of the output audio, the asynchronous starting time difference refers to the relative time delay of the actual PWM starting and the SPI starting, and needs to be formulated according to a specific program compiling environment, and under the condition that the consistency of hardware environments is ensured, the universal purpose can be achieved.
After the operating frequency of the Zigbee microprocessor is configured and the phase synchronization of the analog WS signal is completed, the Zigbee microprocessor outputs the read audio data to the audio DAC chip.
When the audio DAC chip receives audio data output by the Zigbee microprocessor, the audio data is subjected to digital-to-analog signal conversion processing, the audio data is converted into corresponding analog audio signals, then the generated analog audio signals are transmitted to a power amplifier, and the power amplifier is used for carrying out signal amplification processing and then driving a loudspeaker to play corresponding audio.
In this embodiment, the hardware resources and the processing capability of the Zigbee microprocessor are used, and it is not necessary to additionally extend a complete embedded system (voice playing module) and redevelop a set of independent software modules, so that the cost is reduced. In addition, the Flash chip is adopted to store the audio data, so that the audio data can be updated and expanded, and the quality of the audio output through the audio DAC chip is high, thereby greatly improving the user experience.
In the solution provided by this embodiment, the Zigbee microprocessor connects the Flash chip based on the preset SPI interface, and simulates I based on the SPI interface2The S interface is connected with the audio DAC chip, the Zigbee microprocessor reads audio data stored in the Flash chip based on the SPI interface and bases the audio data on the analog I2And the S interface outputs the audio data to an audio DAC chip, the audio DAC chip converts the received audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio. Because the hardware resources and the processing capacity of the Zigbee microprocessor are utilized, a complete embedded system (a voice playing module) does not need to be additionally expanded and an independent software module does not need to be re-developed, so the cost is reduced; and because the Flash chip is adopted to store the audio data, the updating and the expansion of the audio data are realized, and the quality of the audio output through the audio DAC chip is high, namely the effect of giving consideration to both cost and quality is achieved.
Furthermore, an embodiment of the present invention further provides a computer-readable storage medium, where an audio playback control program is stored on the computer-readable storage medium, and when executed by a processor, the audio playback control program implements the following operations:
the Zigbee microprocessor reads audio data stored in the Flash chip based on the SPI interface;
basing the audio data on I2And the S interface outputs the audio data to an audio DAC chip so that the audio DAC chip converts the audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio.
Further, the audio playing control program, when executed by the processor, further implements the following operations:
the Zigbee microprocessor enables a CS signal pin of the Flash chip based on a first IO interface, and sends a reading command to the Flash chip so that the Flash chip feeds back corresponding audio data when receiving the reading command;
and receiving the audio data fed back by the Flash chip by the MISO input data line based on the SPI interface.
Further, the audio playing control program, when executed by the processor, further implements the following operations:
the Zigbee microprocessor adopts a timer to overturn an IO signal of a second IO interface to generate a PWM (pulse width modulation) signal so as to simulate a WS (WS) signal according to the PWM signal;
and carrying out phase synchronization on the simulated WS signal based on a preset PWM synchronization matching value.
Further, the audio playing control program, when executed by the processor, further implements the following operations:
acquiring audio information contained in a frame header of the audio data;
and configuring the working frequency of the Zigbee microprocessor according to the audio information.
Further, the audio playing control program, when executed by the processor, further implements the following operations:
buffering the audio data in a first buffer and a second buffer;
sequentially basing the audio data buffered in the first buffer and the second buffer on the I2And the S interface outputs the audio DAC chip.
Further, the audio playing control program, when executed by the processor, further implements the following operations:
continuously sending two reading commands to the Flash chip so that the Flash chip can feed back the first two audio data segments of the audio data;
respectively caching the first two sections of audio data in the first buffer area and the second buffer area;
outputting the currently cached audio data segment in the first buffer to the audio DAC chip;
when the output of the currently cached audio data segment in the first buffer area is finished, judging whether the reading of the audio data is finished;
if not, sending a reading command to the Flash chip so that the Flash chip can feed back the next audio data segment of the audio data;
outputting the currently cached audio data segment in the second buffer area to the audio DAC chip; buffering the audio data segment fed back by the Flash chip in the first buffer area;
when the output of the currently cached audio data segment in the second buffer area is finished, judging whether the reading of the audio data is finished;
if not, sending a reading command to the Flash chip so that the Flash chip can feed back the next audio data segment of the audio data; and continuing to return to the step of outputting the currently cached audio data segment in the first buffer area to the audio DAC chip until the audio data is completely read and the output of the audio data segments cached in the first buffer area and the second buffer area is completed.
Further, the audio playing control program, when executed by the processor, further implements the following operations:
when an audio playing instruction is received, data processing of a Zigbee protocol stack is suspended;
and when the audio playing is finished, recovering the data processing of the Zigbee protocol stack.
In the solution provided by this embodiment, the Zigbee microprocessor connects the Flash chip based on the preset SPI interface, and simulates I based on the SPI interface2The S interface is connected with the audio DAC chip, the Zigbee microprocessor reads audio data stored in the Flash chip based on the SPI interface and bases the audio data on the analog I2The S interface outputs to the audio DAC chip, and the audio DAC chip converts the received audio dataAnd generating corresponding analog audio signals, and driving a loudspeaker to play corresponding audio after the analog audio signals are subjected to power amplification processing. Because the hardware resources and the processing capacity of the Zigbee microprocessor are utilized, a complete embedded system (a voice playing module) does not need to be additionally expanded and an independent software module does not need to be re-developed, so the cost is reduced; and because the Flash chip is adopted to store the audio data, the updating and the expansion of the audio data are realized, and the quality of the audio output through the audio DAC chip is high, namely the effect of giving consideration to both cost and quality is achieved.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (12)

1. A control method for audio playing is applied to non-I2The Zigbee protocol microprocessor of the S interface is characterized in that the Zigbee microprocessor is connected with a Flash memory chip based on a preset SPI serial peripheral interface and simulates I based on the SPI interface2The S interface is connected with an audio DAC digital-to-analog conversion chip, and the control method for audio playing comprises the following steps:
the Zigbee microprocessor reads the audio data stored in the Flash chip based on the SPI interface;
i simulating the audio data based on the SPI interface2And the S interface outputs the audio DAC chip so that the audio DAC chip converts the audio data into corresponding analog audio signals, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio.
2. The method for controlling audio playing according to claim 1, wherein the Zigbee microprocessor further includes a first IO input/output interface, and is connected to a CS chip select signal pin of the Flash chip based on the first IO interface, and the step of the Zigbee microprocessor reading the audio data stored in the Flash chip based on the SPI interface includes:
the Zigbee microprocessor enables a CS signal pin of the Flash chip based on the first IO interface, and sends a reading command to the Flash chip so that the Flash chip feeds back corresponding audio data when receiving the reading command;
and receiving the audio data fed back by the Flash chip by the MISO input data line based on the SPI interface.
3. The method for controlling audio playing according to claim 1, wherein the Zigbee microprocessor is capable of controlling audio playing according to the audio playing control methodThe audio DAC chip also comprises a second IO interface which is connected with a WS word selection signal pin of the audio DAC chip based on the second IO interface, and the audio data is based on the I2Before the step of outputting the interface S to the audio DAC chip, the method further comprises the following steps:
the Zigbee microprocessor adopts a timer to overturn the IO signal of the second IO interface to generate a PWM (pulse width modulation) signal so as to simulate a WS signal according to the PWM signal;
and carrying out phase synchronization on the simulated WS signal based on a preset PWM synchronization matching value.
4. The method for controlling audio playback of claim 1, wherein said basing said audio data on said I2Before the step of outputting the interface S to the audio DAC chip, the method further comprises the following steps:
acquiring audio information contained in a frame header of the audio data;
and configuring the working frequency of the Zigbee microprocessor according to the audio information.
5. The method for controlling audio playing according to claim 1, wherein the Zigbee microprocessor further includes a first buffer and a second buffer, and after the step of the Zigbee microprocessor reading the audio data stored in the Flash chip based on the SPI interface, the method further includes:
buffering the audio data in the first buffer and the second buffer;
the audio data is based on the I2The step of outputting the S interface to the audio DAC chip comprises the following steps:
sequentially basing the audio data buffered in the first buffer and the second buffer on the I2And the S interface outputs the audio DAC chip.
6. The method for controlling audio playback of claim 5, wherein the buffer space of the first buffer and the second buffer is set to 4 KB.
7. The method for controlling audio playback of claim 5, wherein the method for controlling audio playback comprises:
continuously sending two reading commands to the Flash chip so that the Flash chip can feed back the first two audio data segments of the audio data;
respectively caching the first two sections of audio data in the first buffer area and the second buffer area;
outputting the currently cached audio data segment in the first buffer to the audio DAC chip;
when the output of the currently cached audio data segment in the first buffer area is finished, judging whether the reading of the audio data is finished;
if not, sending a reading command to the Flash chip so that the Flash chip can feed back the next audio data segment of the audio data;
outputting the currently cached audio data segment in the second buffer area to the audio DAC chip; buffering the audio data segment fed back by the Flash chip in the first buffer area;
when the output of the currently cached audio data segment in the second buffer area is finished, judging whether the reading of the audio data is finished;
if not, sending a reading command to the Flash chip so that the Flash chip can feed back the next audio data segment of the audio data; and continuing to return to the step of outputting the currently cached audio data segment in the first buffer area to the audio DAC chip until the audio data is completely read and the output of the audio data segments cached in the first buffer area and the second buffer area is completed.
8. The method for controlling audio playing according to any one of claims 1 to 7, wherein before the step of the Zigbee microprocessor reading the audio data stored in the Flash chip based on the SPI interface, the method further includes:
when an audio playing instruction is received, data processing of a Zigbee protocol stack is suspended;
the audio data is based on the I2The S interface outputs to the audio DAC chip, so that the audio DAC chip converts the audio data into corresponding analog audio signals, and after the step of driving a speaker to play corresponding audio after the analog audio signals are processed by a power amplifier, the method further includes:
and when the audio playing is finished, recovering the data processing of the Zigbee protocol stack.
9. An apparatus for controlling audio playback, the apparatus comprising: memory, processor and an audio playback control program stored on the memory and executable on the processor, the audio playback control program, when executed by the processor, implementing the steps of the method of controlling audio playback as claimed in any one of claims 1 to 8.
10. A Zigbee microprocessor, wherein the Zigbee microprocessor comprises the control device for audio playing according to claim 9.
11. The audio playing control system is characterized by comprising a Zigbee microprocessor, a Flash chip and an audio DAC chip, wherein the Zigbee microprocessor is connected with the Flash chip based on a preset SPI (serial peripheral interface) and is based on the I simulated by the SPI2The S interface is connected with the audio DAC chip, wherein:
the Flash chip is used for feeding back corresponding audio data to the Zigbee microprocessor when receiving a reading command sent by the Zigbee microprocessor;
the Zigbee microprocessor is used for sending a reading command to the Flash chip; when the audio data fed back by the Flash chip are received, the audio data are output to the audio DAC chip;
and the audio DAC chip is used for converting the audio data into corresponding analog audio signals when receiving the audio data, and the analog audio signals are subjected to power amplification processing and then drive a loudspeaker to play corresponding audio.
12. A computer-readable storage medium, having stored thereon an audio playback control program that, when executed by a processor, implements the steps of the method of controlling audio playback of any one of claims 1-8.
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