CN101937879A - Preparation technique of SiGe Bi-CMOS appliance - Google Patents
Preparation technique of SiGe Bi-CMOS appliance Download PDFInfo
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- CN101937879A CN101937879A CN2009100575243A CN200910057524A CN101937879A CN 101937879 A CN101937879 A CN 101937879A CN 2009100575243 A CN2009100575243 A CN 2009100575243A CN 200910057524 A CN200910057524 A CN 200910057524A CN 101937879 A CN101937879 A CN 101937879A
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Abstract
The invention discloses a preparation technique of a SiGe Bi-CMOS appliance. The step of forming a side wall and a metallic silicide barrier layer of the SiGe Bi-CMOS appliance comprises the following steps of: 1, depositing a dielectric film layer; 2, spin-coating a negative photoresist; 3, exposing with a photomask of the metallic silicide barrier layer to form a metallic silicide barrier layer pattern; 4, etching to form the side wall and removing the dielectric film layer on the non-metallic silicide barrier layer at the same time; 5, growing the dielectric film layer protecting the CMOS appliance; 6, photoetching and etching to open a Si/Ge growth zone; and 7, performing the subsequent Si/Ge appliance forming process. In the invention, the side wall and the metallic silicide barrier layer are formed through photolithography at one time by photoetching the metallic silicide barrier layer with the negative photoresist, so that the process flow is simplified and the yield and reliability of the appliance are improved.
Description
Technical field
The present invention relates to the semiconductor integrated circuit technique field, relate in particular to the technology integrating method of germanium silicon Bi-CMOS in the field of semiconductor technology (Bipolar Complementary Metal Oxide Semiconductor, bipolar complementary metal oxide semiconductor) device.
Background technology
In semiconductor was made, because the Si/Ge band gap is littler than Si, electrons/was faster to producing recombination velocity, can be applied to high speed device.Si/Ge device technology and existing Si ic process compatibility are strong simultaneously.Germanium silicon bipolar (Bipolar) device is a kind of analogue device relatively more commonly used.In order to improve integrated level, people integrate corresponding bipolar device and metal oxide compensated semiconductor (CMOS) device simultaneously, form germanium silicon Bi-CMOS device, are widely used as a kind of analogue device commonly used.
Because simultaneously integrated two kinds of technologies in the germanium silicon Bi-CMOS device, the device that characteristic difference is very big, therefore in the technological process of reality, how to form different devices, how to reduce that interacting of technology is the core process integrated approach of this device between the different components.Carry out high temperature germanium silicon bipolar device technology earlier, form cmos device then, forming the germanium silicon bipolar device at last is wherein a kind of method relatively more commonly used.
No matter take which kind of method, how to form cmos device side wall and blocking layer of metal silicide in the germanium silicon Bi-CMOS device and be one of core procedure that different technology integrating methods need consider, the basic step of its common process is as follows:
(1) media coating deposition; (2) etching forms side wall comprehensively; (3) blocking layer of metal silicide deposition; (4) use the light shield of blocking layer of metal silicide to expose, form the blocking layer of metal silicide figure; (5) etching is removed the media coating at place, non-metallic suicides barrier layer; (6) media coating of growth protection cmos device; (7) the Si/Ge vitellarium is opened in photoetching, etching; (8) follow-up Si/Ge device forms technology.
In the prior art, the technology of formation side wall as shown in Figure 1.Comprise buried regions 2 at germanium silicon bi-pole area, deep trench isolation 1 separates epitaxial loayer 7, comprises the collector electrode 3 of device, and shallow-trench isolation 4 also comprises grid 8 in the middle of source-drain area 5.At first, shown in Fig. 1 (a), at the thicker media coating of the comprehensive deposition rate of germanium silicon bi-pole area and CMOS district; Shown in Fig. 1 (b), by the mode of no light shield dielectric layer is carried out direct etching then, utilize the thicker anisotropic character of side direction deposition medium film, the media coating that other are regional is removed when forming side wall 8; Then, growth blocking layer of metal silicide 6 shown in Fig. 1 (c), and carry out chemical wet etching is opened and need be carried out metal silicide and form the zone, keeps other regional media coatings, forms the blocking layer of metal silicide 6 shown in Fig. 1 (d); Then, carry out follow-up technological process.
Subsequent technique, as shown in Figure 2.At first, represented as Fig. 2 (a), on the basis of above-mentioned technology, comprehensively deposition layer protective layer 10 covers All Ranges above germanium silicon bi-pole area and CMOS district, and this protective layer is generally SiO
2Or SiN, or Si, N, the mixture of O (as SiON) perhaps is doping N, B, P, the SiO of materials such as F
2, this of formation layer protective layer makes that all processing steps can not touch the CMOS zone in the process that the Si/Ge device forms; Then, shown in Fig. 2 (b), adopt photoetching process, open the Si/Ge zone with a light shield, then, etching is removed all levels of silicon face, and the photoresist among Fig. 2 (b) is the protective layer of cmos device, can form the back at the Si/Ge device and Remove All; Then, remove the structure of photoresist formation shown in Fig. 2 (c) among Fig. 2 (b), carry out follow-up Si/Ge device and form technology
This existing common processes step is very loaded down with trivial details, causes the flow time of germanium silicon Bi-CMOS device and production cost all very high, and positive photoresist forms small developing defect easily for the large area exposure zone in this technology.For common non-Si/Ge device, design principle from blocking layer of metal silicide, the commonplace components blocking layer of metal silicide zone of opening if desired all is the zone that will form metal silicide, therefore from the circuit board area of pictural surface, the area of opening is very little, can not have the large area exposure zone.Simultaneously for commonplace components, follow-up technology is used Ti, metal electrode material such as Co at high temperature form the node of metallic compound as line with Si, even therefore exist small developing defect also can not influence the material character of the metal suicide electrodes of final formation.But when the Si/Ge device is formed; in the Si/Ge district in order to remove protective layer; carry out follow-up Si/Ge epitaxial growth; this moment is from domain; can open all Si/Ge device areas; and therefore the area of Si/Ge device needs large area exposure much larger than CMOS, is easy to generate developing defect this moment.And follow-up Si/Ge epitaxy technique is a kind of very strict molecule epitaxial growth along the crystal orientation, and any minute defects all can cause lattice defect to cause device property to change.Therefore for needing extra cleaning step to remove this type of tiny flaw in the common Si/Ge technology.
Summary of the invention
Technical problem to be solved by this invention provides a kind of germanium silicon Bi-CMOS device preparation technology, can reduce germanium silicon Bi-CMOS device and generate the technology cost, and reduce the follow-up germanium and silicon epitaxial layer growth defective that relevant developing defect causes, improve the rate of finished products and the reliability of device.
For solving the problems of the technologies described above, the technical scheme of germanium silicon Bi-CMOS device preparation technology of the present invention is that the side wall and the blocking layer of metal silicide that form germanium silicon Bi-CMOS device may further comprise the steps:
1) at first, at whole germanium silicon bi-pole area and comprehensive deposition medium rete above the CMOS district;
2) then, spin coating negative photoresist on media coating;
3) use the light shield of blocking layer of metal silicide to expose, form the blocking layer of metal silicide figure;
4) etching, the side wall of formation cmos device is removed the media coating at place, non-metallic suicides barrier layer simultaneously;
5) media coating of growth protection cmos device;
6) the Si/Ge vitellarium is opened in photoetching, etching;
7) follow-up Si/Ge device forms technology.
Be before step 4), to increase by a step developing process as a further improvement on the present invention.
As another kind of further improvement of the present invention is to increase by a step wet clean step before step 4).
Germanium silicon Bi-CMOS device preparation technology of the present invention is when the blocking layer of metal silicide of side wall that forms CMOS and germanium silicon bipolar device, adopted negative photoresist to carry out the blocking layer of metal silicide photoetching, directly carry out etching then, thereby form side wall and blocking layer of metal silicide by a chemical wet etching, simplify technological process, reduce defective workmanship, improve the rate of finished products and the reliability of device.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 forms the schematic flow sheet of germanium silicon Bi-CMOS device side wall for prior art;
Fig. 2 forms germanium silicon Bi-CMOS device metal silicide barrier layer schematic flow sheet for prior art;
Fig. 3 forms the side wall and the blocking layer of metal silicide schematic flow sheet of germanium silicon Bi-CMOS device for the present invention;
Fig. 4 is a flow chart of the present invention.
Reference numeral is among the figure:
1 is dark isolated area, and 2 is buried regions, and 3 is the draw-out area of collector electrode, and 4 is shallow separator, and 5 is source-drain area, and 6 is blocking layer of metal silicide, and 7 is epitaxial loayer, and 8 is grid, and 9 is dielectric layer, and 10 is protective layer, and 11 is collector electrode.
Embodiment
As shown in Figure 4, germanium silicon Bi-CMOS device preparation technology of the present invention may further comprise the steps when side wall that forms germanium silicon Bi-CMOS device and blocking layer of metal silicide:
At first, on silicon substrate, form the substrate and the doped region of conventional germanium silicon device, comprise buried regions 2 at germanium silicon bi-pole area, deep trench isolation 1 separates epitaxial loayer 7, the collector electrode 11 that comprises device, collector electrode draw-out area 3, shallow-trench isolation 4, the grid 8 that also comprises the COMS device perhaps also can be finished LDD and source leakage injection formation source-drain area 5 earlier in some cases.
Shown in Fig. 3 (a), deposition medium rete above whole germanium silicon device and cmos device, deielectric-coating can for oxide (as SiO
2) or nitride (as SiN), the mixed layer (ONO-SiO of also aerobic nitrogen mixture (SiON), or these materials
2/ SiN/SiO
2Sandwich structure), or contain B, the oxide of F or P, or carbide (SiC), the thickness of deielectric-coating is 10
-10000
Can adopt PVD (Physical Vapor Deposition, physical vapour deposition (PVD)) or CVD (ChemicalVapor Deposition, chemical vapour deposition (CVD)), also can use ALD (atomic layerdeposition, atomic layer deposition) etc. deposition medium film 9 can adopt high pressure, normal pressure or reduced pressure deposition deielectric-coating.
Secondly, shown in Fig. 3 (b), the spin coating negative photoresist on whole media coating uses the light shield of blocking layer of metal silicide to expose, carry out SB (Silicide Block) (metal silicide stops) photoetching, remove the media coating that Si/Ge zone and SB form the zone.Utilize the exposure that do not need of negative photoresist just can be removed characteristic simultaneously, guarantee the low defective in Si/Ge exposure back.
Then, shown in Fig. 3 (c), etching forms side wall, removes the media coating 9 at place, non-metallic suicides barrier layer simultaneously, forms the blocking layer of metal silicide figure.Keep the media coating 9 of place everywhere, this regional media coating does not need to remove especially.In addition, the utmost point electrode place in Si/Ge district does not need specifically created metal silicide region yet, so the SB layer can keep off and can not keep off.
Then, shown in Fig. 3 (d), the media coating of the protection cmos device of above whole germanium silicon device and cmos device, comprehensively growing up
Then, shown in Fig. 3 (e), above whole germanium silicon device and cmos device, be coated with photoresist, adopt photoetching process to carry out chemical wet etching, remove the protective layer on surface, Si/Ge district, open the Si/Ge vitellarium.
At last, shown in Fig. 3 (f), follow-up Si/Ge device forms technology, forms germanium silicon bipolar CMOS device.
Simultaneously, also can mix to 7 by injection technology after this for collector electrode 11 and collector electrode draw-out area 3, annealing forms then, perhaps can further inject 3 and 11 in follow-up technology, improves resistance, improves device performance.
In the present invention, the top, place of Si/Ge device periphery does not have blocking layer of metal silicide, and on the Si/Ge place, other zones all protected seam are covered with.Unless the etch step that etches into the place is arranged in the follow-up technology.
Germanium silicon Bi-CMOS device preparation technology of the present invention, when side wall in preparation germanium silicon Bi-CMOS device and blocking layer of metal silicide, adopt negative photoresist to carry out the blocking layer of metal silicide photoetching, directly carry out etching then, thereby form side wall and blocking layer of metal silicide by a chemical wet etching.
Use the inventive method, can simplify technological process, use by negative photoresist simultaneously, reduce the developing defect that positive photoresist forms easily for the large area exposure zone in the common process, thereby reduce the follow-up germanium and silicon epitaxial layer growth defective that relevant developing defect causes, improve the rate of finished products and the reliability of device.
Claims (8)
1. a germanium silicon Bi-CMOS device preparation technology is characterized in that, the side wall and the blocking layer of metal silicide that form germanium silicon Bi-CMOS device may further comprise the steps:
1) at first, at whole germanium silicon bi-pole area and comprehensive deposition medium rete above the CMOS district;
2) then, spin coating negative photoresist on media coating;
3) use the light shield of blocking layer of metal silicide to expose, form the blocking layer of metal silicide figure;
4) etching, the side wall of formation cmos device is removed the media coating at place, non-metallic suicides barrier layer simultaneously;
5) media coating of growth protection cmos device;
6) the Si/Ge vitellarium is opened in photoetching, etching;
7) follow-up Si/Ge device forms technology.
2. germanium silicon Bi-CMOS device preparation technology according to claim 1 is characterized in that the deielectric-coating that deposits in the step 1) is SiO
2The combination of perhaps SiN, or oxide and nitride.
3. germanium silicon Bi-CMOS device preparation technology according to claim 2 is characterized in that the deielectric-coating that deposits in the step 1) is for containing B, the oxide of F or P, or carborundum.
4. germanium silicon Bi-CMOS device preparation technology according to claim 2 is characterized in that the deielectric-coating that deposits in the step 1) is an ONO sandwich structure.
5. germanium silicon Bi-CMOS device preparation technology according to claim 1 is characterized in that the deielectric-coating thickness 10 that deposits in the step 1)
-10000
6. germanium silicon Bi-CMOS device preparation technology according to claim 1 is characterized in that, increases by a step developing process before step 4).
7. germanium silicon Bi-CMOS device preparation technology according to claim 1 is characterized in that, increases by a step wet clean step before step 4).
8. germanium silicon Bi-CMOS device preparation technology according to claim 1 is characterized in that, adopts PVD or CVD in step 1) and the step 5), also can make ALD deposition medium film.
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| CN101937879B CN101937879B (en) | 2012-10-03 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184898A (en) * | 2011-04-22 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for manufacturing semiconductor device and method for manufacturing SiGe HBT (Heterojunction Bipolar Transistor) |
| CN102956475A (en) * | 2011-08-23 | 2013-03-06 | 上海华虹Nec电子有限公司 | Preparation method of cross-polycrystalline silicon layer of Si-Ge bi-polar CMOS (complementary metal oxide semiconductor) |
| CN105428320A (en) * | 2015-12-17 | 2016-03-23 | 重庆中科渝芯电子有限公司 | Method for protecting active region of heterojunction bipolar transistor (HBT) in SiGe bipolar complementary metal oxide semiconductor (BiCMOS) process |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7488662B2 (en) * | 2005-12-13 | 2009-02-10 | Chartered Semiconductor Manufacturing, Ltd. | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process |
-
2009
- 2009-06-30 CN CN200910057524A patent/CN101937879B/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184898A (en) * | 2011-04-22 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for manufacturing semiconductor device and method for manufacturing SiGe HBT (Heterojunction Bipolar Transistor) |
| CN102184898B (en) * | 2011-04-22 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device and method for manufacturing SiGe HBT (Heterojunction Bipolar Transistor) |
| CN102956475A (en) * | 2011-08-23 | 2013-03-06 | 上海华虹Nec电子有限公司 | Preparation method of cross-polycrystalline silicon layer of Si-Ge bi-polar CMOS (complementary metal oxide semiconductor) |
| CN102956475B (en) * | 2011-08-23 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Preparation method of cross-polycrystalline silicon layer of Si-Ge bi-polar CMOS (complementary metal oxide semiconductor) |
| CN105428320A (en) * | 2015-12-17 | 2016-03-23 | 重庆中科渝芯电子有限公司 | Method for protecting active region of heterojunction bipolar transistor (HBT) in SiGe bipolar complementary metal oxide semiconductor (BiCMOS) process |
| CN105428320B (en) * | 2015-12-17 | 2017-12-22 | 重庆中科渝芯电子有限公司 | A kind of method that HBT active areas are protected in SiGe BiCMOS techniques |
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| CN101937879B (en) | 2012-10-03 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131218 |
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Effective date of registration: 20131218 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |