CN101937879B - Preparation technique of SiGe Bi-CMOS appliance - Google Patents
Preparation technique of SiGe Bi-CMOS appliance Download PDFInfo
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- CN101937879B CN101937879B CN200910057524A CN200910057524A CN101937879B CN 101937879 B CN101937879 B CN 101937879B CN 200910057524 A CN200910057524 A CN 200910057524A CN 200910057524 A CN200910057524 A CN 200910057524A CN 101937879 B CN101937879 B CN 101937879B
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Abstract
The invention discloses a preparation technique of a SiGe Bi-CMOS appliance. The step of forming a side wall and a metallic silicide barrier layer of the SiGe Bi-CMOS appliance comprises the following steps of: 1, depositing a dielectric film layer; 2, spin-coating a negative photoresist; 3, exposing with a photomask of the metallic silicide barrier layer to form a metallic silicide barrier layer pattern; 4, etching to form the side wall and removing the dielectric film layer on the non-photoresist area at the same time; 5, growing the dielectric film layer protecting the CMOS appliance; 6, photoetching and etching to open a germanium-silicaon alloy growth zone; and 7, performing the subsequent germanium-silicaon alloy appliance forming process. In the invention, the side wall and the metallic silicide barrier layer are formed through photolithography at one time by photoetching the metallic silicide barrier layer with the negative photoresist, so that the process flow is simplified and the yield and reliability of the appliance are improved.
Description
Technical field
The present invention relates to the semiconductor integrated circuit technique field; Relate in particular to the technology integrating method of germanium silicon Bi-CMOS in the field of semiconductor technology (Bipolar Complementary Metal Oxide Semiconductor, bipolar complementary metal oxide semiconductor) device.
Background technology
In semiconductor was made, because the germanium-silicon alloy band gap is littler than Si, electrons/was faster to producing recombination velocity, can be applied to high speed device.Germanium-silicon alloy device technology and existing Si ic process compatibility property are strong simultaneously.Germanium silicon bipolar (Bipolar) device is a kind of analogue device relatively more commonly used.In order to improve integrated level, people integrate corresponding bipolar device and metal oxide compensated semiconductor (CMOS) device simultaneously, form germanium silicon Bi-CMOS device, are widely used as a kind of analogue device commonly used.
Because simultaneously integrated two kinds of technologies in the germanium silicon Bi-CMOS device; The device that characteristic difference is very big; Therefore in the technological process of reality, how to form different devices, how to reduce that interacting of technology is the core process integrated approach of this device between the different components.Carry out high temperature germanium silicon bipolar device technology earlier, form cmos device then, forming the germanium silicon bipolar device at last is wherein a kind of method relatively more commonly used.
No matter take which kind of method, how to form cmos device side wall and blocking layer of metal silicide in the germanium silicon Bi-CMOS device and be one of core procedure that the different processes integrated approach need consider, the basic step of its common process is following:
(1) media coating deposition; (2) etching forms side wall comprehensively; (3) blocking layer of metal silicide deposition; (4) use the light shield of blocking layer of metal silicide to make public, form the blocking layer of metal silicide figure; (5) etching is removed the media coating that does not have the blocking layer of metal silicide place; (6) media coating of growth protection cmos device; (7) the germanium-silicon alloy vitellarium is opened in photoetching, etching; (8) follow-up germanium-silicon alloy device forms technology.
In the prior art, the technology of formation side wall is as shown in Figure 1.Comprise buried regions 2 at germanium silicon bi-pole area, deep trench isolation 1 separates epitaxial loayer 7, comprises the collector electrode 3 of device, and shallow-trench isolation 4 also comprises grid 8 in the middle of source-drain area 5.At first, shown in Fig. 1 (a), at the thicker media coating of the comprehensive deposition rate of germanium silicon bi-pole area and CMOS district; Shown in Fig. 1 (b), through the mode of no light shield dielectric layer is carried out direct etching then, utilize the thicker anisotropic character of side direction deposition medium film, the media coating that other are regional is removed when forming side wall 8; Then, growth blocking layer of metal silicide 6 shown in Fig. 1 (c), and carry out chemical wet etching is opened and need be carried out metal silicide and form the zone, keeps other regional media coatings, forms the blocking layer of metal silicide 6 shown in Fig. 1 (d); Then, carry out follow-up technological process.
Subsequent technique, as shown in Figure 2.At first, represented like Fig. 2 (a), on the basis of above-mentioned technology, comprehensively deposition layer protective layer 10 covers All Ranges above germanium silicon bi-pole area and CMOS district, and this protective layer is generally SiO
2Or SiN, or Si, N, the mixture of O (like SiON) perhaps is doping N, B, P, the SiO of materials such as F
2, this of formation layer protective layer makes that all processing steps can not touch the CMOS zone in the process that the germanium-silicon alloy device forms; Then, shown in Fig. 2 (b), adopt photoetching process, open the germanium-silicon alloy zone with a light shield, then, etching is removed all levels of silicon face, and the photoresist among Fig. 2 (b) is the protective layer of cmos device, can form the back at the germanium-silicon alloy device and Remove All; Then, the photoresist of removing among Fig. 2 (b) forms the structure shown in Fig. 2 (c), carries out follow-up germanium-silicon alloy device and forms technology
This existing common processes step is very loaded down with trivial details, causes the flow time of germanium silicon Bi-CMOS device and production cost all very high, and positive photoresist forms small developing defect easily for the large area exposure zone in this technology.For common non-germanium-silicon alloy device; Design principle from blocking layer of metal silicide; The commonplace components blocking layer of metal silicide zone of opening if desired all is the zone that will form metal silicide; Therefore from the circuit board area of pictural surface, the area that institute will open is very little, can not exist large area exposure regional.Simultaneously for commonplace components; Follow-up technology is used Ti; Metal electrode material such as Co at high temperature form the node of metallic compound as line with Si, even therefore exist small developing defect also can not influence the material character of the metal suicide electrodes of final formation.But when the germanium-silicon alloy device is formed; In order to remove protective layer, carry out follow-up germanium-silicon alloy epitaxial growth in the germanium-silicon alloy district, this moment is from domain; Can open all germanium-silicon alloy device areas; And therefore the area of germanium-silicon alloy device needs large area exposure much larger than CMOS, is easy to generate developing defect this moment.And follow-up germanium-silicon alloy epitaxy technique is a kind of very strict molecule epitaxial growth along the crystal orientation, and any minute defects all can cause lattice defect to cause device property to change.Therefore for needing extra cleaning step to remove this type of tiny flaw in the common germanium-silicon alloy technology.
Summary of the invention
Technical problem to be solved by this invention provides a kind of germanium silicon Bi-CMOS device preparation technology; Can reduce germanium silicon Bi-CMOS device and generate the technology cost; And reduce the follow-up germanium and silicon epitaxial layer growth defective that relevant developing defect causes, improve the rate of finished products and the reliability of device.
For solving the problems of the technologies described above, the technical scheme of germanium silicon Bi-CMOS device preparation technology of the present invention is that the side wall and the blocking layer of metal silicide that form germanium silicon Bi-CMOS device may further comprise the steps:
1) at first, at whole germanium silicon bi-pole area and comprehensive deposition medium rete above the CMOS district;
2) then, spin coating negative photoresist on media coating;
3) use the light shield of blocking layer of metal silicide to make public, form the blocking layer of metal silicide figure;
4) etching, the side wall of formation cmos device is removed the media coating that does not have the photoresist zone simultaneously;
5) media coating of growth protection cmos device;
6) photoetching, the etching media coating is to open the germanium-silicon alloy vitellarium;
7) follow-up germanium-silicon alloy device forms technology.
Be between step 3) and step 4), to increase by a step developing process as further improvement of the present invention.
As another kind of further improvement of the present invention is between step 3) and step 4), to increase by a step wet clean step.
Germanium silicon Bi-CMOS device preparation technology of the present invention is when the blocking layer of metal silicide of side wall that forms CMOS and germanium silicon bipolar device; Adopted negative photoresist to carry out the blocking layer of metal silicide photoetching; Directly carry out etching then, thereby form side wall and blocking layer of metal silicide, simplify technological process through a chemical wet etching; Reduce defective workmanship, improve the rate of finished products and the reliability of device.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 forms the schematic flow sheet of germanium silicon Bi-CMOS device side wall for prior art;
Fig. 2 forms germanium silicon Bi-CMOS device metal silicide barrier layer schematic flow sheet for prior art;
Fig. 3 forms the side wall and the blocking layer of metal silicide schematic flow sheet of germanium silicon Bi-CMOS device for the present invention;
Fig. 4 is a flow chart of the present invention.
Reference numeral is among the figure:
1 is dark isolated area, and 2 is buried regions, and 3 is the draw-out area of collector electrode, and 4 is shallow separator, and 5 is source-drain area, and 6 is blocking layer of metal silicide, and 7 is epitaxial loayer, and 8 is grid, and 9 is dielectric layer, and 10 is protective layer, and 11 is collector electrode.
Embodiment
As shown in Figure 4, germanium silicon Bi-CMOS device preparation technology of the present invention may further comprise the steps when side wall that forms germanium silicon Bi-CMOS device and blocking layer of metal silicide:
At first, on silicon substrate, form the substrate and the doped region of conventional germanium silicon device, comprise buried regions 2 at germanium silicon bi-pole area; Deep trench isolation 1 separates epitaxial loayer 7; The collector electrode 11 that comprises device, collector electrode draw-out area 3, shallow-trench isolation 4; The grid 8 that also comprises the COMS device perhaps also can be accomplished LDD and source leakage injection formation source-drain area 5 earlier in some cases.
Shown in Fig. 3 (a), deposition medium rete above whole germanium silicon device and cmos device, deielectric-coating can for oxide (like SiO
2) or nitride (like SiN), the mixed layer (ONO-SiO of also aerobic nitrogen mixture (SiON), or these materials
2/ SiN/SiO
2Sandwich structure), or contain B, the oxide of F or P, or carbide (SiC), the thickness of deielectric-coating does
Can adopt PVD (Physical Vapor Deposition; Physical vapour deposition (PVD)) or CVD (Chemical Vapor Deposition; Chemical vapour deposition (CVD)), also can use ALD deposition medium films 9 such as (atomic layer deposition, atomic layer depositions); Can adopt high pressure, normal pressure or reduced pressure deposition deielectric-coating.
Secondly; Shown in Fig. 3 (b), the spin coating negative photoresist on whole media coating uses the light shield of blocking layer of metal silicide to make public; Carry out SB (Silicide Block) (metal silicide stops) photoetching, remove the media coating that germanium-silicon alloy zone and SB form the zone.Utilize need not making public of negative photoresist just can be removed characteristic simultaneously, guarantee the low defective in germanium-silicon alloy exposure back.
Then, shown in Fig. 3 (c), etching forms side wall, removes the media coating 9 that does not have the photoresist place simultaneously, forms the blocking layer of metal silicide figure.Keep the media coating 9 of place everywhere, this regional media coating does not need to remove especially.In addition, the utmost point electrode in germanium-silicon alloy district does not need specifically created metal silicide region yet, so the SB layer can keep off and can not keep off.
Then, shown in Fig. 3 (d), the media coating of the protection cmos device of above whole germanium silicon device and cmos device, comprehensively growing up
Then, shown in Fig. 3 (e), above whole germanium silicon device and cmos device, be coated with photoresist, adopt photoetching process to carry out chemical wet etching, remove the protective layer on surface, germanium-silicon alloy district, open the germanium-silicon alloy vitellarium.
At last, shown in Fig. 3 (f), follow-up germanium-silicon alloy device forms technology, forms germanium silicon bipolar CMOS device.
Simultaneously, also can mix to 7 through injection technology after this for collector electrode 11 and collector electrode draw-out area 3, annealing forms then, perhaps can in follow-up technology, further inject 3 and 11, improves resistance, improves device performance.
In the present invention, the top, place of germanium-silicon alloy device periphery does not have blocking layer of metal silicide, and on the germanium-silicon alloy place, other zones all protected seam are covered with.Only if the etch step that etches into the place is arranged in the follow-up technology.
Germanium silicon Bi-CMOS device preparation technology of the present invention; When side wall in preparation germanium silicon Bi-CMOS device and blocking layer of metal silicide; Adopt negative photoresist to carry out the blocking layer of metal silicide photoetching; Directly carry out etching then, thereby form side wall and blocking layer of metal silicide through a chemical wet etching.
Use the inventive method; Can simplify technological process; Use through negative photoresist simultaneously; Reduce the developing defect that positive photoresist forms for the large area exposure zone easily in the common process, thereby reduce the follow-up germanium and silicon epitaxial layer growth defective that relevant developing defect causes, improve the rate of finished products and the reliability of device.
Claims (8)
1. a germanium silicon Bi-CMOS device preparation technology is characterized in that, the side wall and the blocking layer of metal silicide that form germanium silicon Bi-CMOS device may further comprise the steps:
1) at first, at whole germanium silicon bi-pole area and comprehensive deposition medium rete above the CMOS district;
2) then, spin coating negative photoresist on media coating;
3) use the light shield of blocking layer of metal silicide to make public, form the blocking layer of metal silicide figure;
4) etching, the side wall of formation cmos device is removed the media coating that does not have the photoresist zone simultaneously;
5) media coating of growth protection cmos device;
6) photoetching, the etching media coating is to open the germanium-silicon alloy vitellarium;
7) follow-up germanium-silicon alloy device forms technology.
2. germanium silicon Bi-CMOS device preparation technology according to claim 1 is characterized in that the deielectric-coating that deposits in the step 1) is SiO
2The combination of perhaps SiN, or oxide and nitride.
3. germanium silicon Bi-CMOS device preparation technology according to claim 1 is characterized in that the deielectric-coating that deposits in the step 1) is for containing B, the oxide of F or P, or carborundum.
4. germanium silicon Bi-CMOS device preparation technology according to claim 2 is characterized in that the deielectric-coating that deposits in the step 1) is an ONO sandwich structure.
5. germanium silicon Bi-CMOS device preparation technology according to claim 1; It is characterized in that the deielectric-coating thickness that deposits in the step 1)
6. germanium silicon Bi-CMOS device preparation technology according to claim 1 is characterized in that, between step 3) and step 4), increases by a step developing process.
7. germanium silicon Bi-CMOS device preparation technology according to claim 1 is characterized in that, between step 3) and step 4), increases by a step wet clean step.
8. germanium silicon Bi-CMOS device preparation technology according to claim 1 is characterized in that, adopts PVD or CVD or ALD deposition medium film in step 1) and the step 5).
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| CN102184898B (en) * | 2011-04-22 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device and method for manufacturing SiGe HBT (Heterojunction Bipolar Transistor) |
| CN102956475B (en) * | 2011-08-23 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Preparation method of cross-polycrystalline silicon layer of Si-Ge bi-polar CMOS (complementary metal oxide semiconductor) |
| CN105428320B (en) * | 2015-12-17 | 2017-12-22 | 重庆中科渝芯电子有限公司 | A kind of method that HBT active areas are protected in SiGe BiCMOS techniques |
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| US7488662B2 (en) * | 2005-12-13 | 2009-02-10 | Chartered Semiconductor Manufacturing, Ltd. | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process |
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| US7488662B2 (en) * | 2005-12-13 | 2009-02-10 | Chartered Semiconductor Manufacturing, Ltd. | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131218 |
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Effective date of registration: 20131218 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |