CN101937867A - Method for improving membrane thickness homogeneity of dielectric layer in manufacturing process of semiconductor metal line - Google Patents
Method for improving membrane thickness homogeneity of dielectric layer in manufacturing process of semiconductor metal line Download PDFInfo
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- CN101937867A CN101937867A CN2009100575192A CN200910057519A CN101937867A CN 101937867 A CN101937867 A CN 101937867A CN 2009100575192 A CN2009100575192 A CN 2009100575192A CN 200910057519 A CN200910057519 A CN 200910057519A CN 101937867 A CN101937867 A CN 101937867A
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Abstract
The invention discloses a method for improving the membrane thickness homogeneity of a dielectric layer in the manufacturing process of a semiconductor metal line. The method comprises the following steps of: depositing a first dielectric layer after manufacturing the metal line; then depositing a barrier layer on the first dielectric layer and depositing a second dielectric layer on the barrier layer, wherein the lowest place of the second dielectric layer is higher than the highest place of the barrier layer; and then performing chemically mechanical polishing, wherein the barrier layer has high selection ratio to the second dielectric layer in the proceeding chemically mechanical polishing so that the surface subjected to the chemically mechanical polishing is remained at the highest place of the barrier layer. The invention ensures that the performing of the chemically mechanical polishing can be stopped on the barrier layer when the dielectric layer is ground so that the chemically mechanical polishing process fluctuation caused by material consumption and variation of the technical parameters is effectively eliminated, the restriction of the property of the chemically mechanical polishing per se is overcame to a certain degree and the membrane thickness homogeneity between the silicon wafer surface subjected to the chemically mechanical polishing and the silicon wafer of the dielectric layer is improved.
Description
Technical field
The present invention relates to a kind of semiconductor technology method, improve the method for dielectric layer thickness homogeneity in especially a kind of semiconductor alloy line manufacture craft.
Background technology
(Back-End-Of-Line BEOL) in the processing procedure, generally needs multi-layer metal wiring, is separated by dielectric layer between the last lower metal layer and connects by through hole in road behind semiconductor.Concrete manufacturing process is generally: as Fig. 1～shown in Figure 3, after etching metal connecting line layer 1, dielectric layer deposited 2 on metal connecting line layer 1, as shown in Figure 2, pass through CMP (Chemical Mechanical Polishing, chemico-mechanical polishing) planarization then, as shown in Figure 3, etching through hole on dielectric layer is the filling and the chemico-mechanical polishing thereof of via metal (as tungsten) then again, afterwards one metal connecting line layer after the deposit again.As shown in Figure 2, dielectric layer 2 depositing technics can keep the difference of height (Step-height) between figure that lower metal line etching forms, this difference of height must be eliminated by CMP (Chemical Mechanical Polishing) process, otherwise can be to follow-up photoetching, technologies such as etching and metal deposit cause the difficulty that is difficult to overcome.Consumptive material and technological parameter that CMP (Chemical Mechanical Polishing) process relates to are a lot, and wherein consumptive material comprises grinding pad (pad), grinding head (head), grinding pad correction-plate (conditioning disk), lapping liquid (slurry) etc.Useful life that these consumptive materials are had nothing in common with each other and replacement cycle.Its technological parameter, as the lapping liquid flow, pressure etc. sometimes also can the off-design value.The technology controlling and process of CMP (Chemical Mechanical Polishing) process and stability are subjected to the restriction of these consumptive materials and changes in process parameters to a great extent and are difficult to improve.In addition, because the restriction of chemico-mechanical polishing self-characteristic is difficult to make the grinding rate of zones of different in the silicon chip face to be consistent,, also be difficult to guarantee the thickness homogeneity in the silicon chip face even therefore under consumptive material and the duplicate situation of technological parameter.With regard to prior art, after the chemico-mechanical polishing in the silicon chip face and between the different silicon chips the thick variation of film reach sometimes the actual needs thickness 1/3rd or bigger.Thereby the exploitation of sophisticated semiconductor processing procedure and the raising of volume production product yield are caused obstacle.And along with dwindling of dimensions of semiconductor devices and tightening up of design specification, this obstructive action is more and more serious.
Summary of the invention
Technical problem to be solved by this invention provides the method for improving dielectric layer thickness homogeneity in a kind of semiconductor alloy line manufacture craft, can overcome the restriction of chemico-mechanical polishing self-characteristic, improve after the dielectric layer chemico-mechanical polishing in the silicon chip face and the thickness homogeneity between the silicon chip.
For solving the problems of the technologies described above, the technical scheme of improving the method for dielectric layer thickness homogeneity in the semiconductor alloy line manufacture craft of the present invention is, after making metal connecting line, deposit first dielectric layer, deposit one deck barrier layer on described first dielectric layer then, deposit second dielectric layer on described barrier layer again, the lowest part of described second dielectric layer will be higher than the highest point on described barrier layer, carry out chemico-mechanical polishing afterwards, in the chemico-mechanical polishing that carry out in the back on described barrier layer described second dielectric layer is had high selectivity, make the surface after the chemico-mechanical polishing rest on the highest point on described barrier layer.
The present invention is by increasing deposit one deck has high selectivity to interlayer dielectric layer in CMP (Chemical Mechanical Polishing) process barrier layer between metal interlayer medium, chemico-mechanical polishing can be parked on this barrier layer, the CMP (Chemical Mechanical Polishing) process fluctuation that causes because of the variation of consumptive material and technological parameter with effective elimination in the abrasive media layer.Simultaneously owing to the chemico-mechanical polishing grinding is parked on the barrier layer, internal homogeneity when the internal homogeneity of residual-film thickness degree depends primarily on interlayer dielectric layer deposit below the chemico-mechanical polishing barrier layer, thereby to a certain extent overcome the restriction of chemico-mechanical polishing self-characteristic, improved after the dielectric layer chemico-mechanical polishing in the silicon chip face and the thickness homogeneity between the silicon chip.The barrier layer that increases deposit provides convenience can for simultaneously the end point determination of interlayer dielectric layer chemico-mechanical polishing, improves the stability of CMP (Chemical Mechanical Polishing) process.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1～Fig. 3 is for improving the schematic diagram of the method for dielectric layer thickness homogeneity in the conventional semiconductor metal connecting line manufacture craft;
Fig. 4～Fig. 8 is for improving the schematic diagram of the method for dielectric layer thickness homogeneity in the semiconductor alloy line manufacture craft of the present invention
Reference numeral is among the figure, 1. the metal connecting line layer; 2. dielectric layer; 3. first dielectric layer; 4. separator; 5. second dielectric layer.
Embodiment
The invention discloses the method for improving dielectric layer thickness homogeneity in a kind of semiconductor alloy line manufacture craft, after making metal connecting line 1 as shown in Figure 4, deposit first dielectric layer 3, as shown in Figure 5, deposit one deck barrier layer 4 on described first dielectric layer 3 then, as shown in Figure 6, deposit second dielectric layer 5 on described barrier layer 4 again, as shown in Figure 7, the lowest part of described second dielectric layer 5 will be higher than the highest point on described barrier layer 4, carry out chemico-mechanical polishing afterwards, in the chemico-mechanical polishing that carry out in the back on described barrier layer 4 described second dielectric layer 5 is had high selectivity, make the surface after the chemico-mechanical polishing rest on the highest point on described barrier layer 4.
Described first dielectric layer 3 is pure SiO
2, or the SiO of one or more impurity elements among doping P, B, the F
2, its depositing technics can be that PE-CVD (plasma enhanced CVD), AP-CVD (normal pressure chemical vapor deposition) or LP-CVD (low-pressure chemical vapor phase deposition) thickness range are 100～10000
Described barrier layer 4 is SiON or SiN, and its depositing technics can be PE-CVD, AP-CVD, and LP-CVD, thickness range are 10～3000
Described second dielectric layer 5 is pure SiO
2, or the SiO of one or more impurity elements among doping P, B, the F
2, its depositing technics can be PE-CVD, AP-CVD or LP-CVD, thickness range are 100～10000
The set time that is controlled to be of described chemico-mechanical polishing is controlled, and perhaps is end point determination control.
According to the optics in silicon chip surface or the CMP (Chemical Mechanical Polishing) process process, machinery, variations in temperature, the end-point detection method of element-specific or compound test.
In CMP (Chemical Mechanical Polishing) process, when from a kind of membranous thin-film grinding to another membranous film the time, the optics of silicon chip surface, machinery (friction) performance, temperature, grinding produce element and the compound that thing comprised and all can change, and these changes can both be detected by specific detecting instrument.After detecting instrument detects these and changes, can give grinding system these feedback information, make system stop automatically grinding, thereby rest on the thin layer of lower floor, Here it is end-point detection method.In the shallow-trench isolation chemical mechanical milling tech (STI chemico-mechanical polishing) at present, chemico-mechanical polishing is to be ground to silicon nitride layer from silicon dioxide layer, after being ground to silicon nitride layer, system utilizes laser acquisition to arrive the optical change of silicon chip surface, thereby stop automatically grinding, process of lapping can be rested on the silicon nitride layer.
In the present invention, the membranous of barrier layer and dielectric layer also is different.When chemico-mechanical polishing after dielectric layer is ground to the barrier layer, system can detect the variation (mode that depends on end point determination) of the said various physicochemical characteristicss in front, thereby stops to grind, and stops on the barrier layer.
The present invention increases the barrier layer of deposit and provides convenience can for simultaneously the end point determination of interlayer dielectric layer chemico-mechanical polishing, improves the stability of CMP (Chemical Mechanical Polishing) process.
In sum, the present invention makes chemico-mechanical polishing can be parked on this barrier layer in the abrasive media layer, the CMP (Chemical Mechanical Polishing) process fluctuation that causes because of the variation of consumptive material and technological parameter with effective elimination, simultaneously to a certain extent overcome the restriction of chemico-mechanical polishing self-characteristic, improved after the dielectric layer chemico-mechanical polishing in the silicon chip face and the thickness homogeneity between the silicon chip.
Claims (6)
1. improve the method for dielectric layer thickness homogeneity in the semiconductor alloy line manufacture craft, it is characterized in that, after making metal connecting line, deposit first dielectric layer, deposit one deck barrier layer on described first dielectric layer then, deposit second dielectric layer on described barrier layer again, the lowest part of described second dielectric layer will be higher than the highest point on described barrier layer, carry out chemico-mechanical polishing afterwards, in the chemico-mechanical polishing that carry out in the back on described barrier layer described second dielectric layer is had high selectivity, make the surface after the chemico-mechanical polishing rest on the highest point on described barrier layer.
2. improve the method for dielectric layer thickness homogeneity in the semiconductor alloy line manufacture craft according to claim 1, it is characterized in that, described first dielectric layer is pure SiO
2, or the SiO of one or more impurity elements among doping P, B, the F
2, its depositing technics is PE-CVD, AP-CVD or LP-CVD, thickness range is 100～10000
3. improve the method for dielectric layer thickness homogeneity in the semiconductor alloy line manufacture craft according to claim 1, it is characterized in that described barrier layer is SiON or SiN, its depositing technics is PE-CVD, AP-CVD or LP-CVD, thickness range are 10～3000
4. improve the method for dielectric layer thickness homogeneity in the semiconductor alloy line manufacture craft according to claim 1, it is characterized in that, described second dielectric layer is pure SiO
2, or the SiO of one or more impurity elements among doping P, B, the F
2, its depositing technics is PE-CVD, AP-CVD or LP-CVD, thickness range are 100～10000
5. improve the method for dielectric layer thickness homogeneity in the semiconductor alloy line manufacture craft according to claim 1, it is characterized in that, the set time that is controlled to be of described chemico-mechanical polishing is controlled, and perhaps is end point determination control.
6. improve the method for dielectric layer thickness homogeneity in the semiconductor alloy line manufacture craft according to claim 5, it is characterized in that, according to the optics in silicon chip surface or the CMP (Chemical Mechanical Polishing) process process, machinery, variations in temperature, the end-point detection method of element-specific or compound test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100575192A CN101937867A (en) | 2009-06-30 | 2009-06-30 | Method for improving membrane thickness homogeneity of dielectric layer in manufacturing process of semiconductor metal line |
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|---|---|---|---|
| CN2009100575192A CN101937867A (en) | 2009-06-30 | 2009-06-30 | Method for improving membrane thickness homogeneity of dielectric layer in manufacturing process of semiconductor metal line |
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| CN101937867A true CN101937867A (en) | 2011-01-05 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102945826A (en) * | 2012-11-30 | 2013-02-27 | 上海宏力半导体制造有限公司 | Method for improving contact resistance uniformity |
| CN109216541A (en) * | 2017-06-30 | 2019-01-15 | 中电海康集团有限公司 | The production method of MRAM and its |
-
2009
- 2009-06-30 CN CN2009100575192A patent/CN101937867A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102945826A (en) * | 2012-11-30 | 2013-02-27 | 上海宏力半导体制造有限公司 | Method for improving contact resistance uniformity |
| CN109216541A (en) * | 2017-06-30 | 2019-01-15 | 中电海康集团有限公司 | The production method of MRAM and its |
| CN109216541B (en) * | 2017-06-30 | 2022-05-17 | 中电海康集团有限公司 | MRAM and manufacturing method thereof |
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