CN101937849A

CN101937849A - Parasitic tube effect reduction method of self-aligned LDMOS

Info

Publication number: CN101937849A
Application number: CN200910057521XA
Authority: CN
Inventors: 戚丽娜; 张帅
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2009-06-30
Filing date: 2009-06-30
Publication date: 2011-01-05

Abstract

The invention discloses a parasitic tube effect reduction method of a self-aligned LDMOS, comprising the following steps: step 1, performing polycrystalline silicon deposition, and carving the polycrystalline silicon injected into the region; step 2, performing a first injection, wherein the injection direction and the vertical direction of the silicon wafer plane form an included angle larger than 0 degree to form a conducting channel for the transverse diffusion of the metal-oxide semiconductor; and step 3, performing a 0 degree injection again to the base region, wherein the ions injected in 0 degree are same as the ions in the first injection, and the 0 degree injection is performed vertically to the direction of the silicon wafer plane. The method optimizes the performance of a self-aligned transverse diffusion metal-oxide semiconductor SAC LDMOS tube, the addition of the one-time 0 degree injection based on the original one time large-angle injection can reduce the value of the amplification factor of the parasitic tube, lower the base region resistance of the parasitic tube and reduce the parasitic tube effect.

Description

Reduce the method for phost line effect among the autoregistration LDMOS

Technical field

The present invention relates to field of semiconductor manufacture, particularly relate to a kind of method that reduces phost line effect in the autoregistration Laterally Diffused Metal Oxide Semiconductor pipe (LDMOS).

Background technology

BCD is a kind of monolithic integrated technique technology.This technology can be made bipolar tube bipolar on same chip, complementary metal oxide semiconductors (CMOS) CMOS and diffused metal oxide emiconductor DMOS device are called BCD technology.BCD technology is produced on bipolar device and complementary metal oxide semiconductors (CMOS) cmos device on the same chip simultaneously.It combines the advantage of bipolar device high transconductance, strong load driving ability and the high and low power consumption of complementary metal oxide semiconductors (CMOS) CMOS integrated level, and it is made up for each other's deficiencies and learn from each other, performance advantage separately.What is more important, it is integrated diffused metal oxide emiconductor DMOS power device, diffused metal oxide emiconductor DMOS can work under switching mode, and power consumption is extremely low.Do not need expensive encapsulation and cooling system just can pass to load with high-power.Low-power consumption is one of major advantage of BCD technology.The BCD manufacturing process of integrating can significantly reduce power dissipation, improves systematic function, saves the encapsulation overhead of circuit, and has better reliability.

At present, often utilize the lower characteristic of conducting resistance Rdson of autoregistration Laterally Diffused Metal Oxide Semiconductor SACLDMOS to do switching device in the BCD technique platform, so-called autoregistration is promptly injected P type tagma P-body wide-angle by the p type and is injected the raceway groove (as shown in Figure 1) that forms pipe.The channel length of this device is not subjected to the influence of technological fluctuation and lithography registration, and device performance is stable.

Though the device electrical parameter, input-output characteristic curve can reach requirement, once injects other performance requirements that can't take into account optimised devices, thereby improves the device reliability during operation such as reducing the phost line effect.

With autoregistration N Laterally Diffused Metal Oxide Semiconductor SAC LDMOS is example, source (the N+)-dark N trap of P type tagma pbody-DNW forms the NPN pipe of a parasitism, in order to satisfy the pipe electrical parameter, requirements such as input-output characteristic curve, these inject all is definite constant, the multiplication factor BETA value of phost line is determined so, injects then unadjustable ghost effect with P type tagma, original base P-body wide-angle.When drain terminal adds high voltage, electron collision in the DMOS raceway groove produces hole current IB, hole current IB can increase along with the increase of drain terminal voltage, just can trigger parasitic NPN pipe conducting when hole current IB * resistance R reaches certain value, thereby cause the DMOS component failure.

Summary of the invention

Technical problem to be solved by this invention provides a kind of method that can effectively reduce phost line effect among the autoregistration Laterally Diffused Metal Oxide Semiconductor pipe LDMOS, can guarantee that phost line is not easy to be triggered, thereby when not influencing DMOS device self parameter, reduce the phost line effect, improve the device reliability during operation.

In order to solve above technical problem, the invention provides a kind of method that reduces phost line effect among the autoregistration Laterally Diffused Metal Oxide Semiconductor pipe LDMOS; May further comprise the steps: step 1, carry out the polysilicon deposit, carve the polysilicon of injection zone; Step 2, carry out the first time earlier and inject, its injection direction forms an angle greater than zero degree with direction perpendicular to the silicon chip plane, is used to form the conducting channel of Laterally Diffused Metal Oxide Semiconductor; Step 3, again the base is carried out zero degree and inject, the ion homotype that the ion that described zero degree is injected and the described first time inject, it is to inject perpendicular to the direction on silicon chip plane that described zero degree is injected.

Beneficial effect of the present invention is: the performance of optimizing autoregistration Laterally Diffused Metal Oxide Semiconductor SACLDMOS pipe, increasing a zero degree on the basis that former once wide-angle is injected injects, can reduce the times magnification numerical value of phost line, reduce the phost line base resistance, reduced the phost line effect.

Description of drawings

Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.

Fig. 1 is that existing autoregistration Laterally Diffused Metal Oxide Semiconductor SAC LDMOS raceway groove forms schematic diagram;

Fig. 2 is the schematic diagram that the described base of the embodiment of the invention injects at twice;

Fig. 3 is the described method flow schematic diagram of the embodiment of the invention.

Embodiment

Core of the present invention is, in order further to optimize the performance of autoregistration Laterally Diffused Metal Oxide Semiconductor SAC LDMOS pipe, increasing a zero degree on the basis that former once wide-angle is injected injects, can reduce the multiplication factor beta value of phost line, reduce the phost line base resistance, reduce the phost line effect.

As Fig. 2, shown in Figure 3, the method that reduces phost line effect in the autoregistration Laterally Diffused Metal Oxide Semiconductor pipe of the present invention may further comprise the steps:

Step 1, carry out the polysilicon deposit, carve the polysilicon of injection zone;

Step 2, carry out primary wide-angle earlier and inject, its injection direction forms certain included angle with direction perpendicular to the silicon chip plane, to form the conducting channel of Laterally Diffused Metal Oxide Semiconductor; Described wide-angle is injected to the mode of the conducting channel of present known formation Laterally Diffused Metal Oxide Semiconductor, and parameters such as its implant angle can adopt the technological parameter of the conducting channel of present known formation Laterally Diffused Metal Oxide Semiconductor.

Step 3, carry out zero degree again and inject, the ion homotype that the ion that described zero degree is injected and the described first time inject, it is to inject perpendicular to the direction on silicon chip plane that described zero degree is injected.Described zero degree is injected the ion concentration of base, back greater than 5E18/cm ³

Method of the present invention is applied in the BCD technological process, and the base that forms autoregistration Laterally Diffused Metal Oxide Semiconductor SAC LDMOS pipe is infused in before the etch polysilicon grid G ate poly, forms after the trap well.

Its concrete technological process of present embodiment is as follows:

1) forms N buried regions NBL according to technique known earlier, P buried regions PBL, extension EPI, dark N trap DNW and high pressure P trap HVPW.

2) form shallow-trench isolation STI, N trap NW, P trap PW according to known technology again.

3) carry out polysilicon Poly deposit, carve the polysilicon poly that removes the Nbody injection zone, carry out a wide-angle earlier and inject, carry out a zero degree again and inject, implanted dopant is phosphorus P; Or carve the polysilicon poly that removes the Pbody injection zone, and carry out a wide-angle earlier and inject, carry out a zero degree again and inject, implanted dopant is a boron.

4) carve polysilicon gate Gate poly according to known technology then.

5) carry out lightly doped drain according to known technology and inject LDD, form gap spacer, carry out the source and leak injection SD.

Of the present invention focusing on, adding a zero degree on the basis that former once wide-angle is injected again injects, zero degree is injected can regulate base concentration specially, can reduce the resistance of parasitic triode multiplication factor BETA value and base, reduce resistance R and can allow bigger hole current IB, thereby guarantee that phost line is not easy to be triggered, thereby when not influencing DMOS device self parameter, reduce the phost line effect, improve the device reliability during operation.

The present invention is adding a zero degree injection (as shown in Figure 2) on the basis of original base P type tagma P-body, being labeled as 1 expression injects for the first time, its injection direction with form certain included angle perpendicular to the direction on silicon chip plane, in order to form the conducting channel of Laterally Diffused Metal Oxide Semiconductor LDMOS, satisfy the electricity requirement, be labeled as 2 expression zero degree injection for the second time, ion that injects and the preceding ion homotype of once injecting, can strengthen the concentration of P type tagma P-body, strengthen phost line base resistance value, reduce triode multiplication factor BETA value, double ion injects does not increase any photoetching level.Method of the present invention makes that phost line is not easy to be triggered, and has improved DMOS device reliability during operation.

One time wide-angle is injected the raceway groove that forms autoregistration Laterally Diffused Metal Oxide Semiconductor SAC LDMOS, described zero degree is injected the ion that adopts with the homotype of wide-angle injection for the first time, form a denseer zone of concentration in the BODY district, can reduce the phost line base resistance, reduce ghost effect, improve device reliability.

For N Laterally Diffused Metal Oxide Semiconductor LDMOS, the ion that zero degree is injected is a boron.

For P Laterally Diffused Metal Oxide Semiconductor LDMOS, the ion that zero degree is injected is a phosphorus.

The present invention is not limited to execution mode discussed above.More than the description of embodiment is intended in order to describe and illustrate the technical scheme that the present invention relates to.Based on the conspicuous conversion of the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, so that those of ordinary skill in the art can use numerous embodiments of the present invention and multiple alternative reaches purpose of the present invention.

Claims

1. method that reduces autoregistration LDMOS effect; It is characterized in that, may further comprise the steps:

Step 2, carry out the first time earlier and inject, its injection direction forms an angle greater than zero degree with direction perpendicular to the silicon chip plane, is used to form the conducting channel of Laterally Diffused Metal Oxide Semiconductor;

Step 3, again the base is carried out zero degree and inject, the ion homotype that the ion that described zero degree is injected and the described first time inject, it is to inject perpendicular to the direction on silicon chip plane that described zero degree is injected.

2. the method that reduces phost line effect among the autoregistration LDMOS as claimed in claim 1 is characterized in that, for N type Laterally Diffused Metal Oxide Semiconductor NLDMOS, the ion that described zero degree is injected is a boron.

3. the method that reduces phost line effect among the autoregistration LDMOS as claimed in claim 1 is characterized in that, for P type Laterally Diffused Metal Oxide Semiconductor PLDMOS, the ion that described zero degree is injected is a phosphorus.

4. the method that reduces phost line effect among the autoregistration LDMOS as claimed in claim 1 is characterized in that, described zero degree is injected the ion concentration of base, back greater than 5E18/cm ³