CN101925987B - 用于形成应变沟道pmos器件的方法以及由该方法形成的集成电路 - Google Patents

用于形成应变沟道pmos器件的方法以及由该方法形成的集成电路 Download PDF

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CN101925987B
CN101925987B CN2009801027028A CN200980102702A CN101925987B CN 101925987 B CN101925987 B CN 101925987B CN 2009801027028 A CN2009801027028 A CN 2009801027028A CN 200980102702 A CN200980102702 A CN 200980102702A CN 101925987 B CN101925987 B CN 101925987B
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Abstract

一种集成电路(IC)(200)包括多个压缩应变PMOS晶体管(201)。该IC包括具有半导体表层(213)的衬底(212)。栅叠层形成在该半导体表层中或表层上并且包括在栅介电质(238)上的栅电极(233(a))。包括从Ge、Sn和Pb中选择的至少一个核素的至少一个压缩应变诱导区域(281)位于该PMOS晶体管的源极和漏极区域(240)的至少一部分内，其中该应变诱导区域提供小于等于1010位错线/cm2以及在该压缩应变诱导区域中高于该压缩应变诱导核素的固溶度限制的该压缩应变诱导核素的活性浓度。一种用于形成压缩应变PMOS晶体管的方法包括使用以下条件在该栅叠层的至少相对侧进行注入：从Ge、Sn和Pb中选择的至少一种压缩应变诱导核素，剂量为大于等于1×1015cm-2，在注入期间注入温度在大于等于273°K的温度范围，其中所述注入条件足够形成无定形区域。使用退火条件对晶圆进行退火，所述退火条件包括在1050℃到1400℃之间的峰值退火温度和在该峰值退火温度下大于等于10秒的退火时间，其中该无定形区域通过固相外延(SPE)再结晶。

Description

用于形成应变沟道PMOS器件的方法以及由该方法形成的集成电路
技术领域
本发明的实施例涉及包括压缩应变PMOS器件的集成电路(IC)。
背景技术
增大的器件密度以及更高速度性能和更低功耗是努力改进IC器件和IC制造方法的主要驱动力。例如，对于高速数字应用的CMOS设计考虑通常由每一单个栅极的上拉时间和下拉时间决定。栅极对于信号传播具有相关的延迟时间周期。该延迟时间周期继而与驱动电流(Idrive)成反比。最大化驱动电流可以增加CMOS器件的速度。
已知机械应力在电荷载流子的迁移率中起作用，所述迁移率影响若干器件参数，包括阈值电压(VT)漂移、饱和驱动电流(IDsat)和驱动电流(Idrive)。作为器件性能的速度的度量，特别重要的是Ion-Ioff的值(也称为(Idrive))。增加MOS器件的沟道区域中的电荷载流子迁移率通常将增加驱动电流Idrive。
用于将机械应变引入到器件的沟道区域中的一种工艺是通过注入合适的核素(species)然后退火，因为通常应变诱导核素必须以取代方式引入到衬底晶格中才能有效。晶格中的间隙位置通常对提供应变是无效的，并且相反会引起缺陷的增多。具有比衬底原子的尺寸大的尺寸的核素提供压缩应变，比衬底原子小的核素提供拉伸应变。这种注入工艺通常在室温下进行，并且相关的退火工艺典型的是相对长的处理时间，例如在若干分钟的数量级，或者更多。已知的应变注入/退火方法通常受限于高的制造成本、工艺集成问题以及由于在完成的器件内残留较多的射程末端无序(end-of-range disorder)而造成难以生产可接受的器件质量。
如本领域中已知的，射程末端无序指代由注入产生的位于无定形区域外的位错环，其通常在最终IC中导致残留缺陷，所述缺陷可能降低成品率、器件性能，在某些情况下还可能降低器件的可靠性。常规应变注入/退火工艺通常导致大于等于1013位错线/cm2的缺陷密度，其主要源于残留的射程末端无序产生的缺陷。这些以及其他缺点表明了在MOS器件制造中持续需要新的应变沟道MOS器件和制造方法，以可靠地并且可预期地实现显著改进的器件性能，同时保证高的成品率和器件可靠性。
发明内容
本发明的实施例描述了基于至少一种应变诱导核素的亚室温注入以及实现固相外延(SPE)的高温退火处理，形成应变沟道MOS器件的方法和由此形成的IC。本发明人发明低温注入工艺，以产生无定形态而没有衬底(例如Si)原子的明显的反冲，从而扩大了无定形区域。据发现，无定形区域的扩大减少了由注入产生的射程末端无序。此外，在注入期间使用的低温也限制了在注入期间可能发生的自退火。
本发明的一个实施例包括形成包括多个压缩应变PMOS器件的IC的方法。提供具有半导体表层的衬底晶圆，所述半导体表层包括至少一个PMOS区域。在所述PMOS区域的表面上形成包括在栅介电质上的栅电极的图形化的栅叠层。使用注入条件在所述栅叠层的至少相对侧对所述PMOS区域进行注入，所述注入条件包括从Ge、Sn和Pb中选择的至少一种压缩应变诱导核素，剂量为大于等于1×1015cm-2，以及在注入期间，晶圆的注入温度在小于等于273°K的温度范围内，其中所述注入条件足够形成无定形区域。接着使用退火条件对晶片进行退火，所述退火条件包括在1050℃和1400℃之间的峰值退火温度以及在该峰值温度下小于等于10秒的退火时间，其中所述无定形区域通过SPE再结晶。接着完成包括所述PMOS器件的IC制造。
发现在高温下(例如大于等于1150℃)进行短时间(例如小于等于10秒)的退火可以限制不期望的应变松弛。此外，已经发现这种退火导致压缩应变诱导原子以颇高于(例如典型地至少2倍)它们在衬底材料中的平衡固溶度限制的浓度进入到衬底晶格中。还发现根据本发明的实施例的方法充分减少了完成的器件中的残留的射程末端无序，其小于等于1010位错线/cm2，通常小于等于108位错线/cm2，导致改进的器件性能、成品率的提高以及在一些情况下可靠性的提高。
附图说明
图1是根据本发明的实施例的用于形成包括多个压缩应变PMOS器件的IC的示例工艺流程，所述压缩应变PMOS器件具有充分减少的射程末端无序。
图2是根据本发明的实施例的包括PMOS和NMOS器件的IC的剖面图，其中PMOS是压缩应变PMOS器件。
具体实施方式
本发明的一个实施例包括用于形成包括多个压缩应变PMOS器件的IC的方法，所述压缩应变PMOS器件具有充分减少的射程末端无序，从而具有减少的缺陷率，图1中为其示出了示例工艺流程100。步骤101包括提供具有包括至少一个PMOS(例如n-)区域的半导体表层的衬底晶圆。半导体衬底可以是单晶硅、绝缘体上的硅(SOI)等，或者上述的结合。步骤102通常包括隔离处理，例如槽隔离(例如浅槽隔离)处理。
步骤103包括在PMOS区域的表面上形成包括在栅介电质上的栅电极的图形化的栅叠层。在典型的实施例中，栅介电质包括氧化硅或者氮氧化硅，栅电极包括多晶硅。栅介电质也可以是淀积的介电质，包括具有k值通常大于10的高k介电质。
步骤104包括使用注入条件对在栅叠层的相对侧上的PMOS区域进行注入，即注入到将是源极和漏极(或其延伸)的PMOS区域，所述注入条件包括从Ge、Sn和Pb中选择的至少一种IV族压缩应变诱导核素。压缩应变诱导注入通常可以在侧墙形成之前或者之后进行。在侧墙之前注入的情况下，如本领域中已知的，注入将到达LDD区域，从而与在侧墙之后注入相比，离完成的器件的沟道更近。在CMOS IC的情况下，在这个注入期间，NMOS区域通常被掩蔽。如本领域中已知的，当被替代进入硅晶格时，与硅相比较大的这种应变诱导核素提供压缩应力。
用于压缩应变诱导注入的注入剂量通常在1×1015cm-2和1×1017cm-2之间，例如大约1×1016cm-2。用于这个注入的注入能量通常在20keV到300keV的范围内。压缩应变诱导注入在低于室温的温度下进行，通常在小于等于273°K的温度下，例如在77°K到273°K的范围内。注入角度通常为0到15度，但是可以更大。已经发现上述压缩应变诱导注入条件通常足够形成中心位于注入的投影射程(Rp)附近的深度处的无定形区域。已经发现在注入期间低于环境(sub-ambient)的晶圆温度通常扩展由注入所形成的无定形区域的空间范围(与常规环境和更高的注入温度相比)，本发明人已经发现该注入导致与注入有关的射程末端无序的更低浓度，例如小于等于1010位错线/cm2，并且通常小于等于108位错线/cm2。
步骤105包括使用退火条件对晶圆进行退火，所述退火条件包括在1050℃和1400℃之间的峰值退火温度以及在该峰值温度下小于等于10秒的退火时间。这个退火激活压缩应变诱导核素并且通过SPE对无定形区域进行再结晶。退火通常包括快速热退火(RTA)、闪光灯退火(flash lamp anneal)或者激光退火。激光退火可以是闪光退火(flash anneal)。在本发明的一个实施例中，可以在激光或者闪光退火之后进行非熔化式尖峰退火(non-melt spike anneal)。尖峰退火可以包括RTA或者激光退火。在激光退火的情况下，时间可以小于10毫秒，例如在大约0.1毫秒和10毫秒之间。在一个实施例中，退火包括1050℃到1150℃的RTA尖峰退火和1200℃到1300℃的小于10毫秒的激光退火。RTA尖峰退火和激光退火可以是任意的顺序。已经发现在高温下相对短的退火时间限制不期望的应变松弛。
步骤106包括完成在IC上的PMOS器件和NMOS器件的制造，通常包括常规步骤，其包括侧墙、硅化物、源极/漏极、多层金属化以及钝化。在本发明的一个替换实施例中，上面所描述的与步骤105有关的退火可以在源极/漏极注入之后进行，从而是单个组合的退火，其激活源极/漏极注入并且也提供SPE。然而，对于多晶硅栅极工艺，通常多晶硅一直不被激活到栅极的底部，使得额外的退火可以是有帮助的，例如额外的RTA尖峰退火。对于金属栅极工艺，单个组合的退火可以是唯一的退火，并且通常提供良好的器件性能。在本发明的实施例中，也可以包括替换栅极工艺(replacement gate processing)。
在本发明的另一实施例中，在形成栅叠层(步骤103)之前或者在形成栅介电质之后但是在形成栅电极之前进行压缩应变诱导注入(步骤104)。在这个实施例中，除了在源极/漏极和LDD区域内，压缩应变诱导区域还沿着PMOS沟道区域的全部长度延伸。
在本发明的又另一实施例中，也可以将位错钉扎(dislocation pinning)核素例如C、N或F与压缩应力诱导核素共同注入。位错钉扎核素可以通过钉扎可能余留的低密度位错来进一步改进PMOS器件性能。通常以从2×1014cm-2到5×1015cm-2的剂量范围并且从3keV到30keV范围的能量注入压缩应力诱导核素。位错钉扎核素注入通常导致最小浓度为至少1×1018cm-3，通常在至少1×1019cm-3的浓度范围。
图2是根据本发明的实施例的包括PMOS器件201和NMOS器件202的IC200的剖面图，其中PMOS器件202是压缩应变PMOS器件。IC 200包括衬底212，其具有半导体表层213。示出了槽隔离271。在半导体表层213中形成N阱222和P阱228。在表层213中或表层213上形成用于PMOS器件201和NMOS器件202两者的栅叠层。PMOS器件201包括通常为P+掺杂的栅电极233a，NMOS器件202包括通常为N+掺杂的栅电极233b，其共同被称作栅电极233。在栅电极233上示出了硅化物层254，在栅电极233下面示出了栅介电质238，其中对于PMOS器件201和NMOS器件202两者，沟道区域位于栅介电质238下面的半导体表层中。侧墙262在栅叠层254/233/238的侧壁上。
PMOS器件201包括位于栅叠层254/233a/238的相对侧上的源极/漏极(SD)区域240。PMOS器件201还包括SD 延伸(LDD)区域235，其位于SD区域240和PMOS器件201的沟道区域之间。PMOS器件201包括在沟道两侧横向延伸到槽隔离271的压缩应变诱导区域281。压缩应变诱导区域包括最小活性浓度为1019cm-3的Ge、Sn或Pb，其中部分提供超过平衡固溶度限制的活性浓度。虽然如上面所描述的，示出了仅在沟道各自侧面的压缩应变诱导区域，但是在本发明的另一实施例中，可以是沿着沟道区域的整个长度延伸的单个压缩应变诱导区域。如上面所描述的，压缩应变诱导区域281还可以包括位错钉扎核素，例如C、N或F，通常最小浓度为至少1×1018cm-3。
NMOS器件202包括位于栅叠层254/233b/238的相对侧面的SD区域246。NMOS器件202包括位于SD区域246和NMOS器件202的沟道区域之间的SD延伸(LDD)区域245。
本发明的实施例可以被集成到多种工艺流程中以形成多种器件和相关产品。半导体衬底可以包括在其中的各种元件和/或在其上的各种层。这些可以包括阻挡层、其他介电层、器件结构、有源元件和无源元件，所述有源元件和无源元件包括源极区域、漏极区域、位线、基极、发射极、集电极、导电线、导电通孔等。此外，本发明可以用在多种工艺中，包括双极工艺、CMOS工艺、BiCMOS工艺和MEMS工艺。
虽然上面已经描述了本发明的各种实施例，但是应明白，仅出于示例而不是限制来给出它们。在不偏离本发明的范围的情况下，可以根据在此的公开对所公开的实施例进行许多改变。

Claims (10)

1.一种用于形成包括多个压缩应变PMOS器件的集成电路即IC的方法，包括：
提供具有半导体表层的衬底晶圆，所述半导体表层包括至少一个PMOS区域；
在所述PMOS区域的表面上形成包括在栅介电质上的栅电极的图形化的栅叠层；
使用注入条件对在所述栅叠层的至少相对侧上的所述PMOS区域进行注入，所述注入条件包括从Ge、Sn和Pb中选择的至少一种压缩应变诱导核素，剂量为大于等于1×1015cm-2，并且在所述注入期间，用于所述晶圆的注入温度在小于等于273°K的温度范围内，其中所述注入条件足够形成无定形区域；
使用退火条件对所述晶圆进行退火，所述退火条件包括在1050℃和1400℃之间的峰值退火温度以及在所述峰值温度下小于等于10秒的退火时间，其中所述无定形区域通过固相外延即SPE再结晶，以及
完成所述PMOS器件的制造。
2.根据权利要求1所述的方法，其中所述注入温度在从173°K到273°K的范围内。
3.根据权利要求1所述的方法，其中所述退火包括1050℃到1150℃的尖峰退火和1200℃到1300℃的小于10毫秒的激光退火。
4.根据权利要求1所述的方法，其中所述方法还包括在所述栅叠层的侧壁上形成侧墙，其中所述注入在所述形成所述图形化的栅叠层之后并且在所述形成所述侧墙之前发生。
5.根据权利要求1所述的方法，还包括使用从2×1014cm-2到5×1015cm-2的剂量、以从3keV到30keV范围的能量，与所述注入共同注入从C、N或F中选择的至少一种位错钉扎核素。
6.根据权利要求1所述的方法，其中所述至少一种压缩应变诱导核素是所述Sn。
7.一种形成包括多个压缩应变PMOS器件的集成电路即IC的方法，包括：
提供具有半导体表层的衬底晶圆，所述半导体表层包括至少一个PMOS区域；
在所述PMOS区域的表面上形成包括在栅介电质上的栅电极的图形化的栅叠层；
使用注入条件对在所述栅叠层的相对侧上的所述PMOS区域进行注入，所述注入条件包括Sn，剂量在5×1015cm-2和5×1016cm-2之间，以及在所述注入期间，所述晶圆的注入温度在从77°K到273°K的温度范围内，其中所述注入条件足够形成无定形区域；
使用退火条件对所述晶圆进行退火，所述退火条件包括在1050℃到1400℃之间的峰值退火温度并且在所述峰值温度下小于等于1秒的退火时间，其中所述无定形区域通过固相外延即SPE再结晶，以及
完成所述PMOS器件的制造。
8.根据权利要求7所述的方法，其中所述退火包括1050℃到1150℃的尖峰退火和1200℃到1300℃的小于10毫秒的激光退火，进一步地，其中所述激光退火在所述尖峰退火之前。
9.一种包括多个压缩应变PMOS晶体管的集成电路即IC，包括：
具有半导体表层的衬底，
其中所述多个压缩应变PMOS晶体管中的每一个包括：
形成在所述半导体表层中或者表层上的栅叠层，其包括在栅介电质上的栅电极，其中沟道区域位于所述栅介电质下面的所述半导体表层中；
在所述栅叠层的相对侧的源极和漏极区域；
至少一个压缩应变诱导区域，其包括从Ge、Sn和Pb中选择的至少一种核素，位于所述源极和漏极区域的至少一部分中，其中所述应变诱导区域提供小于等于1010位错线/cm2，并且在所述压缩应变诱导区域中，所述压缩应变诱导核素的活性浓度高于所述压缩应变诱导核素的固溶度限制。
10.根据权利要求9所述的IC，其中所述压缩应变诱导区域提供小于等于108位错线/cm2，并且在所述压缩应变诱导区域中，所述压缩应变诱导核素的活性浓度是所述压缩应变诱导核素的固溶度限制的至少2倍。
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