CN101916744A

CN101916744A - Method for reducing surface electric field in transistor

Info

Publication number: CN101916744A
Application number: CN2010102356417A
Authority: CN
Inventors: 唐树澍
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-07-23
Filing date: 2010-07-23
Publication date: 2010-12-15

Abstract

The invention discloses a method for reducing a surface electric field in a transistor. The method comprises the following steps of: implanting ions into a semiconductor substrate between an active transistor area and a neighboring area; performing high-temperature diffusion treatment; forming a source area, a grid area and a drain area in the substrate of the transistor respectively; and covering a protective oxide layer on the surface of the transistor. Compared with the prior art, the method for reducing the surface electric field in the transistor has the advantages of reducing the surface electric field to the maximum extent, forming an excellent isolation structure, only adopting one-time ion implantation operation, reducing technical parameters and simplifying operation flow.

Description

Reduce the method for surface field in a kind of transistor

Technical field

The present invention relates to a kind of semiconductor device partition method, relate in particular to the method that reduces surface field in a kind of transistor.

Background technology

Power MOS pipe uses existing historical for many years, the improvement that its design and manufacture method are continuing always.The English full name of MOS is that Metal-Oxide-Semiconductor is a Metal-oxide-semicondutor, and definite says, this WD the structure of metal-oxide-semiconductor in the integrated circuit, that is: on the semiconductor device of a fixed structure, add silicon dioxide and metal.On structure, metal-oxide-semiconductor can be divided into enhancement mode (E type) and depletion type (D type), metal-oxide-semiconductor generally has 3 electrodes: source (source) utmost point, leakage (drain) utmost point and grid (gate) utmost point, the circuit that metal-oxide-semiconductor forms is commonly referred to as the MOS circuit, but difference is arranged, the PMOS logical circuit is called the PMOS circuit, the NMOS logical circuit is called nmos circuit, the common logical circuit of forming of PMOS and NMOS is called the CMOS integrated circuit, and the circuit that MOS and BJT (Bipolar Junction Transistor bipolar junction transistor) form is called the Bi-CMOS integrated circuit.Because the metal-oxide-semiconductor quiescent dissipation is almost 0, all power consumptions all concentrate in the process of switch transition, therefore relative BJT, and the power consumption of metal-oxide-semiconductor is lower.Therefore, in the modern industry design, metal-oxide-semiconductor is mainly used in and realizes switching logic (0,1 logic) in the Digital Logical Circuits.On performance, power MOS pipe mainly is to develop towards low on-resistance (Rdson), high withstand voltage, high-frequency direction.

Reducing the technology of surface field (Reduced SURfsce Field), is taked in some semiconductor device and integrated circuit (IC) chip a kind of in order to improve the measure of plane p-n junction puncture voltage.Generally, the puncture voltage of plane p-n junction will be lower than the puncture voltage of p-n junction in the body, and this mainly is because the puncture near surface place plays the cause of restriction.Therefore, the electric field at reduction p-n junction near surface place, plane is a major issue that improves its puncture voltage.So-called RESURF technology is exactly that a doped regions is set artificially, makes the electric field at p-n junction near surface place, plane be evenly distributed and weakens, thereby can improve surface breakdown voltage.For an epitaxial planar p-n junction, when epitaxy layer thickness was big, epitaxial loayer can not exhaust fully under reverse voltage, and then less in the depletion width of p-n junction surface, the electric field at this place is stronger, thereby surface breakdown voltage is lower; When epitaxy layer thickness hour, epitaxial loayer can exhaust fully, then the depletion width in the p-n junction surface is bigger, thereby the electric field at this place weakens increase in breakdown voltage; Further, when epitaxy layer thickness was very little, not only epitaxial loayer can exhaust fully, and epitaxial loayer is also depleted greatly, the depletion width that promptly is equivalent to the p-n junction surface increases greatly, and then electric field weakens greatly, thereby surface breakdown voltage can improve greatly.Therefore exhaust a kind of like this effect of being brought fully based on epitaxial loayer, just proposed obviously to reduce the structure of the so-called RESURF diode of surface breakdown influence; In this structure, epitaxial loayer is very thin, and doping content is suitable, can exhaust fully under reverse voltage to guarantee whole epitaxial loayer; The core of diode is horizontal n+-p+ knot, and the puncture voltage of this diode is promptly very near puncture voltage in the body.The method of this reduction surface field, raising puncture voltage is exactly the RESURF technology.

In order to obtain low on-resistance, high withstand voltage, high-frequency metal-oxide-semiconductor, the researcher has adopted following measure: in order to obtain lower conducting resistance, must keep the drain region of high concentration 1.; 2. in order to obtain higher puncture voltage, avoid making puncture voltage reduce because of the drain doping region surface concentration is too high, must make that the degree of depth of p-n junction is enough dark in the drain region.The mode that can adopt two secondary ions to inject in the drain region in the prior art reaches above-mentioned effect, please refer to Fig. 1, Fig. 1 is the adjacent MOS structural representation of prior art, on scheming, can see, single MOS structure comprises the source area 12 that is positioned on the substrate 10, gate regions 13 and drain region 11, drain region 11 contains two secondary ions and injects the doped region 16 that stays, 17, isolate with P trap 14 between the drain region 20 of drain region 11 and the metal-oxide-semiconductor that links to each other, inject for two secondary ions, being generally for the first time, ion is injected to dark injection, the injection energy is 200Kev to 300Kev, and implantation concentration is 2.0E ¹³/ cm ²To 8.0E ¹³/ cm ²With respect to the degree of depth that the first time, ion injected, for the second time more shallow comparatively speaking, the injection energy is 35Kev to 45Kev, and implantation concentration is 0.5E ¹³/ cm ²To 2.0E ¹³/ cm ²This traditional method can be good at obtaining lower conducting resistance, can avoid the excessive problem that causes puncture voltage to reduce of electric field on surface, drain region again, but, this method need in addition, also will form the technology of P trap at the annealing process after injection of two secondary ions and ion injection are carried out in the drain region, relate to more technological parameter, the more complicated that operates and trouble.

Summary of the invention

The technical problem to be solved in the present invention provides in a kind of transistor the method that reduces surface field, solves in the semiconductor technology to obtaining low on-resistance and improving puncture voltage, reduce technology that surface field adopts and relate to that technological parameter is many, the problem of complicated operation.

To achieve these goals, the present invention proposes a kind of method that reduces the transistor surface field, may further comprise the steps: carry out ion in the Semiconductor substrate between described transistor active region and adjacent place and inject; Carrying out High temperature diffusion handles; In described transistorized substrate, form source area, gate regions and drain region respectively; In described transistor surface coverage protection oxide layer.

Optionally, the parameter of described ion injection is: the injection energy is 10Kev to 3000Kev, and implantation concentration is 1E ¹²/ cm ²To 5E ¹³/ cm ²

Optionally, described substrate is the P type, and the ion that is used for described ion injection is a P type ion.

Optionally, the temperature range that described High temperature diffusion is handled is 1000 ℃ to 1200 ℃, and the time is 30 minutes to 10 hours.

Optionally, the ion that forms the doping of described drain region is a n type ion.

Optionally, described grid is between described source electrode and described drain electrode.

The beneficial effect that reduces the method for surface field in a kind of transistor of the present invention mainly shows: reduce the method for surface field in the transistor provided by the invention with respect to prior art, only adopt the primary ions implant operation, reduced technological parameter and simplified operating process; Owing to adopt High temperature diffusion technology, therefore the ion doping degree of depth after the diffusion of the present invention in drain electrode is darker than the degree of depth of the ion injection acquisition of prior art, and the technological parameter variation is littler, helps improving the puncture voltage of metal-oxide-semiconductor more, reduces the electric field on transistor surface; In addition, the area of isolation that forms between adjacent metal-oxide-semiconductor after the High temperature diffusion of the present invention P well depth more of the prior art degree is also darker, and isolation effect is also better.

Description of drawings

Fig. 1 is the structural representation of prior art adjacent transistors

Fig. 2 is for reducing the flow chart of the method for surface field in a kind of transistor of the present invention.

Fig. 3 is for using the structural representation that reduces the formed device of method of surface field in a kind of transistor of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the present invention is further elaborated.

At first, please refer to Fig. 2, Fig. 2 is for reducing the flow chart of the method for surface field in a kind of transistor of the present invention, as can be seen, the present invention includes following steps from the figure:

Step 40: carry out ion in the Semiconductor substrate between described transistor active region and adjacent place and inject, described substrate is the P type, the ion that is used for described ion injection is a P type ion, preferably, the parameter that described ion injects is: the injection energy is 10Kev to 3000Kev, and implantation concentration is 1E ¹²/ cm ²To 5E ¹³/ cm ², it is required definite that concrete energy that ion injects and concentration are looked practical operation, and please refer to several preferred embodiments below: the injection energy is 100Kev, and implantation concentration is 2E ¹³/ cm ²The injection energy is 1000Kev, and implantation concentration is 1E ¹³/ cm ²The injection energy is 2000Kev, and implantation concentration is 3E ¹²/ cm ²

Step 41: carry out High temperature diffusion and handle, this step purpose is that the ion that will inject carries out High temperature diffusion, preferably, the temperature range that described High temperature diffusion is handled is 1000 ℃ to 1200 ℃, and the time is 30 minutes to 10 hours, temperature is high more, the speed of diffusion is fast more, and the time is long more, and the scope of diffusion is wide more, please refer to several preferred embodiments below: the temperature that described High temperature diffusion is handled is 1000 ℃, and the time is 10 hours; The temperature that described High temperature diffusion is handled is 1100 ℃, and the time is 5 hours; The temperature that described High temperature diffusion is handled is 1200 ℃, and the time is 30 minutes;

Step 42: in each described transistorized substrate, form source area, gate regions and drain region respectively, described grid is between described source electrode and described drain electrode, the ion that forms the doping of described drain region is a n type ion, this step is a prior art, promptly on substrate, form a plurality of transistors, but not carrying out to each transistor drain district not as shown in the prior art, ion injects;

Step 43: in described transistor surface coverage protection oxide layer, this step is a conventional techniques, mainly transistor is played a protective role.

At last, please refer to Fig. 3, Fig. 3 is for using the structural representation that reduces the formed device of method of surface field in a kind of transistor of the present invention, from the figure as can be seen, single MOS structure comprises the source area 12 that is positioned on the substrate 10, gate regions 13 and drain region 11, between the drain region 20 of drain region 11 and the metal-oxide-semiconductor that links to each other for inject through ion and High temperature diffusion after the doped region 24 that forms, this doped region 24 is divided into two parts, a part is between two drain regions 11 and 20 (vertical direction among the figure), another part is arranged in (figure horizontal direction) under two

drain regions

11 and 20, thereby obtains low on-resistance.Owing to adopt High temperature diffusion technology, therefore the ion doping degree of depth after the diffusion in drain electrode is darker than the degree of depth of the ion injection acquisition of prior art, helps improving the puncture voltage of metal-oxide-semiconductor more, reduces the electric field on transistor surface.

Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.

Claims

1. method that reduces the transistor surface field is characterized in that may further comprise the steps:

Carrying out ion in the Semiconductor substrate between described transistor active region and adjacent place injects;

Carrying out High temperature diffusion handles;

In described transistorized substrate, form source area, gate regions and drain region respectively;

In described transistor surface coverage protection oxide layer.

2. the method for reduction transistor surface field according to claim 1 is characterized in that: the parameter that described ion injects is: the injection energy is 10Kev to 3000Kev, and implantation concentration is 1E ¹²/ cm ²To 5E ¹³/ cm ²

3. the method for reduction transistor surface field according to claim 1 is characterized in that: described substrate is the P type, and the ion that is used for described ion injection is a P type ion.

4. the method for reduction transistor surface field according to claim 1 is characterized in that: the temperature range that described High temperature diffusion is handled is 1000 ℃ to 1200 ℃, and the time is 30 minutes to 10 hours.

5. the method for reduction transistor surface field according to claim 1 is characterized in that: the ion that forms the doping of described drain region is a n type ion.

6. the method for reduction transistor surface field according to claim 1 is characterized in that: described grid is between described source electrode and described drain electrode.