CN101900945B - Overlay error compensation method - Google Patents
Overlay error compensation method Download PDFInfo
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- CN101900945B CN101900945B CN2009100521898A CN200910052189A CN101900945B CN 101900945 B CN101900945 B CN 101900945B CN 2009100521898 A CN2009100521898 A CN 2009100521898A CN 200910052189 A CN200910052189 A CN 200910052189A CN 101900945 B CN101900945 B CN 101900945B
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Abstract
The invention discloses an overlay error compensation method which is applied to a double-platform exposure machine bench. The difference between the overlay compensation values of two working platforms of the exposure machine bench is used for compensating the working platform with great overlay error. Thus, the overlay control difference between the two working platforms is reduced, and simultaneously, the overlay error of the working platforms is controlled within a required range; the performance and the qualification rate of semiconductors are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to two a kind of overlay (overlay) error compensating methods that are used for two stations (twin stage) exposure bench.
Background technology
Semiconductor devices be through producing a series of patterned material layer and non-patterned material layer by being made, the characteristic of the patterned material layer couplet that spatially is relative to each other wherein.Therefore, in manufacture process, the material layer of each patterning all need be aimed at the material layer of its previous patterning.So, in semiconductor fabrication, must consider that semiconductor substrate (for example, wafer) is gone up to align i.e. overlay (overlay) between the material layer.Because,, even can cause component failure because of the short circuit that the articulamentum misalignment caused with the performance that directly influences semiconductor devices if overlay error is bigger.
Continuous increase along with the dwindling gradually of feature sizes of semiconductor devices, number of layers.Conventional microscope judges that layer to the overlay between the layer, can not meet the demands far away.For asking more pinpoint accuracy, must judge that automatically system, Auto-Sensing Control work platform accomplish overlay control by the optics more accurate than naked eyes.For example, utilize the exposure bench (comprising scan-type (scanner) and step-by-step movement (stepper)) in little shadow equipment to come key-course to the overlay between the layer.
When guaranteeing device performance; People are in the efficient of producing of constantly pursuing device; So the exposure bench with two platforms (twin stage) is just used and given birth to, this exposure bench spatially is divided into two parts---measuring junction (measurement side) and exposure end (exposure side): measuring junction is responsible for wafer alignment (alignment), leveling (leveling) and is measured (wafer figure; Wafer map), the exposure end is responsible for exposure (exposure).Its course of work is following:
Suppose initial conditions be first platform at measuring junction, second platform is at exposure end.When beginning to handle a collection of wafer, first platform is received first wafer, then earlier aims at and measures at measuring junction; After obtaining the result, switch in the middle of second platform moves to; First platform is changed to the exposure end, with the result who has just measured first wafer is made public; At this moment, second platform is changed to measuring junction, and it receives second wafer, and it is aimed at and measures; By the time after first wafer was accomplished exposure, first wafer was passed in first platform and the transposition of second platform back, prepares to connect the 3rd wafer simultaneously; Second platform then carries out exposure-processed to second wafer, then repeats successively.So just can reduce the stand-by period of wafer, produce efficient and improve.Yet the overlay control performance of two platforms inevitably there are differences, and the yield of producing of semiconductor devices is impacted.
Summary of the invention
Technical matters to be solved by this invention is the overlay control difference that reduces between two two workbenches of platform (twin stage) exposure bench; Utilize this difference that overlay error is controlled in the required scope simultaneously, to improve the performance and the yield of semiconductor devices.
For solving above technical matters, the present invention provides a kind of overlay error compensation method, is used for two platform exposure benchs, and this method utilizes the difference of overlay offset of two workbenches of said exposure bench to compensate the wherein bigger workbench of overlay error.
Further, the difference of the overlay offset of two workbenches of said exposure bench is to obtain through following steps: measure wafer overlay situation on the line, obtain raw data; According to said raw data, calculate the overlay error modeling data; Said overlay error modeling data is divided into two groups of data that correspond respectively to two workbenches; Obtain overlay offset poor of said two workbenches according to said two groups of data.
Further, said overlay error modeling data comprises 10 groups of data, and wherein 6 groups corresponding to wafer, other 4 groups corresponding to exposure field.
Further, said 6 groups of data corresponding to wafer comprise: wafer is in the translational movement on X and the Y direction, wafer expansion amount, wafer rotation amount, the nonopiate situation of wafer on X and Y direction.
Further, said 4 groups of data corresponding to exposure field comprise: by exposure field rotation amount, exposure field expansion amount, exposure field asymmetric rotational amount, the exposure field asymmetric spreading amount of wafer with the upper module generation.
Further, said compensation work platform is to realize through the chuck of this workbench.
It is thus clear that above overlay error compensation method utilizes the difference of the overlay offset of two workbenches to compensate the wherein bigger workbench of overlay error.So, when reducing two overlays control differences between the workbench, the overlay error of workbench is controlled in the required scope, has improved the performance of semiconductor devices and produced yield.
Description of drawings
Fig. 1 is the schematic flow sheet of the overlay error compensation method that one embodiment of the invention provided;
Fig. 2 is the case line chart (box plot) of the translational movement (wafer translation X) of wafer on directions X when not adopting method provided by the present invention to compensate;
Fig. 3 compensates the case line chart (box plot) of the translational movement (wafer translation X) of back wafer on directions X for adopting method provided by the present invention.
Embodiment
For making technical characterictic of the present invention more obviously understandable,, the present invention is done further description below in conjunction with accompanying drawing and embodiment.
Inventor of the present invention finds in the test process to two platforms (twin stage) exposure bench; The overlay control expressive ability of two workbenches there are differences; In order to reduce this species diversity; The inventor utilizes the difference of the overlay offset of two workbenches to compensate one of them platform, so that their overlay control ability is suitable.And then consider the importance of overlay error for device performance; In compensation process; The overlay error of hoping two workbenches is all as far as possible little, produces yield to improve, and utilizes the difference of the overlay offset of two workbenches to compensate the wherein bigger workbench of overlay error for this reason.So, when reducing two overlays control differences between the workbench, the overlay error of workbench is controlled in the required scope, has improved the performance of semiconductor devices and produced yield.
In addition, this compensation method is used for the exposure process of certain one deck, not only can improves the influence of overlay error, do not need any parameter of renewal of the equipment simultaneously.Thereby can not impact other layer or other products.
Specifically, please refer to Fig. 1, it has provided the schematic flow sheet of the overlay error compensation method that one embodiment of the invention provided.As shown in the figure, comprise the steps:
S1: measure wafer overlay situation on the line, obtain raw data, the wafer of required measurement here is all wafers of on platform, handling certainly, comprises the wafer on first workbench and second workbench;
S2:, calculate the overlay error modeling data according to the raw data that measures;
S3: the overlay error modeling data is divided into two groups of data that correspond respectively to two workbenches;
S4: obtain the overlay offset of two workbenches according to said two groups of data, and then obtain overlay offset poor of two workbenches;
S5: utilize the bigger workbench of difference compensation overlay error of said overlay offset, promptly compensate the bigger workbench of overlay offset.
Above method is applied in the automatic control of board, just can reduces two overlays control differences between the workbench, simultaneously, the overlay error of workbench is controlled in the required scope.Particularly; Obtain an offset (offset that is in the step 4 to be obtained poor) through above method; And an interface is set on exposure bench, receive this offset, through the automated procedures of control board; In the task (job) that generates exposure machine, pass to the offset that obtains the workbench of required compensation.
Above method is write in the automated procedures that join board, when generating the job of exposure bench, pass to offset (offset that is in the step 4 to be obtained poor) workbench of required compensation.
In step S2; Said overlay error modeling data comprises 10 groups of data; Wherein 6 groups is the data corresponding to wafer (wafer); Comprise: wafer translational movement (comprising the translational movement on X and the Y both direction) (wafer translation X, Y), wafer expansion amount (comprising the expansion amount on X and the Y both direction) (waferexpansion), wafer rotation amount (wafer rotation), the nonopiate situation of wafer (wafernon-orthogonality); Other four groups is corresponding to the data of exposure field (shot), comprising: by exposure field rotation amount (intra field shot rotation), exposure field expansion amount (shotmagnification), exposure field asymmetric rotational amount (shot asymmetric rotation), the exposure field asymmetric spreading amount (shot asymmetric magnification) of wafer with the upper module generation.
Resulting these modeling datas and workbench are mapped, so just obtain setting up the modulus certificate, carry out modeling respectively, obtain the overlay error offset corresponding to two of two workbenches.On traditional handicraft, utilize resulting offset respectively the overlay compensation to be carried out in all workbench unifications.And the present invention utilizes the difference of the overlay offset of two workbenches to compensate the bigger workbench of overlay error; When reducing two overlay control differences between the workbench; The overlay error that does not influence under other product situation the workbench of the required layer of required product is controlled in the required scope, has improved the performance of semiconductor devices and has produced yield.In addition, because workbench often utilizes chuck (chuck) to fix wafer, so the compensation work platform is to realize through the chuck of this workbench.
Below, please refer to Fig. 2 to Fig. 3, it is respectively and does not adopt above method to compensate and adopt above method to compensate the case line chart (boxplot) of the translational movement (wafer translation X) of back wafer on directions X.Wherein, horizontal ordinate EPAFS02 represents device numbering, and suffix " _ 1 " is represented the chuck numbering with " _ 2 ", and promptly EPAFS02_1 represents the chuck of first workbench, and EPAFS02_2 represents the chuck of second workbench; Ordinate is represented the translational movement of wafer on directions X.As can beappreciated from fig. 2; When not compensating; Translational movement on the chuck of second workbench (EPAFS02_2) directions X (wafer translation X)-0.8122nm is higher than chuck (the EPAFS02_1)-1.807nm of first workbench, and the translational movement-1.807nm on the chuck of first workbench (EPAFS02_1) directions X do not meet necessary requirement (be not less than-1.5nm).And after the compensation; The translational movement-1.255nm on the chuck of second workbench (EPAFS02_2) directions X and chuck (the EPAFS02_1)-0.6259nm of first workbench meet necessary requirement (-more than the 1.5nm); It is thus clear that; Overlay error compensation method provided by the present invention is controlled at the overlay error of workbench in the required scope when reducing two overlays control differences between the workbench, has improved the performance of semiconductor devices and produced to be merely more than the yield for example; Be not that protection scope of the present invention should be as the criterion with the scope that claims are contained in order to qualification the present invention.
Claims (5)
1. overlay error compensation method; Be used for two platform exposure benchs; It is characterized in that; Comprise: utilize the difference of overlay offset of two workbenches of said exposure bench to compensate the wherein bigger workbench of overlay error, wherein, the difference of the overlay offset of two workbenches of said exposure bench is to obtain through following steps:
Measure wafer overlay situation on the line, obtain raw data;
According to said raw data, calculate the overlay error modeling data;
Said overlay error modeling data is divided into two groups of data that correspond respectively to two workbenches;
Obtain overlay offset poor of said two workbenches according to said two groups of data.
2. overlay error compensation method according to claim 1 is characterized in that, said overlay error modeling data comprises 10 groups of data, and wherein 6 groups corresponding to wafer, other 4 groups corresponding to exposure field.
3. overlay error compensation method according to claim 2 is characterized in that, said 6 groups of data corresponding to wafer comprise:
Wafer is in the translational movement on X and the Y direction, wafer expansion amount, wafer rotation amount, the nonopiate situation of wafer on X and Y direction.
4. overlay error compensation method according to claim 2 is characterized in that, said 4 groups of data corresponding to exposure field comprise:
By exposure field rotation amount, exposure field expansion amount, exposure field asymmetric rotational amount, the exposure field asymmetric spreading amount of wafer with the upper module generation.
5. overlay error compensation method according to claim 1 is characterized in that, said compensation work platform is to realize through the chuck of this workbench.
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| CN2009100521898A CN101900945B (en) | 2009-05-27 | 2009-05-27 | Overlay error compensation method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104656383A (en) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Exposure method, exposure system, and exposure device control system |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103063185B (en) * | 2012-12-31 | 2017-04-19 | 中国电子科技集团公司第四十五研究所 | Single-point method for confirming testing range of wafer |
| TW201520702A (en) * | 2013-11-19 | 2015-06-01 | Huang Tian Xing | Misalignment error compensation method, system, and patterning method |
| CN105225978B (en) * | 2014-06-17 | 2019-06-04 | 联华电子股份有限公司 | The bearing calibration of overlay error |
| US9530199B1 (en) * | 2015-07-13 | 2016-12-27 | Applied Materials Israel Ltd | Technique for measuring overlay between layers of a multilayer structure |
| CN109696804B (en) * | 2017-10-24 | 2021-07-09 | 长鑫存储技术有限公司 | Overlay offset measurement compensation method and device and storage medium |
| CN114721226B (en) * | 2021-01-04 | 2023-08-25 | 长鑫存储技术有限公司 | Photomask placement error correction method and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1493925A (en) * | 2002-09-10 | 2004-05-05 | ��ʽ����Orc������ | Exposure device and method for transfering photomask and workpiece |
| US6836093B1 (en) * | 1999-12-21 | 2004-12-28 | Nikon Corporation | Exposure method and apparatus |
| CN1828427A (en) * | 2006-04-14 | 2006-09-06 | 上海微电子装备有限公司 | Step scan photo-etching machine double-platform exchanging and positioning system |
| CN101138070A (en) * | 2005-08-05 | 2008-03-05 | 株式会社尼康 | Stage apparatus and exposure apparatus |
-
2009
- 2009-05-27 CN CN2009100521898A patent/CN101900945B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6836093B1 (en) * | 1999-12-21 | 2004-12-28 | Nikon Corporation | Exposure method and apparatus |
| CN1493925A (en) * | 2002-09-10 | 2004-05-05 | ��ʽ����Orc������ | Exposure device and method for transfering photomask and workpiece |
| CN101138070A (en) * | 2005-08-05 | 2008-03-05 | 株式会社尼康 | Stage apparatus and exposure apparatus |
| CN1828427A (en) * | 2006-04-14 | 2006-09-06 | 上海微电子装备有限公司 | Step scan photo-etching machine double-platform exchanging and positioning system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104656383A (en) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Exposure method, exposure system, and exposure device control system |
| CN104656383B (en) * | 2013-11-19 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | Exposure method and system, exposure sources control system |
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