CN101894281B - Baseband signal processing SOC chip of multi-protocol UHF RFID reader - Google Patents
Baseband signal processing SOC chip of multi-protocol UHF RFID reader Download PDFInfo
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Abstract
The invention discloses a baseband signal processing SOC chip of a multi-protocol UHF RFID reader, comprising a CPU module, a bus in a chip, a storage interface, a DAC output channel, an ADC input channel, a multi-protocol processing unit of an UHF RFID hardware, a man-machine interface, a high-speed communication interface, a low-speed communication interface, a timer module, a JTAG interface module and a master clock module; a high-speed system bus and a low-speed peripheral bus are connected together through a DMA controller and a bus bridge, and each bus is provided with an address decoder and a bus arbitrator; the CPU module, the storage interface, the man-machine interface, the multi-protocol processing unit, the JTAG interface module and the high-speed communication interface are connected with the high-speed system bus; and the low-speed communication interface, the timer module and the master clock module are connected with the low speed peripheral bus. The invention can conveniently realize a handheld UHF RFID reader with high integrated level, low cost, low power consumption and high generality.
Description
Technical field
The present invention relates to a kind of ultrahigh frequency radio frequency identification (RFID) reader digital baseband signal process chip, belong to digital baseband signal process chip technical field.
Background technology
Passive type super high frequency radio frequency identification UHF rfid system (working frequency range is 860MHz-960MHz) adopts the backscattered modulation pattern; Work in the far-field radiation district; Have reading/writing distance far away (can reach 3-10 rice), non-visual, characteristics such as read or write speed is fast, label is passive, make it be widely used in fields such as warehouse logistics, parking lot management, asset management, valuables antitheft.Passive type super high frequency radio frequency identification RFID system is made up of read write line, electronic tag and background application system, and wherein read write line and electronic tag are the keys of total system.Electronic tag internal passive and adopt the power supply of passive far end radio frequency, internal resource is limited, can't accomplish complicated signal Processing, and therefore, the design performance of read write line is the key point of total system performance in rfid system.
Ultrahigh frequency radio frequency identification (RFID) reader is divided into radio-frequency module and base band control module two parts from structure; As shown in Figure 1; The part that frame of broken lines is enclosed among the figure is a read write line, and wherein radio-frequency module mainly is made up of modulation-demodulation circuit and antenna, mainly accomplishes the modulation and demodulation of high-frequency signal; Emission and reception are the air wireless interface between label and the read write line.The base band control module mainly is made up of agreement control module, coding/decoding module, data check module, interface module etc.Its major function is the control radio system, realizes the codec functions to high-frequency signal, and realizes being similar to the UHF RFID standard agreement of ISO18000-6B/6C.Simultaneously, the application interface between realization and external unit or the main frame, the data communication between completion and the host computer.This shows that the base band control module is the core of whole rfid interrogator, is supporting whole system operation.Specifically, the main task of radio-frequency module is (1) emission 915MHz high-frequency signal, the active electron label, and energy is provided for electronic tag; (2) modulate emission signal is given electronic tag with data-signal through antenna transmission; (3) accept also demodulation from the signal of electronic tag.The main task of base band control module is (1) and application systems software communicates, and the action command that sends of executive system software; (2) Code And Decode of realization RF identification agreement; (3) communication process of control and RF tag; (4) realize the anticollision collision algorithm of blocking more; (5) data that transmit between read write line and the electronic tag are encrypted or deciphered; (6) realize the CRC Code And Decode.
For the handheld RFID read write line, its base band control module needs human interface function's (like LCD demonstration, keyboard, touch-screen etc.) and abundant communication interface (like RS232, Ethernet, USB, WiFi etc.) toward contact except accomplishing top function.
At present, ultrahigh frequency handheld RFID read write line, the mode of generally adopting CPU+FPGA or CPU+RFID special chip (like AS3990) realizes.These two kinds of methods all have certain defective.Wherein in the CPU+FPGA scheme, FPGA has accomplished the Base-Band Processing function, but user interface and communication interface are realized by CPU.The read write line deviser need be integrated in the two on the circuit board, the restriction condition that the communication speed between the two often becomes and improves the read write line performance, reduces read write line cost and power consumption.And many functions such as the advantage of CPU+RFID special chip (like AS3990) scheme to be the RFID special chip realized rfid interrogator Base-Band Processing, rf analog front-end handled, the power amplification of low magnitude and gain control; But the function about user's application interface still needs independent CPU to realize; Equally; Also need high-speed communication between CPU and the RFID special chip, the cost of manufacture of read write line is also very high.
SOC (System on Chip) is called system level chip, is functional modules such as peripheral hardware, storer, communication interface even A/D and D/A conversion in the needed various CPU of system, the sheet are integrated on the chip piece, i.e. SOC(system on a chip).SOC has improved level of integrated system, has reduced equipment cost, has improved reliability, also is convenient to realize simultaneously low-power consumption.
Summary of the invention
The present invention is directed to the deficiency that existing RFID base band signal process mode exists, provide a kind of reliability high, low in energy consumption multi-protocol UHF rfid interrogator baseband signal processing SOC chip.
Multi-protocol UHF rfid interrogator baseband signal processing SOC chip of the present invention adopts following technical solution:
This baseband signal processing SOC chip comprises CPU module, bus on chip, memory interface, DAC output channel, ADC input channel, UHF RFID hardware multi-protocols processing unit, man-machine interface, high-speed communication interface, low-speed communication interface, timer module, jtag interface module and major clock module; Bus on chip comprises high speed system bus and low speed peripheral bus, links together through dma controller and bus bridge between two buses, and every bus all is provided with address decoder and bus arbiter; CPU module, memory interface, man-machine interface, UHF RFID hardware multi-protocols processing unit, jtag interface module and high-speed communication interface all are connected with high speed system bus; Low-speed communication interface, timer module and major clock module are connected with the low speed peripheral bus; High-speed communication interface, DAC output channel and ADC input channel are connected with dma controller; In the CPU module, include the low power consumption control module that is used for controlling power management.
The DAC output channel comprises 3 tunnel 8 DAC output channels, and wherein 2 the tunnel are used for I passage and the Q passage baseband digital signal that output orthogonal is modulated needs, and other 1 tunnel 8 P passage DAC output channel is exported as the gain adjustment of power amplifier PA.
The ADC input channel comprises 2 tunnel 8 ADC input channels, is used to import I passage and the baseband digital signal of Q passage after the quadrature demodulation.
UHF RFID hardware multi-protocols processing unit: comprise coding module, decoder module, CRC check module and clock frequency division module four parts.
Man-machine interface comprises lcd controller and touch screen controller;
High-speed communication interface disposes 32 GPIO interfaces, pci bus interface and USB1.1 interface controller.
The low-speed communication interface configuration has UART interface, SPI interface module and IIS Audio Controller.
Timer module disposes 2 16 bit timing counter timers and real-time clock.
The present invention's various base band signal process functions that the UHF rfid interrogator is required, agreement realize that CPU that function, application and development are relevant and bus on chip function, sheet external tapping function, the gain control function of radio circuit, low power consumption control function are integrated together.Has CPU (is that OR1200 realizes based on the OpenRISC1200 that increases income) in the chip; Can Embedded Operating System (like Windows CE, Linux etc.); Can expand the storer of 4G Bytes capacity; Integrated ISO18000-6B/6C agreement, and provide a kind of open type software interface to realize other UHF RFID agreement, anti-collision algorithm, location algorithm even distributed data base and the middleware except that ISO18000-6B/6C.Can realize the hand-held UHF rfid interrogator of high integration, low cost, low-power consumption, high universalizable easily.
Description of drawings
Fig. 1 is the structured flowchart of existing rfid interrogator.
Fig. 2 is the structural principle block diagram of ultrahigh frequency RFID Base-Band Processing SOC chip of the present invention.
Fig. 3 is the structural principle block diagram that utilizes the hand-held UHF rfid interrogator of SOC chip realization of the present invention.
Fig. 4 is the inner structure synoptic diagram of multi-protocols processing unit.
Fig. 5 is the startup process flow diagram of ultrahigh frequency RFID Base-Band Processing SOC chip of the present invention.
Embodiment
As shown in Figure 2; Ultrahigh frequency RFID Base-Band Processing SOC chip of the present invention comprises CPU module, bus on chip, memory interface, DAC output channel, ADC input channel, UHF RFID hardware multi-protocols processing unit, man-machine interface, high-speed communication interface, low-speed communication interface, timer module, low power consumption control module and other modules
The CPU module: the SOC built-in chip type 32 bit CPU kernels (based on OR1200), this CPU core utilization instruction can be accomplished the functions such as coordination, configuration and duty detection to respectively forming module in the entire chip.Can embed various embedded OSs (like Windows CE or Linux etc.),, and good routine interface is provided for the user so that realize function more flexibly.In addition, can also carry out processing such as digital filtering, encryption, decoding, coding, decoding to baseband signal through the CPU executive software.
Bus on chip: the SCO chip internal has disposed two Wishbone buses, is respectively the system bus at a high speed and the peripheral bus of low speed.CPU, memory controller, lcd controller, touch screen controller and multi-protocols control module and communication interface USB at a high speed and PCI and GPIO interface controller all hang on the high speed system bus.And low-speed communication interface (as: SPI, PS/2, RS232, IIS and PWM etc.) and real-time clock RTC controller hang on the low speed peripheral bus.Link together through DMA and bus bridge between system bus and the peripheral bus.Every bus all has the address decoder of oneself, is convenient to work alone.High-speed communication interface (like USB and PCI and GPIO interface) and each AD/DA passage also can be accomplished data communication under the control of dma controller.In addition, the Wishbone bus adopts Master and Slaver control model, allows many Master, therefore need accomplish bus arbitration by bus arbiter.
Memory interface: the SOC chip can be expanded multiple memory devices, comprises EPROM, SRAM, DRAM, Flash etc., utilizes pci interface can also expand the SD card memory appts, and the extending space maximum can reach 4GBytes.
The DAC output channel: the SOC chip provides 3 tunnel 8 DAC passages, and wherein 2 the tunnel are used for I passage and the Q passage baseband digital signal that output orthogonal is modulated needs, and other 1 tunnel 8 P passage DAC passage is exported as the gain adjustment of power amplifier PA.
The ADC input channel: the SOC chip provides 2 tunnel 8 ADC passages, is used to import I passage and the baseband digital signal of Q passage after the quadrature demodulation.
UHF RFID hardware multi-protocols processing unit: the SOC chip configuration has hardware multi-protocols processing unit, can be in any switching between the multiple UHF RFID consensus standards such as ISO18000-6B, ISO18000-6C, EPC Global C1G2.Through this unit, can accomplish the PIE coding of baseband signal, FMO coding, Miller decoding, CRC check, the detection of each channel signal intensity, the execution of anti-collision algorithm produce frame synchronization sequence, the functions such as State Control that carry on an agreement and require.In addition, this protocol processing unit has been reserved open software protocol interface, and the mode of CPU executive software capable of using makes this SOC support other UHF RFID agreement except that agreements such as ISO18000-6B, ISO18000-6C, EPC Global C1G2.
Man-machine interface: the SOC chip configuration lcd controller and touch screen controller, can realize friendly human-machine interface function.
High-speed communication interface: the SOC chip configuration 32 GPIO interfaces, be convenient to expand other high-speed parallel equipment.Disposed pci bus interface, can expand Ethernet easily, high capacity External memory equipments such as the communication facilities of high speed such as Wi-Fi, USB2.0 and SD card.Disposed the USB1.1 interface controller, can provide USB master's (Host) interface and USB from (Device) interface.
The low-speed communication interface: the SOC chip configuration UART interface and SPI interface module, can realize some short-range communications.Dispose the IIS Audio Controller, can realize excellent voice playing and collection.
Timer module: the SOC chip configuration 2 16 bit timing counter timers, WatchDog Timer and PWM output function can be provided.Disposed real-time clock, can be the user provides precise time and calendar to show.
The low power consumption control module: multi-operation modes such as this chip supports power down, standby, work, wake up, and can individually the power supply of each interface module be controlled, be convenient to realize low power consumption control ability flexibly.
Also dispose jtag interface in addition, supported on-line debugging and program to download.The external crystal-controlled oscillation frequency of major clock module is 27MHz, can make CPU work predominant frequency reach 150MHz through inner PLL.Entire chip adopts single 5V power supply.
Utilize SOC chip of the present invention can realize the hand-held UHF rfid interrogator of high integration, low cost, low-power consumption, high universalizable easily; Its structure is illustrated in fig. 3 shown below; Visible by Fig. 3; SOC chip of the present invention has been exported the baseband signal (this signal has been accomplished coding according to protocol requirement) of necessary I passage of orthogonal modulation and Q passage; Be used for power amplifier gain adjustment P channel digital signal, this three road signal all needs external 8 DAC to convert the digital signal of output to simulating signal.The base-band analog signal of I passage and Q passage is crossed after bandpass filtering (BPF) and the power amplifier through orthogonal modulation (like LT5568), sends into antenna through circulator again, constitutes transmission channel.For receiving cable, this chip configuration input I passage and Q channel interface, be used for receiving through quadrature demodulation (like LT5516) and through low noise and amplify (LNA) and LPF (LPF), and then the base-band input signal behind ADC.
The functional structure of UHF RFID hardware multi-protocols processing unit is as shown in Figure 4, has comprised coding module, decoder module, CRC check module and clock frequency division module four parts.The course of work of this multi-protocols processing unit module is: clock division signal input back:
(1) cataloged procedure: after main frame (HOST) is given OR1200 processor instruction and information data; The OR1200 processor sends to coding module and the enabled instruction of CRC check module; Coding module can be returned to answer signal of OR1200 processor after receiving enabled instruction; Subsequently, the OR1200 processor can import data message into coding module and CRC check module.After coded data is accomplished, the CRC check value that produces is sent to scrambler, send through output channel then.
(2) decode procedure: after the OR1200 processor detects the information that electronic tag sends over; Can send to decoder module and the enabled instruction of CRC check module respectively; Decoder module can be returned to answer signal of OR1200 processor after receiving enabled instruction, thereupon, and after decoded data information is accomplished; Can data message and proof test value be sent to the OR1200 processor; Data message can be sent to main frame (HOST), LCD display or storer with the result after necessarily handling through the OR1200 processor.
The course of work of ultrahigh frequency radio frequency identification (RFID) reader Base-Band Processing SOC chip of the present invention is divided into start-up course and course of normal operation.Wherein the flow process of start-up course is as shown in Figure 5:
After powering on; At first accomplish the reset function of CPU OR1200 and each functional module; Begin to read and executive system initialization (Bootloader) program from fixed address then; Completion is to each functional module parameter configuration of (comprising: clock module, interruption and power management module, memory control module, LCD control module and touch screen control module, multi-protocols processing unit module and AD/DA control module, DMA control module, various communication interface moduless etc.), and on LCD output initialization interface.Read user program from the assigned address program storage, display of user interfaces.Load the local data library manager.From I/Q passage DAC outgoing carrier output signal, and make output signal strength maximum (being that P passage ADC output is maximum), open I/Q passage ADC, start the multi-protocols processing module, whether inspection has label to exist.If label is arranged then the display label data, and its information is counted database.If there is not label, then launch carrier wave continuously and read the ADC channel data, if the 5s clock does not all have the label response data then changes low-power consumption mode over to continuously, so far, start-up course finishes.
In course of normal operation; Accomplish the read-write of label data by application call read write line running program; With data interaction and database synchronization, multimedia and other user's appointed function of host computer, the concrete operations content is relevant with user application.
Claims (6)
1. a multi-protocol UHF rfid interrogator baseband signal processing SOC chip comprises CPU module, bus on chip, memory interface, DAC output channel, ADC input channel, UHF RFID hardware multi-protocols processing unit, man-machine interface, high-speed communication interface, low-speed communication interface, timer module, jtag interface module and major clock module; It is characterized in that: bus on chip comprises high speed system bus and low speed peripheral bus, links together through dma controller and bus bridge between two buses, and every bus all is provided with address decoder and bus arbiter; CPU module, memory interface, man-machine interface, UHF RFID hardware multi-protocols processing unit, jtag interface module and high-speed communication interface all are connected with high speed system bus; Low-speed communication interface, timer module and major clock module are connected with the low speed peripheral bus; High-speed communication interface, DAC output channel and ADC input channel are connected with dma controller; In the CPU module, include the low power consumption control module; Said DAC output channel comprises 3 tunnel 8 DAC output channels, and wherein 2 the tunnel are used for I passage and the Q passage baseband digital signal that output orthogonal is modulated needs, and other 1 tunnel 8 P passage DAC output channel is exported as the gain adjustment of power amplifier PA; Said ADC input channel comprises 2 tunnel 8 ADC input channels, is used to import I passage and the baseband digital signal of Q passage after the quadrature demodulation.
2. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1; It is characterized in that said UHF RFID hardware multi-protocols processing unit: comprise coding module, decoder module, CRC check module and clock frequency division module four parts.
3. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1 is characterized in that said man-machine interface comprises lcd controller and touch screen controller;
4. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1 is characterized in that said high-speed communication interface disposes 32 GPIO interfaces, pci bus interface and USB1.1 interface controller.
5. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1 is characterized in that said low-speed communication interface configuration has UART interface, SPI interface module and IIS Audio Controller.
6. multi-protocol UHF rfid interrogator baseband signal processing SOC chip according to claim 1 is characterized in that, said timer module disposes 2 16 bit timing counter timers and real-time clock.
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| CN102663458B (en) * | 2012-03-16 | 2015-03-25 | 江苏瑞福智能科技有限公司 | Multi-core UHF RFID reader-writer realized by application software |
| CN103353944A (en) * | 2013-04-27 | 2013-10-16 | 无锡昶达信息技术有限公司 | Baseband control chip and ultrahigh-frequency radio frequency read-write device |
| CN103235961A (en) * | 2013-04-27 | 2013-08-07 | 无锡昶达信息技术有限公司 | Base band control chip and ultrahigh frequency radio-frequency identification read-write device |
| CN103258228A (en) * | 2013-04-27 | 2013-08-21 | 无锡昶达信息技术有限公司 | Ultrahigh frequency RFID reader, base band system on chip (SOC) and port control method |
| CN103401654A (en) * | 2013-08-13 | 2013-11-20 | 南京中科微电子有限公司 | Dual-mode digital baseband structure of chip of reader |
| CN104239276A (en) * | 2014-09-05 | 2014-12-24 | 四川和芯微电子股份有限公司 | SOC (System On Chip) |
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| CN104680214B (en) * | 2015-03-13 | 2017-07-07 | 福建爱特点信息科技有限公司 | Multi-protocol UHF rfid interrogator digital baseband system |
| CN105137863B (en) * | 2015-07-31 | 2018-05-18 | 上海卫星工程研究所 | Spacecraft control manages SoC chip |
| CN105656712B (en) * | 2015-12-22 | 2019-01-29 | 山东大学 | A kind of RFID protocol uniformity test platform and its working method based on ZYNQ |
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| CN112860620B (en) * | 2019-11-28 | 2024-04-26 | 科大国盾量子技术股份有限公司 | SOC framework chip for QKD system |
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| CN113792000B (en) * | 2021-11-12 | 2022-02-25 | 南京沁恒微电子股份有限公司 | Microcontroller chip containing multi-protocol communication interface peripheral and operation method thereof |
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