CN112860620B - SOC framework chip for QKD system - Google Patents
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Abstract
The invention discloses an SOC framework chip for a QKD system, which comprises: a first interconnect bus; the QKD module is connected with the first interconnection bus and is used for being connected with one optical quantum communication device through a first type of peripheral interface connected with the first interconnection bus so as to perform data interaction with the connected optical quantum communication device; the second interconnection bus is connected with the first interconnection bus through a first bus bridge and is connected with the optical quantum communication equipment through a second type of peripheral interface so as to acquire working parameters of the optical quantum communication equipment; and the CPU subsystem is connected with the first interconnection bus and is connected with an interrupt controller. The technical scheme of the invention provides an SOC framework chip for a QKD system, all components in the chip are integrated integrally, the chip size is small, a data processing and control subsystem for the QKD system is not required to be built by adopting separated electronic components, and the use is convenient.
Description
Technical Field
The present invention relates to the field of Quantum Key Distribution (QKD) technology, and more particularly, to a system-on-a-chip (SOC) architecture chip for a QKD system.
Background
The current QKD (Quantum Key Distribution, QKD) system basically adopts the traditional photoelectric technology and ethernet to complete the processes of light quantum transmission, detection, data interaction between transmitting and receiving parties, data processing and the like based on the BB84 protocol, so as to refine the secure quantum key. The QKD system is composed of optical signal transmitting equipment and optical signal detecting equipment, and the optical signal transmitting equipment and the optical signal detecting equipment are connected by optical fibers to form an optical quantum channel. QKD systems include optical and electrical signal conditioning in signal form, and functionally spectral sources, detection and data processing, and information interaction.
In terms of functional distinction, the present QKD system forms a system configuration that is modularized with three parts, namely a light source subsystem, a receiving subsystem, data processing and control, as shown in fig. 1, fig. 1 is a schematic diagram of the QKD system, and has an optical signal transmitting device 11 and an optical signal detecting device 12. The optical signal transmission device 11 has a light source subsystem 112 and a data processing and control subsystem 111, the data processing and control subsystem 111 controlling the light source subsystem 112 to transmit the encoded optical signal to the optical signal detection device 12. The optical signal detection device 12 has a receiving subsystem 121 and a data processing and control subsystem 122, the data processing and control subsystem 122 controlling the receiving subsystem 121 to decode and detect the optical signal to refine the secure quantum key.
Because QKD is an emerging field of information technology, there is currently no application specific integrated circuit chip (ASIC) for a QKD system.
Disclosure of Invention
In view of this, the present application provides an SOC skeleton chip for a QKD system, the scheme being as follows:
an SOC backbone chip for a QKD system having two optical quantum communication devices in quantum communication, the SOC backbone chip comprising:
A first interconnect bus;
The first type of peripheral interfaces are connected with the first interconnection bus and are used for connecting the optical quantum communication equipment;
The QKD module is connected with the first interconnection bus and is used for carrying out data interaction with the optical quantum communication equipment connected with the chip to complete a preset QKD algorithm;
The second interconnection bus is connected with the first interconnection bus through a first bus bridge and connected with the light quantum communication equipment through a second type of peripheral interfaces so as to acquire working parameters of the light quantum communication equipment;
the CPU subsystem is connected with the first interconnection bus and is connected with an interrupt controller, and the CPU subsystem is used for executing at least one function of system start-stop, hardware parameter configuration, peripheral driving, application end command analysis and issuing, data scheduling and flow management.
Preferably, in the SOC frame chip, the SOC frame chip further includes:
and the application port is connected with the first interconnection bus and is used for outputting a quantum key.
Preferably, in the SOC frame chip, the two optical quantum communication devices are an optical signal transmitting device and an optical signal detecting device respectively;
The first type of peripheral interface comprises: the first peripheral interface is used for connecting the photon detector of the optical signal detection equipment to complete the configuration of the encoding parameters of the off-chip device and the reading of the detection result.
Preferably, in the SOC frame chip, the two optical quantum communication devices are an optical signal transmitting device and an optical signal detecting device respectively;
The first type of peripheral interface comprises: the second external interface is connected with the luminous coding and control module inside the chip and is used for being connected with the light source subsystem of the optical signal transmitting equipment, and the luminous coding and control module is used for providing a light source driving signal for the light source subsystem through the second external interface.
Preferably, in the SOC skeleton chip described above, the SOC skeleton chip has an on-chip true random number generator;
The first type of peripheral interface further comprises: the third peripheral interface is used for connecting a peripheral random number generator, and the third peripheral interface is connected with the on-chip true random number generator through a gating device and the luminous coding and control module.
Preferably, in the SOC frame chip, the SOC frame chip further includes: the third type of peripheral interfaces are connected with a second bus bridge through a third interconnection bus independently, and the second bus bridge is connected with the first interconnection bus;
the third type of peripheral interfaces are used for connecting an external DDR3 chip, so that the SOC framework chip is connected with external data and a programmer to form a working system.
Preferably, in the SOC architecture chip, the light emitting coding and control module is connected to the third type of peripheral interfaces through a third interconnection bus alone; the QKD module interfaces with the third class of peripherals solely through one of the third interconnect buses.
Preferably, in the SOC frame chip, the SOC frame chip further includes: and a fourth type of peripheral interfaces respectively connected with the QKD module and the first interconnection bus, wherein the fourth type of peripheral interfaces are used for connecting with an Ethernet PHY chip to form an Ethernet.
Preferably, in the SOC frame chip, the SOC frame chip further includes: and a fifth type of peripheral interface connected with the first interconnection bus, wherein the fifth type of peripheral interface is used for connecting the external program flash memory.
Preferably, in the SOC architecture chip, at least the CPU subsystem and the QKD module are each connected to a memory.
As can be seen from the above description, the SOC skeleton chip for the QKD system according to the embodiment of the present invention includes: a first interconnect bus; the QKD module is connected with the first interconnection bus and is used for being connected with one optical quantum communication device through a first type of peripheral interface connected with the first interconnection bus so as to perform data interaction with the connected optical quantum communication device, and a preset QKD algorithm is completed; the second interconnection bus is connected with the first interconnection bus through a first bus bridge and connected with the light quantum communication equipment through a second type of peripheral interfaces so as to acquire working parameters of the light quantum communication equipment; the CPU subsystem is connected with the first interconnection bus and is connected with an interrupt controller, and the CPU subsystem is used for executing at least one function of system start-stop, hardware parameter configuration, peripheral driving, application end command analysis and issuing, data scheduling and flow management. The technical scheme of the invention provides an SOC framework chip for a QKD system, all components in the chip are integrated integrally, the chip size is small, a data processing and control subsystem for the QKD system is not required to be built by adopting separated electronic components, and the use is convenient.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a QKD system;
FIG. 2 is a diagram of an SOC architecture chip for a QKD system according to an embodiment of the present invention;
FIG. 3 is another SOC architecture chip for a QKD system provided in an embodiment of the present invention;
FIG. 4 is a schematic diagram of yet another SOC architecture chip for a QKD system according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a further SOC architecture chip for a QKD system according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a further SOC skeleton chip for a QKD system, provided in accordance with an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The traditional photoelectric technology has no integrated circuit chip specially used for the QKD system, besides a small quantity of optical devices and a small quantity of customized products, the traditional QKD system is built by adopting a large quantity of commercial and civil universal chips in the aspects of a light source subsystem and a receiving subsystem, and is realized by adopting one to a plurality of FPGA (field programmable gate array), a memory, a universal processor, a network processor and other electronic components in the aspects of data processing and control, so that at least the following major defects exist:
First, equipment is bulky, and is with high costs, and the consumption is great.
Secondly, the key equipment is easy to be attacked by a network and a side channel, if the existing equipment is basically commercial Ethernet as an interaction channel, a commercial protocol TCP/IP protocol is adopted at a network port, and an attacker is easy to attack the equipment; moreover, a plurality of PCB boards are used for connecting and constructing the data processing and control subsystem, more data interfaces can be exposed, and more side channels are left for the attacker to attack conveniently.
Third, a significant feature of QKD systems is that the final secure key generation rate is not high, which is a significant feature of QKD systems in that the system data processing throughput is required to be high, e.g., for 100Km fiber QKD systems, the final system rate is approximately 100kbps even when the optical quantum transmitting device is transmitting photons at GHz operating frequency, while in data processing, the system must be capable of handling 10Gbps data throughput. Because the prior art adopts the FPGA to complete the algorithm data processing, all the data processing is completed by the hardware module, all the data processing conforms to a single flat structure, the subsequent data processing can be started after the completion of the prior data processing, the overhead of temporary data storage is increased, and the throughput rate of the whole data processing cannot be improved.
Fourth, the same device of the prior art architecture cannot adapt to different QKD application scenarios and code rate requirements.
In order to solve the above problems, the embodiment of the invention provides a design scheme of an SOC chip for a QKD system, which can complete data processing based on BB84 protocol, and realize key control and status parameter monitoring of light source and detector in the QKD system.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 2, fig. 2 is a SOC skeleton chip for a QKD system provided in an embodiment of the present invention, where the QKD system has two optical quantum communication apparatuses for quantum communication, and one of the two optical quantum communication apparatuses is an optical signal transmitting apparatus, and the other is an optical signal detecting apparatus, and the optical signal transmitting apparatus structure and the optical signal detecting apparatus structure in the two optical quantum communication apparatuses may be in a conventional QKD system manner, and the embodiment of the present invention is not limited thereto specifically.
The illustrated SOC skeleton chip 10 includes: a first interconnection bus 11; a first type peripheral interface D1 connected to the first interconnection bus 11; the QKD module 12 is connected with the first interconnection bus, and the QKD module 12 is used for performing data interaction with the optical quantum communication device connected with the chip to complete a preset QKD algorithm; the second interconnection bus 13 is connected with the first interconnection bus 11 through a first bus bridge 14, and the second interconnection bus 13 is connected with the optical quantum communication device through a second type peripheral interface D2 to obtain working parameters of the optical quantum communication device; the CPU subsystem 15 is connected to the first interconnection bus 11, and is connected to an interrupt controller 16, where the CPU subsystem 15 is configured to perform at least one function of system start-stop, hardware parameter configuration, peripheral driver, application command parsing and issuing, data scheduling, and flow management.
The first interconnect bus 11 may be an AHB bus. The second interconnection bus 13 may be an APB bus. The first bus bridge 14 may be an AHB-2-APB bridge. QKD module 12 can execute all QKD algorithms associated with a communication protocol, such as the BB84 protocol, based on an existing QKD communication protocol to effect QKD communication, the particular algorithm being a standard algorithm under the corresponding communication protocol, and can be implemented based on existing software and hardware schemes, as embodiments of the invention are not limited in this regard.
The working parameters of the optical quantum communication device comprise the light intensity parameter of a light source in the optical signal sending device, the temperature parameter of a detector in the optical signal detecting device and the like. The second type of peripheral interface D2 may be arranged to connect to a plurality of low-speed peripheral interfaces 17 via a multiplexer Pin MUX and to the second interconnect bus 13 via the low-speed peripheral interfaces 17. The low-speed peripheral interface 17 includes two i2c interfaces, two uart interfaces, two spi interfaces, two RTC interfaces, one Timer interface, and two gpio interfaces. The number and model of the low-speed peripheral interfaces 17 may be set based on the chip communication requirements, and are not particularly limited. Each low-speed peripheral interface 17 is connected to the second interconnect bus 13 on-chip, and external signals can be configured by software in different combinations to be connected to a total of 64 output pins through the multiplexer Pin MUX.
Optionally, in the SOC architecture chip according to the embodiment of the present invention, at least the CPU subsystem 15 and the QKD module 12 are respectively connected to a memory, and the memory may be an SRAM (static random access memory). The specific memory amount and layout can be set based on the chip usage requirements, and are not limited to the manner described in the embodiments of the present invention.
Referring to fig. 3, fig. 3 is another SOC frame chip for a QKD system according to an embodiment of the present invention, where the manner shown in fig. 3 is based on the manner shown in fig. 2, and further includes: an application port 18 connected to the first interconnection bus 11, the application port 18 being configured to output a quantum key. The application port 18 is a GMAC compliant port.
As described above, the two optical quantum communication devices in the QKD system are an optical signal transmitting device and an optical signal detecting device, respectively, and the SOC skeleton chip may be as shown in fig. 4.
Referring to fig. 4, fig. 4 is a schematic diagram of another SOC architecture chip for a QKD system according to an embodiment of the present invention, and the manner shown in fig. 4 may be based on the manner shown in fig. 2 or fig. 3, where the first type of peripheral interface D1 includes: and the first peripheral interface D11 is used for connecting a photon detector of the optical signal detection equipment, and finishing the configuration of the encoding parameters of the off-chip device and the reading of detection results. The first peripheral interface D11 is connected to the first interconnection bus 11 through an on-chip TDC interface and a photon information decoding module.
In the manner shown in fig. 4, the SOC architecture chip is used for data processing and control of the optical signal detection device in the QKD system, and may be connected to the detector in the optical signal detection device only through the first peripheral interface D11, and may detect the working parameters of the elements in the optical signal detection device through the second peripheral interface D2.
As described above, the two optical quantum communication devices in the QKD system are an optical signal transmitting device and an optical signal detecting device, respectively, and the SOC skeleton chip may also be as shown in fig. 5.
Referring to fig. 5, fig. 5 is a schematic diagram of another SOC architecture chip for a QKD system according to an embodiment of the present invention, and the manner shown in fig. 5 may be based on the manner shown in fig. 2 or fig. 3, where the first type of peripheral interface D1 includes: the second external interface D12 is connected with the light emitting coding and control module 19 inside the chip, the second external interface D12 is used for connecting the light source subsystem of the light signal transmitting device, and the light emitting coding and control module 19 is used for providing a light source driving signal for the light source subsystem through the second external interface D12.
Alternatively, as shown in fig. 5, the SOC skeleton chip 10 has an on-chip True Random Number Generator (TRNG) 20; the first class peripheral interface D1 further includes: the third peripheral interface D13 is used for connecting with a peripheral random number generator, and the third peripheral interface D13 and the on-chip true random number generator 20 are connected with the luminous coding and control module 19 through a gate 21. The light emitting encoding and control module 19 performs random number control on the optical signal transmission device in the QKD system based on two random number generators.
In the manner shown in fig. 5, the SOC architecture chip is used for data processing and control of the optical signal transmission device in the QKD system, and may be connected to the light source subsystem in the optical signal transmission device only through the second external interface D12, and may detect the working parameters of the elements in the optical signal transmission device through the second external interface D2.
The SOC skeleton chip 10 according to each of the above embodiments further includes: a third type of peripheral interface D3, where the third type of peripheral interface D3 is connected to the second bus bridge 21 through a third interconnection bus alone, and the second bus bridge 21 is connected to the first interconnection bus 11; the third interconnect bus is an AXI bus. The third type of peripheral interface D3 is used to connect to an external DDR3 chip, so that the SOC frame chip 10 connects to external data and a programmer to form a working system.
As shown in fig. 5, the light emitting encoding and control module 19 is connected to the third type of peripheral interface D3 through one of the third interconnection buses alone; the QKD module 12 is coupled to the third class peripheral interface D3 via only one of the third interconnect buses.
The SOC frame chip according to each of the foregoing embodiments further includes: and a fourth type of peripheral interface D4 connected to the QKD module 12 and the first interconnection bus 11, respectively, where the fourth type of peripheral interface D4 is used to connect to an ethernet PHY chip to form an ethernet network. The fourth type of peripheral interface D4 is an interface of the TCP/IP protocol and the GMAC protocol.
The SOC frame chip according to each of the foregoing embodiments further includes: and a fifth type of peripheral interface D5 connected to the first interconnection bus 11, where the fifth type of peripheral interface D5 is used for connecting an external program flash memory. The fifth type of peripheral interface D5 may be eMMc interfaces.
Based on the above embodiments, the SOC skeleton chip may also be shown in fig. 6, where fig. 6 is another SOC skeleton chip for a QKD system according to an embodiment of the present invention, and in this manner, the SOC skeleton chip has both a peripheral interface for connecting an optical signal transmitting device and an optical signal detecting device in the QKD system and a built-in functional module, and at this time, when the chip works, the SOC skeleton chip may selectively connect one of the optical signal transmitting device and the optical signal detecting device to perform data processing and control.
In the above embodiments, the SOC skeleton chip may be configured to further include a DMA controller connected to the first interconnection bus 11.
In the embodiment of the present invention, the types of each interconnection bus, each interface and each bus bridge can be selected to meet the preset communication standard based on the requirements, and the types of each interconnection bus, each interface and each bus bridge in the embodiment of the present invention are not limited to the modes described in the embodiment of the present invention.
The structure and the working principle of the SOC frame chip shown in fig. 6 in the embodiment of the present invention are described below, but the structure and the working principle of the SOC frame chip that can only be connected to a set one of optical signal transmission and detection devices in the QKD system can be referred to the following description, and will not be described in detail.
The modules inside the chip are mostly connected to the network of the first interconnection bus 11, and different modules are set to be the master and slave identities of the first interconnection bus 11 according to the data transmission priority and the control requirement. The second interconnection bus 13 is connected to the network of the first interconnection bus 11 by a first bus bridge 14, and the third type of peripheral interface D3 is connected to the network of the first interconnection bus 11 by a second bus bridge 21. In addition, the light emitting encoding and control module 19 is directly connected to the third type of peripheral interface D3 as a channel for transmitting the original photon information stored to the external DDR, and is not interconnected through the first interconnection bus 11.
The SOC framework chip is connected with an external subsystem through four peripheral interfaces: ① Outputting a light source driving signal to the light source subsystem through a second external interface D12 supporting the high-speed signal; ② The external TDC is connected through a first peripheral interface D11 to finish the configuration of the external TDC and the reading of the measurement result; ③ The fourth type of peripheral interface D4 is connected with the Ethernet PHY chip to form Ethernet connection; ④ The quantum key is output through the application port 18.
The SOC framework chip is required to be connected with external data and a programmer to form a self working system, wherein external DDR3 chip particles are connected through a third type of peripheral interfaces D3; the external program Flash memory (Flash) is connected through a fifth type of peripheral interface D5. In addition, the SOC framework chip is connected with corresponding ports of the light source and the receiving subsystem through a low-speed peripheral interface 17 so as to monitor the light source or the detector; the third peripheral interface D13 for transmitting high-speed signals is connected with an external high-speed random number generator and reads in random numbers.
The SOC chip adopts a brand new data processing and control framework system, integrates all functions of QKD algorithm data processing, light source and detector interfaces, an interaction network, on-chip and off-chip storage and interfaces and the like, embeds a CPU IP core in the chip, connects each data processing and control hardware module to an internal bus, adopts software to schedule the flow direction of data, and finally completes the extraction of quantum keys through the cooperative work of software and hardware.
QKD module 12 is a general term for a macroblock that performs all of the algorithmic functions of quantum key distribution, including optical signaling device macroblocks and/or optical signal detection device macroblocks. The SRAM is a generic term of all on-chip memories for completing the quantum key distribution function, and in one mode of the embodiment of the present invention, the on-chip SRAM includes 16 SRAM blocks with different sizes, and the SRAM blocks are configured near different QKD sub-functional modules for data caching.
The CPU subsystem 15 in the chip includes a CPU, and completes system start-stop, hardware configuration and peripheral driving, application command analysis and issue, data scheduling, flow management, and the like through software execution. The CPU and software are adopted to realize flow management of quantum key generation, control dimension of data processing is increased, pipeline management of data processing flow can be realized, and overall data processing throughput rate is improved. The same chip can be selected from the optical signal transmitting device and the optical signal detecting device by configuring the system through software, and various luminous rates can be selected by configuring the software.
The SOC framework chip provided by the embodiment of the invention can greatly reduce the volume of equipment, simplify the system constitution, enhance the reliability of the system, improve the system performance, reduce the side channel attack point in key equipment, reduce the cost and the power consumption of the system, and is beneficial to the modularization of a QKD system and the formation of industry standards.
In the present specification, each embodiment is described in a progressive manner, or a parallel manner, or a combination of progressive and parallel manners, and each embodiment is mainly described as a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or device comprising the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. An SOC backbone chip for a QKD system having two optical quantum communication devices in quantum communication, the SOC backbone chip comprising:
A first interconnect bus;
The first type of peripheral interfaces are connected with the first interconnection bus and are used for connecting the optical quantum communication equipment;
The QKD module is connected with the first interconnection bus and is used for carrying out data interaction with the optical quantum communication equipment connected with the chip to complete a preset QKD algorithm;
The second interconnection bus is connected with the first interconnection bus through a first bus bridge and connected with the light quantum communication equipment through a second type of peripheral interfaces so as to acquire working parameters of the light quantum communication equipment; the second type of peripheral interfaces are connected with a plurality of low-speed peripheral interfaces through a multiplexer and are connected with the second interconnection bus through the low-speed peripheral interfaces;
The CPU subsystem is connected with the first interconnection bus and is connected with an interrupt controller, and the CPU subsystem is used for executing at least one function of system start-stop, hardware parameter configuration, peripheral driving, application end command analysis and issuing, data scheduling and flow management;
The two optical quantum communication devices are respectively an optical signal transmitting device and an optical signal detecting device; the first type of peripheral interface comprises: the second external interface is connected with the luminous coding and control module inside the chip and is used for connecting a light source subsystem of the optical signal transmitting device, the luminous coding and control module is used for providing a light source driving signal for the light source subsystem through the second external interface, and the luminous coding and control module is directly connected to a third type of external interface to serve as a channel for transmitting original photon information to be stored in an external DDR (double data rate) and is not interconnected through the first interconnection bus; the SOC framework chip is provided with an on-chip true random number generator, the first type of peripheral interfaces further comprise a third peripheral interface used for connecting the peripheral random number generator, and the third peripheral interface is connected with the on-chip true random number generator through a gating device and the luminous coding and control module.
2. The SOC frame chip of claim 1, further comprising:
and the application port is connected with the first interconnection bus and is used for outputting a quantum key.
3. The SOC skeleton chip of claim 1, wherein the two optical quantum communication devices are an optical signal transmitting device and an optical signal detecting device, respectively;
The first type of peripheral interface comprises: the first peripheral interface is used for connecting the photon detector of the optical signal detection equipment to complete the configuration of the encoding parameters of the off-chip device and the reading of the detection result.
4. The SOC backbone chip of claim 1, wherein the third class of peripheral interfaces are connected to a second bus bridge solely by a third interconnect bus, the second bus bridge connecting the first interconnect bus;
the third type of peripheral interfaces are used for connecting an external DDR3 chip, so that the SOC framework chip is connected with external data and a programmer to form a working system.
5. The SOC frame chip of claim 4 wherein the light emitting encoding and control module is interfaced with the third class of peripherals solely via one of the third interconnect buses; the QKD module interfaces with the third class of peripherals solely through one of the third interconnect buses.
6. The SOC frame chip of claim 1, further comprising: and a fourth type of peripheral interfaces respectively connected with the QKD module and the first interconnection bus, wherein the fourth type of peripheral interfaces are used for connecting with an Ethernet PHY chip to form an Ethernet.
7. The SOC frame chip of claim 1, further comprising: and a fifth type of peripheral interface connected with the first interconnection bus, wherein the fifth type of peripheral interface is used for connecting the external program flash memory.
8. SOC architecture chip according to any of claims 1-7, characterized in that at least the CPU subsystem and the QKD module are each connected with a memory.
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