CN101887894A - Static discharge protective device - Google Patents
Static discharge protective device Download PDFInfo
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- CN101887894A CN101887894A CN2009101391961A CN200910139196A CN101887894A CN 101887894 A CN101887894 A CN 101887894A CN 2009101391961 A CN2009101391961 A CN 2009101391961A CN 200910139196 A CN200910139196 A CN 200910139196A CN 101887894 A CN101887894 A CN 101887894A
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Abstract
The invention discloses a static discharge protective device. The static discharge protective device comprises a substrate, a first doping area, a first grid, a second doping area, a second grid and a third doping area, wherein the substrate is provided with a first electric conduction pattern; the first doping area is provided with a second electric conduction pattern and is formed in the substrate; the first grid is formed on the substrate; the second doping area is provided with a second electric conduction pattern and is formed in the substrate; the first doping area, the second doping area and the first grid form a transistor; the second grid is formed on the substrate and is separated from the first grid; the third doping area is provided with a first electric conduction pattern, is formed in the substrate and is separated from the second doping area; and the first doping area, the third doping area and the second grid form a discharge element. The static discharge protective device of the invention can effectively protect integrated circuits, prevent the integrated circuits from being damaged due to occasional ESD events and simultaneously does not increase the complexity of the circuit layout.
Description
Technical field
The invention relates to a kind of electrostatic discharge protective device, particularly relevant for a kind of high-pressure electrostatic discharge protector.
Background technology
The static discharge of integrated circuit (ElectroStatic Discharge; Hereinafter to be referred as ESD) incident, refer to and have high-tension electrostatic charge, by the dispose procedure of integrated circuit (IC) chip.Electrostatic charge even so is few usually, and still, because high-tension reason, also suitable considerable of the transient energy of its release if not kindly add processing, tends to cause burning of integrated circuit.
Therefore, ESD has been that reliability important in the semiconductor product is investigated one of index.Relatively have two kinds for ESD that common people were familiar with tests, the human body discharge mode (human body model, HBM) and the machine discharge mode (machine model, MM).The integrated circuit of general commercial usefulness all must possess to a certain degree HBM and the tolerance level of MM, just can sell, otherwise integrated circuit is very easy to damage because of accidental esd event.Also therefore, how making an efficient ESD protector/element, protect integrated circuit, also is that industry is constantly inquired into and the problem of studying always.
In order to bear high voltage, traditional high pressure ESD element normally is made of circuit mesohigh element.Yet the metal coiling of high voltage device can influence Electric Field Distribution, thereby causes damage of circuit.
Known settling mode is that the end with high voltage device is designed to independently contact mat (PAD).But, revise resulting high pressure ESD element by high voltage device and also must have a contact mat independently.Therefore, increase the complexity of circuit layout, and make the area of integrated circuit significantly increase.
Summary of the invention
The invention provides a kind of electrostatic discharge protective device, described electrostatic discharge protective device comprises a substrate, one first doped region, a first grid, one second doped region, a second grid and one the 3rd doped region.Substrate has one first conductivity.First doped region has one second conductivity, and is formed among the substrate.First grid is formed on the substrate.Second doped region has second conductivity, and is formed among the substrate.First, second doped region and first grid constitute a transistor.Second grid is formed on the substrate, and is isolated from each other with first grid.The 3rd doped region has first conductivity, is formed among the substrate, and isolates mutually with second doped region.The first, the 3rd doped region and second grid constitute an arresting element.
The present invention provides a kind of electrostatic discharge protective device in addition, and described electrostatic discharge protective device comprises a substrate, one first doped region, a first grid, one second doped region, one the 3rd doped region and one the 4th doped region.Substrate has one first conductivity.First doped region has one second conductivity, and is formed among the substrate.First grid is formed on the substrate.Second doped region has second conductivity, and is formed among the substrate.First, second doped region and first grid constitute a transistor.The 3rd doped region has first conductivity, is formed among the substrate, and isolates mutually with second doped region.The 4th doped region has second conductivity, is formed among the substrate, and isolates mutually with second doped region.The first, the 3rd, the 4th doped region and second grid constitute an arresting element.
Electrostatic discharge protective device of the present invention can be protected integrated circuit effectively, avoids it and damages because of accidental esd event, does not increase the complexity of circuit layout simultaneously.
Description of drawings
Figure 1A is a possible embodiment of ESD protector of the present invention;
Figure 1B is another possibility embodiment of ESD protector of the present invention;
Fig. 2 is the A-A of Figure 1B " generalized section;
Fig. 3 A is the B-B of Figure 1B " generalized section;
Fig. 3 B is the circuit diagram of ESD protector of the present invention;
Fig. 4 is another possibility embodiment of arresting element.
Drawing reference numeral
100,100 ': the ESD protector;
111,112,121,171,172,371,381: doped region;
151,161: grid;
180,180 ': arresting element;
190,190 ': transistor;
101: contact mat;
131～134,141: field oxide;
200: substrate;
211,212,221,222,311,321: trap;
240,250,260,340,360: metal level;
241,251,261,341,361,362: connector.
Embodiment
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below:
Figure 1A is that one of ESD protector of the present invention may embodiment.As shown in the figure, ESD protector 100 comprises, substrate (not shown), doped region 111,112,121, grid 151 and 161.In the present embodiment, doped region 111 and 121 is isolated mutually. Grid 151 and 161 is isolated mutually.In another possibility embodiment, doped region 111 and 121 is to be respectively formed among two traps, and wherein this two trap is isolated mutually.
Under protection mode (esd event generation), transistor 190 is a disabled state, and arresting element 180 is an enabled state, in order to discharge the caused ESD electric current of esd event.In the present embodiment, because doped region 111 and 121 is isolated from each other, therefore, under normal mode (esd event does not take place), during transistor 190 runnings, the electric current that it produced can not impact arresting element 180.
In this example, when esd event did not take place, arresting element 180 was a disabled state, and transistor 190 is an enabled state.In a possibility embodiment, transistor 190 can be one and opens beginning (startup) element, in order to provide operating voltage to interlock circuit.
In the present embodiment, ESD protector 100 also comprises doped region 171, in order to isolate doped region 111 and 121.In another may embodiment, but the 171 also isolated gates 151 and 161 that mix.In other embodiments, ESD protector 100 also comprises contact mat 101.Contact mat 101 is formed on the doped region 111.
In addition, doped region 111 and 121 forms a loop configuration, and around contact mat 101. Grid 151 and 161 forms a loop configuration, around doped region 111 and 121.Similarly, doped region 112 forms a loop configuration, around grid 151 and 161.
Figure 1B is another possibility embodiment of ESD protector of the present invention.Figure 1B is similar in appearance to Figure 1A, and difference is that the ESD protector 100 ' of Figure 1B has field oxide 131～134,141 and doped region 172.Doped region 172 has first conductivity, can be used as the base stage (bulk) of transistor 190 ' and arresting element 180 '.
In the present embodiment, the width W 1 of field oxide 131 equals the width W 2 of field oxide 141.Therefore, under protection mode, arresting element 180 ' can be enabled before transistor 190 ' is enabled ahead of time, so but instant-free ESD electric current.In other possibility embodiment, the width W 1 of field oxide 131 is greater than the width W 2 of field oxide 141.
Fig. 2 is the A-A of Figure 1B " section (being transistor 190 ') schematic diagram.As shown in the figure, doped region 111,112 and 172 all is formed among the substrate 200.Grid 151 is formed on the substrate 200.One may embodiment in, substrate 200 is the P type with the conductivity of doped region 172, doped region 111 and 112 conductivity are the N type.Therefore, transistor 190 ' is a N type LDMOS FET.
As shown in the figure, field oxide 131 is arranged between doped region 111 and the grid 151.In addition, doped region 111 is formed among the trap 211 with field oxide 131.In the present embodiment, trap 211 is a deep N-well (Deep-Nwell).The doping content of doped region 111 is higher than trap 211.
In the present embodiment, metal level 240 is electrically connected doped region 112 by connector (plug) 241.Metal level 250 is electrically connected doped region 172 by connector 251.Metal level 260 is electrically connected doped region 111 by connector 261.In a possibility embodiment, metal level 260 is electrically connected contact mats (shown in Figure 1A or Figure 1B) 101.
Fig. 3 A is the B-B of Figure 1B " profile (being arresting element 180 ').As shown in the figure, doped region 121,112 and 172 all is formed among the substrate 200.Grid 161 is formed on the substrate 200.One may embodiment in, substrate 200, doped region 121 and 172 conductivity are the P type, the conductivity of doped region 112 is the N type. Doped region 121 and 172 doping content are higher than substrate 200.
In the present embodiment, arresting element 180 ' is an insulated gate bipolar transistor (IGBT).Doped region 121 is as the drain electrode of IGBT.Grid 161 is as the grid of IGBT.Doped region 112 is as the source electrode of IGBT.Doped region 172 is as the base stage of IGBT.
As shown in the figure, field oxide 141 is arranged between doped region 121 and the grid 161.Moreover doped region 121 is formed among the trap 311 with field oxide 141.In the present embodiment, trap 311 is a deep N-well.Trap 311 is isolated with trap 211 (as shown in Figure 2), and the width W 2 of field oxide 141 can be less than or equal to the width W 1 of field oxide 131.One may embodiment in, please in conjunction with consulting Figure 1A, Figure 1B, Fig. 2 and Fig. 3 A, doped region 171 isolation wells 211 and 311, wherein the doping content of doped region 121 is higher than trap 311.
In the present embodiment, metal level 340 is electrically connected doped region 112 and grid 161 by connector 341 and 342.Metal level 360 is electrically connected doped region 121 by connector 361.In a possibility embodiment, metal level 360 also is electrically connected contact mat (shown in Figure 1A or Figure 1B) 101.By the width W 3 between control connector 361 and the field oxide 141, the just trigger voltage of may command arresting element 180 '.Therefore, under protection mode (esd event generation), arresting element 180 ' can be triggered than transistor 190 ' is Zao, in order to instant-free ESD electric current.
Fig. 3 B is the circuit diagram of ESD protector of the present invention.As shown in the figure, ESD protector 100 ' comprises arresting element 180 ' and transistor 190 '.In the present embodiment, arresting element 180 ' is the IGBT of N type, and transistor 190 ' is the LDMOS FET of N type.
The base stage of transistor 190 ' (Bulk) couples the base stage of arresting element 180 '.The drain electrode of transistor 190 ' (drain) couples the drain electrode of arresting element 180 '.In a possibility embodiment, the drain electrode of arresting element 180 ' is coupled to a contact mat (pad).The source electrode of transistor 190 ' (Source) couples the source electrode and the grid of arresting element 180 '.In a possibility embodiment, the source electrode of arresting element 180 ' is a ground connection position (grounding).Therefore, when esd event occurred in contact mat, arresting element 180 ' just can be released into ground with the ESD electric current.
Fig. 4 is another possibility embodiment of arresting element 180 '.Fig. 4 is similar in appearance to Fig. 3 A, and difference is that the doped region 121 of Fig. 4 has doped region 371 and 381.The conductivity of doped region 371 is the P type, and the conductivity of doped region 381 is the N type.The doping content of doped region 371 is higher than substrate 200.The doping content of doped region 381 is higher than trap 311.
In the present embodiment, arresting element 180 ' is a thyristor (Silicon Controlled Rectifier; Hereinafter to be referred as SCR).Metal level 360 is electrically connected doped region 371 and 381, as the drain electrode of SCR by connector 361 and 362.By the width W 4 between control connector 362 and the field oxide 141, the just trigger voltage of may command SCR.Grid 161 is electrically connected doped region 112, in order to the grid as SCR by metal level 340.Doped region 172 is as the base stage of SCR.
Because doped region 371 and 381 is by doped region 171, isolated with doped region 111, therefore, under normal mode (esd event does not take place), the electric current of transistor 190 ' can not impact arresting element 180 '.In addition, by circulus, can make the ESD protector bear high pressure.
Moreover, by the conductivity in controlled doping district 121, just can produce required arresting element.For example, when the conductivity of doped region 121 was P type (shown in Fig. 3 B), then arresting element was IGBT.When the conductivity of doped region 121 is P type and N type when (as shown in Figure 4), then arresting element is SCR.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention attached claims scope before looking defines and is as the criterion.
Claims (10)
1. an electrostatic discharge protective device is characterized in that, described electrostatic discharge protective device comprises:
One substrate has one first conductivity;
One first doped region has one second conductivity, and is formed among the described substrate;
One first grid is formed on the described substrate;
One second doped region has described second conductivity, and is formed among the described substrate, and wherein said first, second doped region and described first grid constitute a transistor;
One second grid is formed on the described substrate, and is isolated from each other with described first grid; And
One the 3rd doped region has described first conductivity, is formed among the described substrate, and isolates mutually with described second doped region, and wherein said the first, the 3rd doped region and described second grid constitute an arresting element.
2. electrostatic discharge protective device as claimed in claim 1, it is characterized in that, described electrostatic discharge protective device also comprises one the 4th doped region, it has described first conductivity, and be formed among the described substrate, in order to isolate described second and third doped region, described the 4th doped region is also isolated described first and second grid, described first conductivity is the P type, and described second conductivity is the N type.
3. electrostatic discharge protective device as claimed in claim 1, it is characterized in that, described transistor is a transverse diffusion metal oxide semiconductor field effect transistor, described arresting element is an insulated gate bipolar transistor, wherein said first doped region is as described transistorized source electrode, described second doped region is as described transistor drain, and described first doped region is as the source electrode of described arresting element, and described the 3rd doped region is as the drain electrode of described arresting element.
4. electrostatic discharge protective device as claimed in claim 1 is characterized in that described electrostatic discharge protective device also comprises a metal level, is electrically connected described second grid and described first doped region.
5. electrostatic discharge protective device as claimed in claim 1 is characterized in that described electrostatic discharge protective device also comprises a contact mat, is formed on described second doped region.
6. electrostatic discharge protective device as claimed in claim 1 is characterized in that, described electrostatic discharge protective device also comprises:
One first field oxide is formed between described first grid and described second doped region; And
One second field oxide is formed between described second grid and described the 3rd doped region, and the width of wherein said second field oxide is less than or equal to the width of described first field oxide, and described first and second field oxide is isolated from each other.
7. an electrostatic discharge protective device is characterized in that, described electrostatic discharge protective device comprises:
One substrate has one first conductivity;
One first doped region has one second conductivity, and is formed among the described substrate;
One first grid is formed on the described substrate;
One second doped region has described second conductivity, and is formed among the described substrate, and wherein said first, second doped region and described first grid constitute a transistor;
One the 3rd doped region has described first conductivity, is formed among the described substrate, and isolates mutually with described second doped region; And
One the 4th doped region has described second conductivity, is formed among the described substrate, and isolates mutually with described second doped region, and wherein said the first, the 3rd, the 4th doped region and described second grid constitute an arresting element.
8. electrostatic discharge protective device as claimed in claim 7 is characterized in that, described electrostatic discharge protective device also comprises:
One the 5th doped region has described first conductivity, and is formed among the described substrate, in order to isolating described second and third doped region, and isolates the described second and the 4th doped region; And
One metal level is electrically connected the described the 3rd and the 4th doped region, and wherein said first conductivity is the P type, and described second conductivity is the N type.
9. electrostatic discharge protective device as claimed in claim 7, it is characterized in that, described transistor is a transverse diffusion metal oxide semiconductor field effect transistor, described arresting element is a thyristor, wherein said first doped region is as described transistorized source electrode, described second doped region is as described transistor drain, and described first doped region is as the source electrode of described arresting element, and the described the 3rd and the 4th doped region is as the drain electrode of described arresting element.
10. electrostatic discharge protective device as claimed in claim 7 is characterized in that, described electrostatic discharge protective device also comprises:
One metal level is electrically connected described second grid and described first doped region;
One contact mat is formed on described second doped region;
One first field oxide is formed between described first grid and described second doped region; And
One second field oxide is formed between described second grid and described the 4th doped region, and the width of wherein said second field oxide is less than or equal to the width of described first field oxide, and described first and second field oxide is isolated from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101391961A CN101887894B (en) | 2009-05-13 | 2009-05-13 | Static discharge protective device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101391961A CN101887894B (en) | 2009-05-13 | 2009-05-13 | Static discharge protective device |
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| Publication Number | Publication Date |
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| CN101887894A true CN101887894A (en) | 2010-11-17 |
| CN101887894B CN101887894B (en) | 2012-05-23 |
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| CN2009101391961A Active CN101887894B (en) | 2009-05-13 | 2009-05-13 | Static discharge protective device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113471190A (en) * | 2020-03-31 | 2021-10-01 | 新唐科技股份有限公司 | Semiconductor device and semiconductor structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7420250B2 (en) * | 2004-08-30 | 2008-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection device having light doped regions |
| US7217984B2 (en) * | 2005-06-17 | 2007-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Divided drain implant for improved CMOS ESD performance |
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2009
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113471190A (en) * | 2020-03-31 | 2021-10-01 | 新唐科技股份有限公司 | Semiconductor device and semiconductor structure |
| CN113471190B (en) * | 2020-03-31 | 2023-09-29 | 新唐科技股份有限公司 | Semiconductor device and semiconductor structure |
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| CN101887894B (en) | 2012-05-23 |
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