CN100364093C

CN100364093C - High-voltage electrostatic discharge protection device with gap structure

Info

Publication number: CN100364093C
Application number: CNB2004100311100A
Authority: CN
Inventors: 林耿立; 周业宁; 柯明道
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2004-04-06
Filing date: 2004-04-06
Publication date: 2008-01-23
Anticipated expiration: 2024-04-06
Also published as: CN1681122A

Abstract

A high voltage electrostatic discharge protection device with a gap structure is applied to a laterally diffused metal oxide semiconductor field effect transistor (LDMOS). The present invention utilizes the existing LDMOS structure and additionally adds a gap structure to separate the diffusion region from the field oxide region. When a parasitic silicon controlled rectifier of the LDMOS is not conducted, the ESD current is dispersed in other discharge paths so as to prevent the ESD current from being excessively concentrated in a certain discharge path and further causing the damage of an element.

Description

High-pressure electrostatic discharge protector with interstitial structure

Technical field

The invention relates to a kind of Electrostatic Discharge protective device, particularly relevant for a kind of electrostatic discharge protective equipment that between field oxide region and diffusion region, adds an interstitial structure, in order to the damage of avoiding field oxide region to be caused because of ESD electric current bump.

Background technology

Because of the infringement of element that static discharge caused has become one of topmost reliability issues concerning integrated circuit (IC) products.Especially constantly be contracted to the degree of deep-sub-micrometer along with size, the grid oxic horizon of metal-oxide-semiconductor (MOS) is also more and more thinner, and integrated circuit is easier to wreck because of the static discharge phenomenon.In the general industrial standard, the output and input pins of integrated circuit (IC) products (I/O pin) is essential can be by Human Body Model's electrostatic discharge testing more than 2000 volts and the mechanical mode electrostatic discharge testing more than 200 volts.Therefore, in integrated circuit (IC) products, protecting component for electrostatic discharge must be arranged on all and export near the weld pad (pad), is not subjected to the infringement of static discharge current to protect inner core circuit (corecircuit).

Fig. 1 is United States Patent (USP) numbering 6,459,127 shown ESD protective elements, simultaneously also be a lateral diffusion metal-oxide half-court effect transistor (laterally diffused metal oxidesemiconductor field effect transistor, LDMOS).As shown in the figure, this MOS is NMOS, and the grid 110 of NMOS is located in the P type substrate 100, and source electrode is constituted with N+ diffusion region 112, and drain electrode is constituted with N type well region 102 on the entity, with N+ diffusion region 106 as the electrode tie point.Grid 110 can be connected to earth connection VSS or be connected to prime driver (pre-driver) in order to the electric connection of control N+ diffusion region 112 with N type well region 102, decides on circuit requirement.

P type substrate 100 sees through P+ diffusion region 116 and is coupled to earth connection VSS.N+ diffusion region 112 also is coupled to earth connection VSS.Drain electrode sees through N+ diffusion region 106 and is connected to bond pad pad.P+ diffusion region 104, N type well region 102, P type substrate 100 and N+ diffusion region 112 constitute the SCR of a parasitism.

When a pair of earth connection VSS esd event that is positive voltage betided bond pad pad, after SCR triggered, electric current was begun by bond pad pad, through P+ diffusion region 104, N type well region 102, P type substrate 100 and N+ diffusion region 112, discharged to earth connection VSS.

Yet, when esd event betides bond pad pad and ESD voltage as yet not during conducting SCR, the ESD electric current is shown in discharge path A, and pad begins by bond pad, through N+ diffusion region 106, N type well region 102, P type substrate 100 and N+ diffusion region 112, discharge to earth connection VSS.

Because the doping content of N+ diffusion region 106 is higher, so impedance is lower; And the doping content of N type well region 102 is lower, so impedance is higher.The discharge path that most ESD electric current can see through the impedance minimum discharges.Discharge path A is N+ diffusion region 106 discharge path to impedance minimum between the N+ diffusion region 112, so as SCR not during conducting, most ESD electric current will discharge to earth connection VSS along the discharge path A of impedance minimum.

Shown in discharge path A, the ESD electric current turns to after bumping against field oxide region 108 again, because the ESD electric current has sizable energy, so will produce high heat in the turning point of field oxide region 108, causes the damage of field oxide region 108 and discharge path A.

Summary of the invention

Main purpose of the present invention is to provide a kind of electrostatic discharge protective equipment, as yet not during conducting, too concentrates on a certain discharge path, and then causes component wear at SCR in order to avoid the ESD electric current.

In order to achieve the above object; the present invention proposes a kind of electrostatic discharge protective equipment, comprising: one first conductivity type substrate, a field-effect transistor (field effect transistor), one the 3rd conductivity type, first diffusion region, a field oxide region and a gap.

This field-effect transistor comprises: one second conductivity type well region, one second conductivity type, first diffusion region and a grid.This second conductivity type well region and second conductivity type, first diffusion region are formed in the substrate.This grid, in order to control the electric connection of second conductivity type, first diffusion region and well region, wherein this grid is in this suprabasil view field of first conductivity type, this second conductivity type well region of lap.

The 3rd conductivity type first diffusion region, field oxide region and gap are formed in the well region, and wherein, this field oxide region is between this grid and the 3rd conductivity type first diffusion region, and this gap is between field oxide region and the 3rd conductivity type first diffusion region.

First conductivity type can be P type or N type, and second conductivity type can be N type or P type, and the 3rd conductivity type can be P type or N type.

Owing to have a gap between field oxide region of the present invention and the N+ diffusion region, when esd event takes place, and thyristor is not under the situation of conducting, by structure of the present invention, make the ESD electric current no longer only concentrate on a certain discharge path, in order to avoiding the damage of discharge path, and then cause the damage of inner member.

Description of drawings

Fig. 1 is the generalized section of known esd protection device;

Fig. 2 is the profile of a horizontal proliferation NMOS of esd protection device of the present invention;

Fig. 3 is the second embodiment profile of a horizontal proliferation NMOS of esd protection device of the present invention;

Fig. 4 is the 3rd embodiment profile of a horizontal proliferation NMOS of esd protection device of the present invention;

Fig. 5 is the profile of a transverse diffusion p MOS of esd protection device of the present invention.

Symbol description:

100,200,500:P type substrate

102,202,503:N type well region

104,116,204,216:P+ diffusion region

106,112,206,212:N+ diffusion region

108,114,208,214: field oxide region

110,210,220: grid

218,222: nominal grid

The 501:N+ buried regions

502:P type well region

Pad: bond pad

Gap: gap

Embodiment

Fig. 2 shows the profile of a horizontal proliferation NMOS of esd protection device of the present invention.As shown in the figure, the grid 210 of this NMOS is located in the P type substrate 200, and source electrode is constituted with N+ diffusion region 212, and drain electrode is constituted with N type well region 202 on the entity, still by N+ diffusion region 206 as the electrode tie point.Grid 210 can be connected to earth connection VSS or be connected to prime driver (pre-driver) in order to the electric connection of control N+ diffusion region 212 with N type well region 202, decides on circuit requirement.

P type substrate 200 sees through P+ diffusion region 216 and is coupled to earth connection VSS.N+ diffusion region 212 also is coupled to earth connection VSS.Drain electrode sees through N+ diffusion region 206 and is connected to bond pad pad.

Field oxide region 214 has been separated N+ diffusion region 212 and P+ diffusion region 216.Field oxide region 208 is located between N+ diffusion region 206 and the grid 210, utilizes thick oxide layer to completely cut off grid 210 and N type well region 202.If there is not field oxide region 208, gate oxide under the grid 210 may be because when normal running, and cross-pressure is excessive and collapse.Field oxide region can by STI or LOCOS wherein a kind of technology formed.Gap gap is located between field oxide region 208 and the N+ diffusion region 206.P+ diffusion region 204 is located among the N type well region 202, is coupled to bond pad pad.Wherein, P+ diffusion region 204 can be located between gap gap and the N+ diffusion region 206; Or N+ diffusion region 206 is located between gap gap and the P+ diffusion region 204.Because the existence of P+ diffusion region 204 so formed the SCR of a parasitism, is made of P+ diffusion region 204, N type well region 202, P type substrate 200 and N+ diffusion region 212.

When a pair of earth connection is that the esd event of negative voltage is when betiding bond pad pad, because N type well region 202 sees through N+ diffusion region 206 and is connected to bond pad pad, P type substrate 200 sees through P+ diffusion region 216 and is coupled to earth connection, therefore P type substrate 200 connects forward conducting of face with the PN of N type well region 202, make earth connection and bond pad pad short circuit, and discharge the ESD electric current.

When a pair of earth connection VSS esd event that is positive voltage betides bond pad pad, after the SCR of parasitism triggers, electric current is begun by bond pad pad, through P+ diffusion region 204, N type well region 202, P type substrate 200 and N+ diffusion region 212, discharges to earth connection VSS.

Yet, when esd event betides bond pad pad and ESD voltage as yet not during conducting SCR, the ESD electric current is shown in discharge path B, C, and pad begins by bond pad, through N+ diffusion region 206, N type well region 202, P type substrate 200 and N+ diffusion region 212, discharge to earth connection VSS.

Owing to have a gap gap between field oxide region 208 and the N+ diffusion region 206, make the ESD electric current can directly not clash into field oxide region 208.Compare with known technology, if under all the same condition of the size of All Ranges, because the field oxide region 108 of Fig. 1 contact N+ diffusion regions 106 make ESD electric current major part concentrate on the discharge path A of impedance minimum, easily cause field oxide region 208 to be subjected to ESD electric current bump and damage.Use the horizontal proliferation NMOS of esd protection device of the present invention, make the ESD electric current no longer concentrate on a certain discharge path, and can see through other discharge path,, discharge to earth connection VSS as discharge path B, C.

Wherein, the formation of gap gap is defined by mask (mask) pattern, with forming the mask pattern of N+ diffusion region 206, behind distance field zoneofoxidation 208 1 specific ranges, forms N+ diffusion region 206 again.If at gap gap place's doping P+, then make between N+ diffusion region 206 and the field oxide region 208 and produce high resistance regions, directly clash into field oxide region 208 in order to avoid the ESD electric current.

Fig. 3 shows the second embodiment profile of electrostatic discharge protective equipment of the present invention.As shown in the figure, use identical symbol with Fig. 2 similar elements; See through mask pattern and form a nominal grid (dummy gate) 218 between N+ diffusion region 206 and field oxide region 208, nominal grid 218 is not received any DC power supply, is (floating) grid of floating.Grid 220 is between field oxide region 208 and N+ diffusion region 212, and grid 220 parts extend on the field oxide region 208.

Fig. 4 shows the 3rd embodiment profile of electrostatic discharge protective equipment of the present invention.Fig. 4 uses identical symbol with Fig. 3 similar elements.As shown in the figure, nominal grid 222 parts extend on the field oxide region 208.

Fig. 5 is utilization PMOS profile of the present invention, forms a n type buried layer 501 in P type substrate 500.Wherein, n type buried layer 501 is the N type substrate of PMOS with N type well region 503.Compare with the N type element of Fig. 3, except the exchanging of conductivity N and P, VSS power line (low voltage power line) also changes VDD power line (high voltage power line) into.

In addition, Fig. 3 and Fig. 5 are the suprabasil high-pressure N-shaped and P type element of P type, form high-pressure N-shaped and P type element, also applicable structure of the present invention in the substrate of N type.Because the conversion between P type element and the N type element by the people in the industry is familiar with, therefore, repeats no more.

Claims

1. A high-voltage electrostatic discharge protection device with gap structure, characterized in that said electrostatic discharge protection device comprises:

a substrate of the first conductivity type;

a second conductivity type well region formed in the substrate;

a first diffusion region of the second conductivity type formed in the substrate;

a gate, used to control the electrical connection between the first diffusion region of the second conductivity type and the well region, the gate, the first diffusion region of the second conductivity type and the well region constitute a field effect transistor, wherein the The projection area of the gate on the substrate of the first conductivity type overlaps part of the well region of the second conductivity type;

a first diffusion region of the third conductivity type formed in the well region;

a field oxidation region formed in the well region between the gate and the third conductivity type first diffusion region; and

A gap is formed in the well region and is located between the field oxide region and the first diffusion region of the third conductivity type.

2 . The ESD protection device according to claim 1 , wherein the ESD protection device further comprises a first diffusion region of the first conductivity type formed in the substrate as an electrical contact point of the substrate. 3 .

3. The electrostatic discharge protection device according to claim 2, wherein the first and third conductivity types are P-type, and the second conductivity type is N-type.

4. The electrostatic discharge protection device according to claim 2, wherein the first conductivity type is P-type, and the second and third conductivity types are N-type.

5 . The electrostatic discharge protection device according to claim 4 , wherein the first diffusion region of the second conductivity type and the first diffusion region of the first conductivity type are connected to a first power line under normal operation.

6. The electrostatic discharge protection device according to claim 2, wherein the first and third conductivity types are N-type, and the second conductivity type is P-type.

7. The electrostatic discharge protection device according to claim 2, wherein the first conductivity type is N-type, and the second and third conductivity types are P-type.

8 . The electrostatic discharge protection device according to claim 7 , wherein the first diffusion region of the second conductivity type and the first diffusion region of the first conductivity type are connected to a second power line under normal operation.

9. The electrostatic discharge protection device according to claim 1, wherein the gap is defined by a mask.

10 . The electrostatic discharge protection device according to claim 1 , further comprising a dummy gate formed between the first diffusion region of the third conductivity type and the field oxidation region. 11 .