CN100364093C - High-voltage electrostatic discharging protector with gap structure - Google Patents
High-voltage electrostatic discharging protector with gap structure Download PDFInfo
- Publication number
- CN100364093C CN100364093C CNB2004100311100A CN200410031110A CN100364093C CN 100364093 C CN100364093 C CN 100364093C CN B2004100311100 A CNB2004100311100 A CN B2004100311100A CN 200410031110 A CN200410031110 A CN 200410031110A CN 100364093 C CN100364093 C CN 100364093C
- Authority
- CN
- China
- Prior art keywords
- conductivity type
- diffusion region
- region
- type
- electrostatic discharge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001012 protector Effects 0.000 title claims abstract description 4
- 238000007599 discharging Methods 0.000 title 1
- 238000009792 diffusion process Methods 0.000 claims abstract description 73
- 230000005669 field effect Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 23
- 230000001681 protective effect Effects 0.000 claims description 18
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 230000035755 proliferation Effects 0.000 description 5
- 239000012141 concentrate Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000024241 parasitism Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to a high-voltage electrostatic discharge protector with a gap structure, which is used for lateral diffusion metal-oxide semi field effect transistors (LDMOS). The present invention utilizes the existing structure of an LDMOS and a gap structure to separate a diffusion region and a field oxide region. When a parasitic silicon controlled rectifier of the LDMOS is not turned on, electrostatic discharge (ESD) currents are dispersed to other discharge paths to avoid the phenomenon that because the ESD currents are concentrated in a discharge path, elements are damaged.
Description
Technical field
The invention relates to a kind of Electrostatic Discharge protective device, particularly relevant for a kind of electrostatic discharge protective equipment that between field oxide region and diffusion region, adds an interstitial structure, in order to the damage of avoiding field oxide region to be caused because of ESD electric current bump.
Background technology
Because of the infringement of element that static discharge caused has become one of topmost reliability issues concerning integrated circuit (IC) products.Especially constantly be contracted to the degree of deep-sub-micrometer along with size, the grid oxic horizon of metal-oxide-semiconductor (MOS) is also more and more thinner, and integrated circuit is easier to wreck because of the static discharge phenomenon.In the general industrial standard, the output and input pins of integrated circuit (IC) products (I/O pin) is essential can be by Human Body Model's electrostatic discharge testing more than 2000 volts and the mechanical mode electrostatic discharge testing more than 200 volts.Therefore, in integrated circuit (IC) products, protecting component for electrostatic discharge must be arranged on all and export near the weld pad (pad), is not subjected to the infringement of static discharge current to protect inner core circuit (corecircuit).
Fig. 1 is United States Patent (USP) numbering 6,459,127 shown ESD protective elements, simultaneously also be a lateral diffusion metal-oxide half-court effect transistor (laterally diffused metal oxidesemiconductor field effect transistor, LDMOS).As shown in the figure, this MOS is NMOS, and the grid 110 of NMOS is located in the P type substrate 100, and source electrode is constituted with N+ diffusion region 112, and drain electrode is constituted with N type well region 102 on the entity, with N+ diffusion region 106 as the electrode tie point.Grid 110 can be connected to earth connection VSS or be connected to prime driver (pre-driver) in order to the electric connection of control N+ diffusion region 112 with N type well region 102, decides on circuit requirement.
When a pair of earth connection VSS esd event that is positive voltage betided bond pad pad, after SCR triggered, electric current was begun by bond pad pad, through P+ diffusion region 104, N type well region 102, P type substrate 100 and N+ diffusion region 112, discharged to earth connection VSS.
Yet, when esd event betides bond pad pad and ESD voltage as yet not during conducting SCR, the ESD electric current is shown in discharge path A, and pad begins by bond pad, through N+ diffusion region 106, N type well region 102, P type substrate 100 and N+ diffusion region 112, discharge to earth connection VSS.
Because the doping content of N+ diffusion region 106 is higher, so impedance is lower; And the doping content of N type well region 102 is lower, so impedance is higher.The discharge path that most ESD electric current can see through the impedance minimum discharges.Discharge path A is N+ diffusion region 106 discharge path to impedance minimum between the N+ diffusion region 112, so as SCR not during conducting, most ESD electric current will discharge to earth connection VSS along the discharge path A of impedance minimum.
Shown in discharge path A, the ESD electric current turns to after bumping against field oxide region 108 again, because the ESD electric current has sizable energy, so will produce high heat in the turning point of field oxide region 108, causes the damage of field oxide region 108 and discharge path A.
Summary of the invention
Main purpose of the present invention is to provide a kind of electrostatic discharge protective equipment, as yet not during conducting, too concentrates on a certain discharge path, and then causes component wear at SCR in order to avoid the ESD electric current.
In order to achieve the above object; the present invention proposes a kind of electrostatic discharge protective equipment, comprising: one first conductivity type substrate, a field-effect transistor (field effect transistor), one the 3rd conductivity type, first diffusion region, a field oxide region and a gap.
This field-effect transistor comprises: one second conductivity type well region, one second conductivity type, first diffusion region and a grid.This second conductivity type well region and second conductivity type, first diffusion region are formed in the substrate.This grid, in order to control the electric connection of second conductivity type, first diffusion region and well region, wherein this grid is in this suprabasil view field of first conductivity type, this second conductivity type well region of lap.
The 3rd conductivity type first diffusion region, field oxide region and gap are formed in the well region, and wherein, this field oxide region is between this grid and the 3rd conductivity type first diffusion region, and this gap is between field oxide region and the 3rd conductivity type first diffusion region.
First conductivity type can be P type or N type, and second conductivity type can be N type or P type, and the 3rd conductivity type can be P type or N type.
Owing to have a gap between field oxide region of the present invention and the N+ diffusion region, when esd event takes place, and thyristor is not under the situation of conducting, by structure of the present invention, make the ESD electric current no longer only concentrate on a certain discharge path, in order to avoiding the damage of discharge path, and then cause the damage of inner member.
Description of drawings
Fig. 1 is the generalized section of known esd protection device;
Fig. 2 is the profile of a horizontal proliferation NMOS of esd protection device of the present invention;
Fig. 3 is the second embodiment profile of a horizontal proliferation NMOS of esd protection device of the present invention;
Fig. 4 is the 3rd embodiment profile of a horizontal proliferation NMOS of esd protection device of the present invention;
Fig. 5 is the profile of a transverse diffusion p MOS of esd protection device of the present invention.
Symbol description:
100,200,500:P type substrate
102,202,503:N type well region
104,116,204,216:P+ diffusion region
106,112,206,212:N+ diffusion region
108,114,208,214: field oxide region
110,210,220: grid
218,222: nominal grid
The 501:N+ buried regions
502:P type well region
Pad: bond pad
Gap: gap
Embodiment
Fig. 2 shows the profile of a horizontal proliferation NMOS of esd protection device of the present invention.As shown in the figure, the grid 210 of this NMOS is located in the P type substrate 200, and source electrode is constituted with N+ diffusion region 212, and drain electrode is constituted with N type well region 202 on the entity, still by N+ diffusion region 206 as the electrode tie point.Grid 210 can be connected to earth connection VSS or be connected to prime driver (pre-driver) in order to the electric connection of control N+ diffusion region 212 with N type well region 202, decides on circuit requirement.
When a pair of earth connection is that the esd event of negative voltage is when betiding bond pad pad, because N type well region 202 sees through N+ diffusion region 206 and is connected to bond pad pad, P type substrate 200 sees through P+ diffusion region 216 and is coupled to earth connection, therefore P type substrate 200 connects forward conducting of face with the PN of N type well region 202, make earth connection and bond pad pad short circuit, and discharge the ESD electric current.
When a pair of earth connection VSS esd event that is positive voltage betides bond pad pad, after the SCR of parasitism triggers, electric current is begun by bond pad pad, through P+ diffusion region 204, N type well region 202, P type substrate 200 and N+ diffusion region 212, discharges to earth connection VSS.
Yet, when esd event betides bond pad pad and ESD voltage as yet not during conducting SCR, the ESD electric current is shown in discharge path B, C, and pad begins by bond pad, through N+ diffusion region 206, N type well region 202, P type substrate 200 and N+ diffusion region 212, discharge to earth connection VSS.
Owing to have a gap gap between field oxide region 208 and the N+ diffusion region 206, make the ESD electric current can directly not clash into field oxide region 208.Compare with known technology, if under all the same condition of the size of All Ranges, because the field oxide region 108 of Fig. 1 contact N+ diffusion regions 106 make ESD electric current major part concentrate on the discharge path A of impedance minimum, easily cause field oxide region 208 to be subjected to ESD electric current bump and damage.Use the horizontal proliferation NMOS of esd protection device of the present invention, make the ESD electric current no longer concentrate on a certain discharge path, and can see through other discharge path,, discharge to earth connection VSS as discharge path B, C.
Wherein, the formation of gap gap is defined by mask (mask) pattern, with forming the mask pattern of N+ diffusion region 206, behind distance field zoneofoxidation 208 1 specific ranges, forms N+ diffusion region 206 again.If at gap gap place's doping P+, then make between N+ diffusion region 206 and the field oxide region 208 and produce high resistance regions, directly clash into field oxide region 208 in order to avoid the ESD electric current.
Fig. 3 shows the second embodiment profile of electrostatic discharge protective equipment of the present invention.As shown in the figure, use identical symbol with Fig. 2 similar elements; See through mask pattern and form a nominal grid (dummy gate) 218 between N+ diffusion region 206 and field oxide region 208, nominal grid 218 is not received any DC power supply, is (floating) grid of floating.Grid 220 is between field oxide region 208 and N+ diffusion region 212, and grid 220 parts extend on the field oxide region 208.
Fig. 4 shows the 3rd embodiment profile of electrostatic discharge protective equipment of the present invention.Fig. 4 uses identical symbol with Fig. 3 similar elements.As shown in the figure, nominal grid 222 parts extend on the field oxide region 208.
Fig. 5 is utilization PMOS profile of the present invention, forms a n type buried layer 501 in P type substrate 500.Wherein, n type buried layer 501 is the N type substrate of PMOS with N type well region 503.Compare with the N type element of Fig. 3, except the exchanging of conductivity N and P, VSS power line (low voltage power line) also changes VDD power line (high voltage power line) into.
In addition, Fig. 3 and Fig. 5 are the suprabasil high-pressure N-shaped and P type element of P type, form high-pressure N-shaped and P type element, also applicable structure of the present invention in the substrate of N type.Because the conversion between P type element and the N type element by the people in the industry is familiar with, therefore, repeats no more.
Claims (10)
1. high-pressure electrostatic discharge protector with interstitial structure is characterized in that described electrostatic discharge protective equipment comprises:
One first conductivity type substrate;
One second conductivity type well region is formed in this substrate;
One second conductivity type, first diffusion region is formed in this substrate;
One grid, in order to control the electric connection of this second conductivity type, first diffusion region and this well region, this grid, this second conductivity type, first diffusion region and this well region constitute a field-effect transistor, wherein this grid is in this suprabasil view field of first conductivity type, this second conductivity type well region of lap;
One the 3rd conductivity type, first diffusion region is formed in this well region;
One field oxide region is formed in this well region, between this grid and the 3rd conductivity type first diffusion region; And
One gap is formed in this well region, between this field oxide region and the 3rd conductivity type first diffusion region.
2. electrostatic discharge protective equipment according to claim 1 is characterized in that: this electrostatic discharge protective equipment includes one first conductivity type, first diffusion region in addition, is formed in this substrate, as the electrical pickoff of this substrate.
3. electrostatic discharge protective equipment according to claim 2 is characterized in that: this first, the 3rd conductivity type is the P type, and this second conductivity type is the N type.
4. electrostatic discharge protective equipment according to claim 2 is characterized in that: this first conductivity type is the P type, and this second, third conductivity type is the N type.
5. electrostatic discharge protective equipment according to claim 4 is characterized in that: this second conductivity type, first diffusion region and this first conductivity type, first diffusion region are to connect one first power line under normal operation.
6. electrostatic discharge protective equipment according to claim 2 is characterized in that: this first, the 3rd conductivity type is the N type, and this second conductivity type is the P type.
7. electrostatic discharge protective equipment according to claim 2 is characterized in that: this first conductivity type is the N type, and this second, third conductivity type is the P type.
8. electrostatic discharge protective equipment according to claim 7 is characterized in that: this second conductivity type, first diffusion region and this first conductivity type, first diffusion region are to connect a second source line under normal operation.
9. electrostatic discharge protective equipment according to claim 1 is characterized in that: this gap is defined by mask.
10. electrostatic discharge protective equipment according to claim 1 is characterized in that: more comprise a nominal grid, be formed between the 3rd conductivity type first diffusion region and this field oxide region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100311100A CN100364093C (en) | 2004-04-06 | 2004-04-06 | High-voltage electrostatic discharging protector with gap structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100311100A CN100364093C (en) | 2004-04-06 | 2004-04-06 | High-voltage electrostatic discharging protector with gap structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1681122A CN1681122A (en) | 2005-10-12 |
| CN100364093C true CN100364093C (en) | 2008-01-23 |
Family
ID=35067622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100311100A Expired - Lifetime CN100364093C (en) | 2004-04-06 | 2004-04-06 | High-voltage electrostatic discharging protector with gap structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100364093C (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101546769B (en) * | 2008-03-28 | 2010-12-22 | 盛群半导体股份有限公司 | Integrated circuit and electrostatic charge protection method thereof |
| WO2009134812A1 (en) * | 2008-04-28 | 2009-11-05 | Lakota Technologies, Inc. | Mosfet with integrated field effect rectifier |
| CN102034806B (en) * | 2009-09-24 | 2014-08-13 | 新唐科技股份有限公司 | Electrostatic-discharge protecting device |
| US8405941B2 (en) | 2009-11-30 | 2013-03-26 | Nuvoton Technology Corporation | ESD protection apparatus and ESD device therein |
| US8304831B2 (en) * | 2010-02-08 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus of forming a gate |
| CN102931234B (en) * | 2011-08-10 | 2016-01-20 | 无锡华润上华半导体有限公司 | LDMOS device and manufacture method thereof |
| CN103378087B (en) * | 2012-04-28 | 2016-02-24 | 无锡华润上华半导体有限公司 | Electrostatic discharge protection structure and manufacture method thereof |
| CN102832233B (en) * | 2012-08-30 | 2015-05-20 | 北京大学 | SCR (silicon controlled rectifier) type LDMOS ESD (lateral double diffusion metal-oxide-semiconductor device electrostatic discharge) device |
| CN103715233B (en) * | 2014-01-10 | 2016-08-03 | 江南大学 | A kind of ESD protective device of the LDMOS structure with high maintenance voltage |
| CN105810740B (en) * | 2016-04-19 | 2019-04-09 | 上海华虹宏力半导体制造有限公司 | High-voltage LDMOS device and process |
| CN105870188B (en) * | 2016-04-19 | 2019-04-09 | 上海华虹宏力半导体制造有限公司 | High-voltage LDMOS device and process |
| CN108807373B (en) * | 2018-06-25 | 2021-04-13 | 湖南大学 | Electrostatic protection device |
| CN111968970B (en) * | 2020-08-28 | 2022-04-08 | 电子科技大学 | ESD protection device |
| CN112736124B (en) * | 2020-12-28 | 2023-10-27 | 矽力杰半导体技术(杭州)有限公司 | ESD protection device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008508A (en) * | 1996-09-12 | 1999-12-28 | National Semiconductor Corporation | ESD Input protection using a floating gate neuron MOSFET as a tunable trigger element |
| US6465848B2 (en) * | 2000-10-27 | 2002-10-15 | Vanguard International Semiconductor Corporation | Low-voltage-triggered electrostatic discharge protection device and relevant circuitry |
| US20020187601A1 (en) * | 2001-02-20 | 2002-12-12 | Taiwan Semiconductor Manufacturing Company | Low capacitance ESD protection device |
| US20030213971A1 (en) * | 2001-08-29 | 2003-11-20 | Taiwan Semiconductor Manufacturing Company | Silicon controlled rectifier ESD structures with trench isolation |
-
2004
- 2004-04-06 CN CNB2004100311100A patent/CN100364093C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008508A (en) * | 1996-09-12 | 1999-12-28 | National Semiconductor Corporation | ESD Input protection using a floating gate neuron MOSFET as a tunable trigger element |
| US6465848B2 (en) * | 2000-10-27 | 2002-10-15 | Vanguard International Semiconductor Corporation | Low-voltage-triggered electrostatic discharge protection device and relevant circuitry |
| US20020187601A1 (en) * | 2001-02-20 | 2002-12-12 | Taiwan Semiconductor Manufacturing Company | Low capacitance ESD protection device |
| US20030213971A1 (en) * | 2001-08-29 | 2003-11-20 | Taiwan Semiconductor Manufacturing Company | Silicon controlled rectifier ESD structures with trench isolation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1681122A (en) | 2005-10-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6538266B2 (en) | Protection device with a silicon-controlled rectifier | |
| US6665160B2 (en) | Voltage control component for ESD protection and its relevant circuitry | |
| US5872379A (en) | Low voltage turn-on SCR for ESD protection | |
| US8570698B2 (en) | ESD protection for FinFETs | |
| KR101975608B1 (en) | Electrostatic discharge high voltage type transistor and electrostatic dscharge protection circuit thereof | |
| CN100364093C (en) | High-voltage electrostatic discharging protector with gap structure | |
| US7705404B2 (en) | Electrostatic discharge protection device and layout thereof | |
| JP2003179206A (en) | Semiconductor device with electrostatic discharge protective function | |
| US20050179087A1 (en) | LDMOS transistor with improved ESD protection | |
| JPH10504424A (en) | Electrostatic discharge protection circuit | |
| US7323752B2 (en) | ESD protection circuit with floating diffusion regions | |
| US11239229B2 (en) | Self-biased bidirectional ESD protection circuit | |
| CN100508322C (en) | Protection circuit for an integrated circuit device | |
| US20040207020A1 (en) | CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection | |
| US20040190209A1 (en) | Apparatus for providing ESD protection for MOS input devices having ultra-thin gate oxides | |
| US6455898B1 (en) | Electrostatic discharge input protection for reducing input resistance | |
| US8736022B2 (en) | Semiconductor device with a diode-type ESD protection circuit | |
| US20030043517A1 (en) | Electro-static discharge protecting circuit | |
| US7098522B2 (en) | High voltage device with ESD protection | |
| CN1322586C (en) | Electrostatic discharge protection device for high-voltage integrated circuit | |
| US8278715B2 (en) | Electrostatic discharge protection device | |
| TWI481009B (en) | Esd protection apparatus and esd device therein | |
| JP2008172216A (en) | Well potential triggered esd protection | |
| CN101887894B (en) | Static discharge protective device | |
| TW494564B (en) | Electrostatic discharge protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20080123 |