CN108807373B - Electrostatic protection device - Google Patents
Electrostatic protection device Download PDFInfo
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- CN108807373B CN108807373B CN201810661331.8A CN201810661331A CN108807373B CN 108807373 B CN108807373 B CN 108807373B CN 201810661331 A CN201810661331 A CN 201810661331A CN 108807373 B CN108807373 B CN 108807373B
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- 238000002347 injection Methods 0.000 claims abstract description 108
- 239000007924 injection Substances 0.000 claims abstract description 108
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002513 implantation Methods 0.000 claims description 21
- 239000007943 implant Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an electrostatic protection device, which comprises a substrate, wherein a deep N well is arranged on the substrate, a P well and an N well are arranged in the deep N well, a first P + injection region, a first N-base injection layer and a first N + injection region are arranged in the P well, and a second N-base injection layer, a second N + injection region and a second P + injection region are arranged in the N well; the first P + injection region and the first N + injection region are connected with the cathode; the second N + injection region and the second P + injection region are connected with the anode; a first thin gate oxide layer is arranged between the first P + injection region and the first N + injection region, a first polysilicon gate covers the first thin gate oxide layer, a second thin gate oxide layer is arranged between the second N + injection region and the second P + injection region, and a second polysilicon gate covers the second thin gate oxide layer; the second N-base injection layer is bridged between the P well and the N well, and the first N-base injection layer is positioned below the first N + injection region. The invention can solve the problems of high trigger voltage and weak total dose resistance.
Description
Technical Field
The invention relates to the technical field of integrated circuit electrostatic protection, in particular to an electrostatic protection device.
Background
LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices are widely used in power management chips, such as DC-DC converters, AC-DC converters, and the like. With the development of integrated circuits at high speed and high voltage, the weak electrostatic protection capability of the LDMOS device becomes a bottleneck limiting the development thereof. Therefore, how to improve the electrostatic discharge (ESD) capability of the LDMOS device becomes a hot point of research.
Referring to fig. 3 and 4, in the conventional LDMOS electrostatic protection device, a diode or a Silicon Controlled Rectifier (SCR) is usually introduced to enhance the electrostatic discharge capability, but both solutions have the disadvantages of high trigger voltage and weak total dose resistance, which limits the application range of the electrostatic protection device, especially cannot be applied in an aerospace high-voltage integrated circuit.
Disclosure of Invention
In view of the above, there is a need for an electrostatic protection device that solves the problems of high trigger voltage and poor total dose resistance.
An electrostatic protection device comprises a substrate, wherein a deep N well is arranged on the substrate, a P well and an N well are arranged in the deep N well, a first P + injection region, a first N-base injection layer and a first N + injection region are arranged in the P well, and a second N-base injection layer, a second N + injection region and a second P + injection region are arranged in the N well; the first P + injection region and the first N + injection region are connected with a cathode; the second N + injection region and the second P + injection region are connected with an anode; a first thin gate oxide layer is arranged between the first P + injection region and the first N + injection region, a first polysilicon gate covers the first thin gate oxide layer, a second thin gate oxide layer is arranged between the second N + injection region and the second P + injection region, and a second polysilicon gate covers the second thin gate oxide layer; the second N-base injection layer is bridged between the P well and the N well, and the first N-base injection layer is positioned below the first N + injection region.
According to the electrostatic protection device, the first P + injection region and the first N + injection region and the second P + injection region are isolated by using the polysilicon gate structure to replace a thick field oxide layer, the total dose resistance of the device can be effectively improved, the second N-base injection layer is bridged between the P well and the N well, the effects of reducing trigger voltage and improving the total dose resistance are achieved, in addition, the first N-base injection layer is positioned below the first N + injection region, the amplification factor of an NPN (negative-positive-negative) tube near a cathode can be enlarged, the holding voltage can be improved, and finally the electrostatic protection device has the advantages of low trigger voltage, high discharge efficiency and strong total dose resistance, and can be applied to electrostatic protection of a high-voltage integrated circuit for spaceflight.
In addition, the electrostatic protection device provided by the invention can also have the following additional technical characteristics:
furthermore, a third thin gate oxide layer and a field oxide region are sequentially arranged between the first N + injection region and the second N + injection region, a third polysilicon gate covers the third thin gate oxide layer, and the third polysilicon gate is connected with the cathode.
Further, the second N-base injection layer surrounds the field oxide region.
Further, the second P + injection region, the N-well, and the P-well form a PNP structure, and the first N + injection region, the P-well, and the second N-base injection layer form an NPN structure.
Further, the P-well and the N-well are sequentially arranged in the deep N-well from left to right, the first P + injection region, the first N-base injection layer and the first N + injection region are sequentially arranged in the P-well from left to right, and the second N-base injection layer, the second N + injection region and the second P + injection region are sequentially arranged in the N-well from left to right.
Furthermore, from the anode to the cathode, the electrostatic protection device has three electrostatic discharge paths, and the first path is the second P + injection region, the N well, the P well, and the first P + injection region; the second path is the second N + injection region, the N well, the P well and the first N + injection region; the third path is the second N + injection region, the second N-base injection layer, the P-well, and the first N + injection region.
Further, the substrate is a P-type silicon substrate.
Drawings
Fig. 1 is a schematic structural diagram of an electrostatic protection device according to an embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram of FIG. 1;
FIG. 3 is a schematic structural diagram of an LDMOS ESD device in the prior art;
FIG. 4 is a schematic structural diagram of an electrostatic protection device with an LDMOS-SCR structure in the prior art.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. Several embodiments of the invention are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "up," "down," and the like are for illustrative purposes only and do not indicate or imply that the referenced device or element must be in a particular orientation, constructed or operated in a particular manner, and is not to be construed as limiting the present invention.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1 and fig. 2, an electrostatic protection device according to an embodiment of the invention includes a substrate 100, and in this embodiment, the substrate 100 is a P-type silicon substrate.
The substrate 100 is provided with a deep N-well 200, and a P-well 300 and an N-well 301 are provided in the deep N-well 200. Specifically, in the present embodiment, the P-well 300 and the N-well 301 are sequentially disposed from left to right in the deep N-well 200.
A first P + injection region 401, a first N-base injection layer 402 and a first N + injection region 403 are disposed in the P-well 300. Specifically, in the present embodiment, the first P + implantation region 401, the first N-base implantation layer 402 and the first N + implantation region 403 are sequentially disposed from left to right in the P well 300.
A second N-base implantation layer 404, a second N + implantation region 405 and a second P + implantation region 406 are disposed in the N well 301. Specifically, in this embodiment, the second N-base implantation layer 404, the second N + implantation region 405, and the second P + implantation region 406 are sequentially disposed from left to right in the N well 301.
The first P + injection region 401 and the first N + injection region 403 are connected to a cathode; the second N + implantation region 405 and the second P + implantation region 406 are connected to the anode.
Specifically, the second N-base injection layer 404 is bridged between the P-well 300 and the N-well 301, and the first N-base injection layer 402 is located below the first N + injection region 403.
A first thin gate oxide layer 501 is arranged between the first P + injection region 401 and the first N + injection region 403, a first polysilicon gate 502 covers the first thin gate oxide layer 501, a second thin gate oxide layer 503 is arranged between the second N + injection region 405 and the second P + injection region 406, and a second polysilicon gate 504 covers the second thin gate oxide layer 503.
The second P + injection region 406, the N well 301, and the P well 300 form a PNP structure, i.e., a transistor Qp; the first N + injection region 403, the P well 300, and the second N-base injection layer 404 form an NPN structure, i.e., a transistor Qn.
Where Rpw is the resistance of P-well 300 and Rnw is the resistance of N-well 301.
In this embodiment, a third thin gate oxide layer 505 and a field oxide region 506 are sequentially disposed between the first N + injection region 403 and the second N + injection region 405, a third polysilicon gate 507 covers the third thin gate oxide layer 505, and the third polysilicon gate 507 is connected to a cathode. The second N-base implant layer 404 surrounds the field oxide region 506.
From the anode to the cathode, the electrostatic protection device has three electrostatic discharge paths, the first path is the second P + injection region 406, the N well 301, the P well 300, and the first P + injection region 401; the second path is the second N + implantation region 405, the N-well 301, the P-well 300, and the first N + implantation region 403; the third path is the second N + injection region 405, the second N-base injection layer 404, the P-well 300, and the first N + injection region 403, so that the esd protection device has a strong electrostatic discharge capability and a high discharge efficiency.
According to the electrostatic protection device provided by the embodiment, a polysilicon gate structure is used for replacing a thick field oxide layer for isolation between the first P + injection region and the first N + injection region and between the second N + injection region and the second P + injection region, so that the total dose resistance of the device can be effectively improved, the second N-base injection layer is bridged between the P well and the N well, the trigger voltage is reduced, and the total dose resistance is improved.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. An electrostatic protection device is characterized by comprising a substrate, wherein a deep N well is arranged on the substrate, a P well and an N well are arranged in the deep N well, a first P + injection region, a first N-base injection layer and a first N + injection region are arranged in the P well, and a second N-base injection layer, a second N + injection region and a second P + injection region are arranged in the N well; the first P + injection region and the first N + injection region are connected with a cathode; the second N + injection region and the second P + injection region are connected with an anode; a first thin gate oxide layer is arranged between the first P + injection region and the first N + injection region, a first polysilicon gate covers the first thin gate oxide layer, a second thin gate oxide layer is arranged between the second N + injection region and the second P + injection region, and a second polysilicon gate covers the second thin gate oxide layer; the second N-base injection layer is bridged between the P well and the N well, and the first N-base injection layer is positioned below the first N + injection region.
2. The electrostatic protection device according to claim 1, wherein a third thin gate oxide layer and a field oxide region are sequentially disposed between the first N + implantation region and the second N + implantation region, a third polysilicon gate is covered on the third thin gate oxide layer, and the third polysilicon gate is connected to the cathode.
3. The electrostatic protection device of claim 2, wherein the second N-base implant layer surrounds the field oxide region.
4. The ESD device of claim 1 wherein the second P + implant region, the N-well, and the P-well form a PNP structure, and the first N + implant region, the P-well, and the second N-base implant layer form an NPN structure.
5. The ESD protection device according to claim 1, wherein the P-well and the N-well are sequentially disposed in the deep N-well from left to right, the first P + implantation region, the first N-base implantation layer, and the first N + implantation region are sequentially disposed in the P-well from left to right, and the second N-base implantation layer, the second N + implantation region, and the second P + implantation region are sequentially disposed in the N-well from left to right.
6. The ESD protection device of claim 1, wherein the ESD protection device has three ESD paths from the anode to the cathode, and the first ESD path is the second P + implant region, the N-well, the P-well, and the first P + implant region; the second path is the second N + injection region, the N well, the P well and the first N + injection region; the third path is the second N + injection region, the second N-base injection layer, the P-well, and the first N + injection region.
7. The electrostatic protection device of claim 1, wherein the substrate is a P-type silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810661331.8A CN108807373B (en) | 2018-06-25 | 2018-06-25 | Electrostatic protection device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810661331.8A CN108807373B (en) | 2018-06-25 | 2018-06-25 | Electrostatic protection device |
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| CN108807373A CN108807373A (en) | 2018-11-13 |
| CN108807373B true CN108807373B (en) | 2021-04-13 |
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| CN201810661331.8A Active CN108807373B (en) | 2018-06-25 | 2018-06-25 | Electrostatic protection device |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09293881A (en) * | 1996-04-23 | 1997-11-11 | Kaho Denshi Kofun Yugenkoshi | Manufacture of electrostatic discharge protective circuit |
| US6777721B1 (en) * | 2002-11-14 | 2004-08-17 | Altera Corporation | SCR device for ESD protection |
| CN1681122A (en) * | 2004-04-06 | 2005-10-12 | 世界先进积体电路股份有限公司 | High-voltage electrostatic discharging protector with gap structure |
| CN101697355A (en) * | 2009-10-28 | 2010-04-21 | 苏州博创集成电路设计有限公司 | Evenly-triggered semiconductor silicon-controlled rectifier controller for ESD |
| CN102130184A (en) * | 2010-12-22 | 2011-07-20 | 东南大学 | High-robustness back biased diode applied to high-voltage static protection |
| CN102148242A (en) * | 2010-12-30 | 2011-08-10 | 浙江大学 | Silicon controlled device with double-conduction path |
| CN103730462A (en) * | 2014-01-20 | 2014-04-16 | 江南大学 | ESD self-protection device with LDMOS-SCR structure and high in holding current and robustness |
| CN105609488A (en) * | 2015-12-23 | 2016-05-25 | 电子科技大学 | Low-trigger-voltage SCR (semiconductor control rectifier) device used for ESD (electro-static discharge) protection |
-
2018
- 2018-06-25 CN CN201810661331.8A patent/CN108807373B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09293881A (en) * | 1996-04-23 | 1997-11-11 | Kaho Denshi Kofun Yugenkoshi | Manufacture of electrostatic discharge protective circuit |
| US6777721B1 (en) * | 2002-11-14 | 2004-08-17 | Altera Corporation | SCR device for ESD protection |
| CN1681122A (en) * | 2004-04-06 | 2005-10-12 | 世界先进积体电路股份有限公司 | High-voltage electrostatic discharging protector with gap structure |
| CN101697355A (en) * | 2009-10-28 | 2010-04-21 | 苏州博创集成电路设计有限公司 | Evenly-triggered semiconductor silicon-controlled rectifier controller for ESD |
| CN102130184A (en) * | 2010-12-22 | 2011-07-20 | 东南大学 | High-robustness back biased diode applied to high-voltage static protection |
| CN102148242A (en) * | 2010-12-30 | 2011-08-10 | 浙江大学 | Silicon controlled device with double-conduction path |
| CN103730462A (en) * | 2014-01-20 | 2014-04-16 | 江南大学 | ESD self-protection device with LDMOS-SCR structure and high in holding current and robustness |
| CN105609488A (en) * | 2015-12-23 | 2016-05-25 | 电子科技大学 | Low-trigger-voltage SCR (semiconductor control rectifier) device used for ESD (electro-static discharge) protection |
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| CN108807373A (en) | 2018-11-13 |
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