CN108807373A - electrostatic protection device - Google Patents
electrostatic protection device Download PDFInfo
- Publication number
- CN108807373A CN108807373A CN201810661331.8A CN201810661331A CN108807373A CN 108807373 A CN108807373 A CN 108807373A CN 201810661331 A CN201810661331 A CN 201810661331A CN 108807373 A CN108807373 A CN 108807373A
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- Prior art keywords
- injection regions
- well
- traps
- injection
- implanted layers
- Prior art date
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- 238000002347 injection Methods 0.000 claims abstract description 98
- 239000007924 injection Substances 0.000 claims abstract description 98
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000001012 protector Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of electrostatic protection device; including substrate, substrate is equipped with deep N-well, and p-well and N traps are equipped in deep N-well; it is equipped with the first injection regions P+, the first N-base implanted layers and the first injection regions N+ in p-well, the 2nd N-base implanted layers, the 2nd injection regions N+ and the 2nd injection regions P+ are equipped in N traps；First injection regions P+, the first injection regions N+ are connected with cathode；2nd injection regions N+, the 2nd injection regions P+ are connected with anode；The first thin gate oxide is equipped between first injection regions P+ and the first injection regions N+, the first polysilicon gate is covered on first thin gate oxide, it is equipped with the second thin gate oxide between 2nd injection regions N+ and the 2nd injection regions P+, the second polysilicon gate is covered on the second thin gate oxide；2nd N-base implanted layers are connected across between p-well and N traps, and the first N-base implanted layers are located at the lower section of the first injection regions N+.The present invention can solve the problems, such as that trigger voltage is high, resistant to total dose ability is weak.
Description
Technical field
The present invention relates to Integrated circuit electrostatic protection technology fields, more particularly to a kind of electrostatic protection device.
Background technology
LDMOS (Laterally Diffused Metal Oxide Semiconductor, lateral diffused metal oxide
Semiconductor) device is widely used in power management chip, such as DC-DC converter, AC-DC converter.With integrated circuit to
At a high speed, high pressure direction is developed, and the electrostatic protection ability of LDMOS device is weak to become the bottleneck for limiting its development.Therefore, how to improve
The electrostatic protection ability (Electro-Static discharge, ESD) of LDMOS device, becomes the hot spot of research.
Fig. 3 and Fig. 4 are please referred to, in traditional LDMOS electrostatic protection devices, generally use introduces diode or silicon-controlled
Rectifying device (Silicon Controlled Rectifier, SCR) mode enhances its electrostatic leakage ability, but both solve
Certainly scheme haves the shortcomings that trigger voltage is high, resistant to total dose ability is weak, limits the application range of electrostatic protection device, especially
It is that can not be applied in space flight high voltage integrated circuit.
Invention content
In view of above-mentioned condition, it is necessary to a kind of electrostatic protection device is provided, to solve trigger voltage height, resistant to total dose ability
Weak problem.
A kind of electrostatic protection device, including substrate, the substrate are equipped with deep N-well, p-well and N are equipped in the deep N-well
Trap is equipped with the first injection regions P+, the first N-base implanted layers and the first injection regions N+ in the p-well, and the is equipped in the N traps
Two N-base implanted layers, the 2nd injection regions N+ and the 2nd injection regions P+；First injection regions P+, the first injection regions N+ with
Cathode is connected；2nd injection regions N+, the 2nd injection regions P+ are connected with anode；First injection regions P+ and described the
It is equipped with the first thin gate oxide between one injection regions N+, the first polysilicon gate is covered on first thin gate oxide, it is described
The second thin gate oxide, the second thin gate oxide overlying are equipped between 2nd injection regions N+ and the 2nd injection regions P+
It is stamped the second polysilicon gate；The 2nd N-base implanted layers are connected across between the p-well and the N traps, the first N-
Base implanted layers are located at the lower section of the first injection regions N+.
According to above-mentioned electrostatic protection device, between the first injection regions P+ and the first injection regions N+ and the 2nd N+ injects
It replaces thick field oxygen layer to be isolated with polysilicon grating structure between area and the 2nd injection regions P+, device can be effectively improved
Resistant to total dose performance, the 2nd N-base implanted layers are connected across between p-well and N traps, and having reduces trigger voltage, improves resistant to total dose
The effect of performance can expand putting for the neighbouring NPN pipes of cathode in addition, the first N-base implanted layers are located at below the first injection regions N+
Big multiple, while maintenance voltage can be improved, finally having the electrostatic protection device, trigger voltage is low, it is efficient to release, anti-total
The strong advantage of dosage capability, can be applied to the electrostatic protection of space flight high voltage integrated circuit.
In addition, electrostatic protection device proposed by the present invention, can also have following additional technical characteristic：
Further, third thin oxide gate is equipped between the first injection regions N+ and the 2nd injection regions N+ successively
Layer, field oxygen zone are covered with third polysilicon gate on the third thin gate oxide, and the third polysilicon gate is connected with cathode.
Further, the 2nd N-base implanted layers surround the field oxygen zone.
Further, the 2nd injection regions P+, the N traps, the p-well constitute positive-negative-positive structure, the first N+ injections
Area, the p-well, the 2nd N-base implanted layers constitute NPN structures.
Further, the p-well and the N traps are from left to right equipped in the deep N-well successively, in the P traps from a left side to
It is right to be equipped with the first injection regions P+, the first N-base implanted layers and the first injection regions N+ successively, in the N traps
It is from left to right equipped with the 2nd N-base implanted layers, the 2nd injection regions N+ and the 2nd injection regions P+ successively.
Further, from anode to cathode, the electrostatic protection device has the three electrostatic leakage paths, the first paths to be
2nd injection regions P+, the N traps, the p-well, the first injection regions P+；Second paths inject for the 2nd N+
Area, the N traps, the p-well, the first injection regions N+；Third path is the 2nd injection regions N+, the 2nd N-
Base implanted layers, the p-well, the first injection regions N+.
Further, the substrate is P-type silicon substrate.
Description of the drawings
Fig. 1 is the structural schematic diagram for the electrostatic protection device that one embodiment of the invention provides；
Fig. 2 is the equivalent circuit diagram of Fig. 1；
Fig. 3 is the structural schematic diagram of LDMOS electrostatic protection devices in the prior art；
Fig. 4 is the structural schematic diagram of the electrostatic protection device of LDMOS-SCR structures in the prior art.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.Several embodiments of the present invention are given in attached drawing.But the present invention can be to be permitted
Mostly different form is realized, however it is not limited to embodiment described herein.Make on the contrary, purpose of providing these embodiments is
It is more thorough and comprehensive to the disclosure.
It should be noted that when element is referred to as " being fixedly arranged on " another element, it can be directly on another element
Or there may also be elements placed in the middle.When an element is considered as " connection " another element, it can be directly connected to
To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " left side ",
" right side ", "upper", "lower" and similar statement for illustrative purposes only, do not indicate or imply the indicated device or member
Part must have a particular orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can be machine
Tool connects, and can also be electrical connection；It can be directly connected, can also can be indirectly connected through an intermediary two members
Connection inside part.For the ordinary skill in the art, above-mentioned term can be understood in this hair as the case may be
Concrete meaning in bright.Term " and or " used herein include the arbitrary of one or more relevant Listed Items and
All combinations.
It please refers to Fig.1 and Fig. 2, the electrostatic protection device that one embodiment of the invention provides, including substrate 100, specifically at this
In embodiment, substrate 100 is P-type silicon substrate.
The substrate 100 is equipped with deep N-well 200, and p-well 300 and N traps 301 are equipped in the deep N-well 200.Specifically at this
In embodiment, p-well 300 and N traps 301 are set gradually from left to right in deep N-well 200.
The first injection regions P+ 401, the first N-base implanted layers 402 and the first injection regions N+ are equipped in the p-well 300
403.Specifically in the present embodiment, the first injection regions P+ 401, the first N-base implanted layers 402 and the first injection regions N+ 403 are in P
It is set gradually from left to right in trap 300.
The 2nd N-base implanted layers 404, the 2nd injection regions N+ 405 and the 2nd injection regions P+ are equipped in the N traps 301
406.Specifically in the present embodiment, the 2nd N-base implanted layers 404, the 2nd injection regions N+ 405 and the 2nd injection regions P+ 406 exist
It is set gradually from left to right in first N traps 301.
First injection regions P+ 401, the first injection regions N+ 403 are connected with cathode；2nd injection regions N+
405, the 2nd injection regions P+ 406 are connected with anode.
Specifically, the 2nd N-base implanted layers 404 are connected across between the p-well 300 and the N traps 301, it is described
First N-base implanted layers 402 are located at the lower section of the first injection regions N+ 403.
The first thin gate oxide 501, institute are equipped between first injection regions P+ 401 and the first injection regions N+ 403
It states and is covered with the first polysilicon gate 502 on the first thin gate oxide 501, the 2nd injection regions N+ 405 and the 2nd P+ is noted
Enter and be equipped with the second thin gate oxide 503 between area 406, the second polysilicon gate is covered on second thin gate oxide 503
504。
2nd injection regions P+ 406, the N traps 301, the p-well 300 constitute positive-negative-positive structure, i.e. triode Qp；It is described
First injection regions N+ 403, the p-well 300, the 2nd N-base implanted layers 404 constitute NPN structures, i.e. triode Qn.
Wherein, Rpw is p well resistances, and Rnw is n well resistances.
It is thin that third is equipped in the present embodiment, between the first injection regions N+ 403 and the 2nd injection regions N+ 405 successively
Gate oxide 505, field oxygen zone 506 are covered with third polysilicon gate 507 on the third thin gate oxide 505, and the third is more
Crystal silicon grid 507 are connected with cathode.The 2nd N-base implanted layers 404 surround the field oxygen zone 506.
From anode to cathode, it is the 2nd P that the electrostatic protection device, which has three electrostatic leakage paths, the first paths,
+ injection region 406, the N traps 301, the p-well 300, the first injection regions P+ 401；Second paths are noted for the 2nd N+
Enter area 405, the N traps 301, the p-well 300, the first injection regions N+ 403；Third path is injected for the 2nd N+
Area 405, the 2nd N-base implanted layers 404, the p-well 300, the first injection regions N+ 403, therefore with stronger quiet
Electric relieving capacity is released efficient.
According to electrostatic protection device provided in this embodiment, between the first injection regions P+ and the first injection regions N+, Yi Ji
It replaces thick field oxygen layer to be isolated with polysilicon grating structure between two injection regions N+ and the 2nd injection regions P+, can effectively carry
The resistant to total dose performance of high device, the 2nd N-base implanted layers are connected across between p-well and N traps, and having reduces trigger voltage, improves
The effect of resistant to total dose performance can expand near cathode in addition, the first N-base implanted layers are located at below the first injection regions N+
The amplification factor of NPN pipes, while maintenance voltage can be improved, finally having the electrostatic protection device, trigger voltage is low, effect of releasing
The advantage that rate is high, resistant to total dose ability is strong, can be applied to the electrostatic protection of space flight high voltage integrated circuit.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiments or example in can be combined in any suitable manner.
Several embodiments of the invention above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
Cannot the limitation to the scope of the claims of the present invention therefore be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (7)
1. a kind of electrostatic protection device, which is characterized in that including substrate, the substrate is equipped with deep N-well, is set in the deep N-well
There are a p-well and N traps, be equipped with the first injection regions P+, the first N-base implanted layers and the first injection regions N+ in the p-well, in the N traps
Equipped with the 2nd N-base implanted layers, the 2nd injection regions N+ and the 2nd injection regions P+；First injection regions P+, the first N+ notes
Enter area with cathode to be connected；2nd injection regions N+, the 2nd injection regions P+ are connected with anode；First injection regions P+ with
It is equipped with the first thin gate oxide between first injection regions N+, the first polysilicon is covered on first thin gate oxide
Grid are equipped with the second thin gate oxide, second thin oxide gate between the 2nd injection regions N+ and the 2nd injection regions P+
It is covered with the second polysilicon gate on layer；The 2nd N-base implanted layers are connected across between the p-well and the N traps, and described
One N-base implanted layers are located at the lower section of the first injection regions N+.
2. electrostatic protection device according to claim 1, which is characterized in that the first injection regions N+ and the 2nd N+
Third thin gate oxide, field oxygen zone are equipped between injection region successively, third polysilicon is covered on the third thin gate oxide
Grid, the third polysilicon gate are connected with cathode.
3. electrostatic protection device according to claim 2, which is characterized in that the 2nd N-base implanted layers are by the field
Oxygen area surrounds.
4. electrostatic protection device according to claim 1, which is characterized in that the 2nd injection regions P+, the N traps, institute
It states p-well and constitutes positive-negative-positive structure, the first injection regions N+, the p-well, the 2nd N-base implanted layers constitute NPN structures.
5. electrostatic protection device according to claim 1, which is characterized in that be from left to right equipped with successively in the deep N-well
The p-well and the N traps are from left to right equipped with the first injection regions P+ in the p-well successively, the first N-base injects
Layer and the first injection regions N+ are from left to right equipped with the 2nd N-base implanted layers, the 2nd N+ in the N traps successively
Injection region and the 2nd injection regions P+.
6. electrostatic protection device according to claim 1, which is characterized in that from anode to cathode, the electrostatic protector
It is the 2nd injection regions P+, the N traps, the p-well, the first P+ that part, which has three electrostatic leakage paths, the first paths,
Injection region；Second paths are the 2nd injection regions N+, the N traps, the p-well, the first injection regions N+；Article 3 road
Diameter is the 2nd injection regions N+, the 2nd N-base implanted layers, the p-well, the first injection regions N+.
7. electrostatic protection device according to claim 1, which is characterized in that the substrate is P-type silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810661331.8A CN108807373B (en) | 2018-06-25 | 2018-06-25 | Electrostatic protection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810661331.8A CN108807373B (en) | 2018-06-25 | 2018-06-25 | Electrostatic protection device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108807373A true CN108807373A (en) | 2018-11-13 |
| CN108807373B CN108807373B (en) | 2021-04-13 |
Family
ID=64070820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810661331.8A Active CN108807373B (en) | 2018-06-25 | 2018-06-25 | Electrostatic protection device |
Country Status (1)
| Country | Link |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09293881A (en) * | 1996-04-23 | 1997-11-11 | Kaho Denshi Kofun Yugenkoshi | Manufacture of electrostatic discharge protective circuit |
| US6777721B1 (en) * | 2002-11-14 | 2004-08-17 | Altera Corporation | SCR device for ESD protection |
| CN1681122A (en) * | 2004-04-06 | 2005-10-12 | 世界先进积体电路股份有限公司 | High-voltage electrostatic discharging protector with gap structure |
| CN101697355A (en) * | 2009-10-28 | 2010-04-21 | 苏州博创集成电路设计有限公司 | Evenly-triggered semiconductor silicon-controlled rectifier controller for ESD |
| CN102130184A (en) * | 2010-12-22 | 2011-07-20 | 东南大学 | High-robustness back biased diode applied to high-voltage static protection |
| CN102148242A (en) * | 2010-12-30 | 2011-08-10 | 浙江大学 | Silicon controlled device with double-conduction path |
| CN103730462A (en) * | 2014-01-20 | 2014-04-16 | 江南大学 | ESD self-protection device with LDMOS-SCR structure and high in holding current and robustness |
| CN105609488A (en) * | 2015-12-23 | 2016-05-25 | 电子科技大学 | Low-trigger-voltage SCR (semiconductor control rectifier) device used for ESD (electro-static discharge) protection |
-
2018
- 2018-06-25 CN CN201810661331.8A patent/CN108807373B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09293881A (en) * | 1996-04-23 | 1997-11-11 | Kaho Denshi Kofun Yugenkoshi | Manufacture of electrostatic discharge protective circuit |
| US6777721B1 (en) * | 2002-11-14 | 2004-08-17 | Altera Corporation | SCR device for ESD protection |
| CN1681122A (en) * | 2004-04-06 | 2005-10-12 | 世界先进积体电路股份有限公司 | High-voltage electrostatic discharging protector with gap structure |
| CN101697355A (en) * | 2009-10-28 | 2010-04-21 | 苏州博创集成电路设计有限公司 | Evenly-triggered semiconductor silicon-controlled rectifier controller for ESD |
| CN102130184A (en) * | 2010-12-22 | 2011-07-20 | 东南大学 | High-robustness back biased diode applied to high-voltage static protection |
| CN102148242A (en) * | 2010-12-30 | 2011-08-10 | 浙江大学 | Silicon controlled device with double-conduction path |
| CN103730462A (en) * | 2014-01-20 | 2014-04-16 | 江南大学 | ESD self-protection device with LDMOS-SCR structure and high in holding current and robustness |
| CN105609488A (en) * | 2015-12-23 | 2016-05-25 | 电子科技大学 | Low-trigger-voltage SCR (semiconductor control rectifier) device used for ESD (electro-static discharge) protection |
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| CN108807373B (en) | 2021-04-13 |
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