CN101887847B - Method for forming monocrystal silicon structure with alternated P types and N types - Google Patents
Method for forming monocrystal silicon structure with alternated P types and N types Download PDFInfo
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Abstract
The invention discloses a method for forming a monocrystal silicon structure with alternated P types and N types, comprising the following steps: depositing a layer of P type monocrystal silicon or P type polycrystalline silicon with high doped concentration on a groove, dispersing P type impurities to the side wall and bottom part of the groove by adopting a diffusion process to form a P type layer on the side wall and/or bottom part of the groove, and oxidizing the deposited P type monocrystal silicon or P type polycrystalline silicon into silica. The method in the invention lowers the technical requirements on the epitaxy or deposition process of the traditional P type epitaxy method, and can obtain seamless groove filling effect so as to improve the reliability of a semiconductor device using the process.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacturing process, particularly relate to the P type that a kind of formation replaces and the method for n type single crystal silicon structure.
Background technology
See also Fig. 1, this is plane super junction metal-oxide-semiconductor (super junction MOSFET) cellular construction schematic diagram.Have one deck N type epitaxial loayer 12 on N type heavily doped silicon substrate 11, have a groove on the epitaxial loayer 12, this channel bottom extends to silicon substrate 11.The sidewall of groove is a P type layer 13, promptly around and next-door neighbour trenched side-wall N type epitaxial loayer 12 on formed P type doped silicon regions.Next-door neighbour's trenched side-wall and bottom have silicon dioxide layer 141 in the groove, are filled with filler 142 again toward in, and filler 142 can be plain unformed silicon, plain polysilicon, silicon dioxide, silicon nitride, oxidized silicon nitride (SiO
xN
y) or its any combination.P type heavily doped region 18 is arranged at P type layer 13 top (near epitaxial loayer 12 surfaces), and outwards there is N type heavily doped region 19 both sides as source electrode again, and outwards both sides are P trap 17 again.Have on the epitaxial loayer 12 gate oxide 15 with and on polysilicon gate 16, gate oxide 15 is right after source electrode 19 on upper-lower position.Ground floor inter-level dielectric (ILD-1) layer 21 is arranged on grid 16, part source electrode 19, the trench filling 14.On inter-level dielectric 21, part source electrode 19, the P type heavily doped region 18 source electrode metal electrode layer 22 is arranged.
Above-mentioned super junction metal-oxide-semiconductor adopts new structure of voltage-sustaining layer, promptly utilizes N type epitaxial loayer 12 and next-door neighbour's P type layer 13 to form the P type and the n type single crystal silicon structure of alternately arranging.This new structure of voltage-sustaining layer has following characteristic: under cut-off state, applied voltage makes the existing transverse electric field of device inside that longitudinal electric field also be arranged, if before puncturing generation, charge carrier in P type and the n type single crystal silicon is all depleted, realize that hole and electronics compensate mutually, the puncture voltage of device just only depends on the thickness of N type epitaxial loayer 12 so, and it is irrelevant with the doping content of N type epitaxial loayer 12, thereby can utilize the N type epitaxial loayer 12 of high-dopant concentration, when obtaining low on-resistance, realize the high-breakdown-voltage of super junction metal-oxide-semiconductor, the theoretical limit of the power MOS pipe that breaks traditions.
The manufacture method of above-mentioned P type that replaces and n type single crystal silicon structure has multiple at present.First kind is to utilize repeatedly photoetching, epitaxial growth and ion to inject to prepare, this method not only complex process, realize that difficulty is big but also cost is very high.Second kind is first etching groove on N type epitaxial loayer, deposit P type polysilicon in groove again, and deposit P type polysilicon is difficult to obtain the concentration of needs in this method on technology, and there is the big problem of leaking electricity in P type polysilicon under reverse voltage.The third is elder generation's etching groove on N type epitaxial loayer, carries out the ion injection of p type impurity at trenched side-wall and/or bottom with the angle of inclination again, and the stability of this method and poor repeatability can not be with going into to produce in batches.The 4th kind is elder generation's etching groove on N type epitaxial loayer, in groove, carry out P type epitaxial growth (deposit monocrystalline silicon) again, carry out cmp (CMP) then, this is present common way, this method for gash depth in 40～50 μ m or darker situation, exist the process time long, cost is high relatively and be difficult to obtain seamless filled shortcoming, and since epitaxial growth in groove, its defective control is also very difficult.
Summary of the invention
Technical problem to be solved by this invention provides the P type that a kind of formation replaces and the method for n type single crystal silicon structure.
For solving the problems of the technologies described above, the present invention forms P type alternately and the method for n type single crystal silicon structure comprises the steps:
The 1st step had one deck N type epitaxial loayer on N type heavily doped silicon substrate, thermal oxide growth or be deposited with layer of silicon dioxide on it is deposited with one deck dielectric layer again on it; The doping content of described N type heavily doped silicon substrate is 10
19The order of magnitude that atom is every cubic centimetre;
In the 2nd step, etching one groove on silicon chip passes dielectric layer, silicon dioxide layer, part or all of epitaxial loayer, and channel bottom is positioned at epitaxial loayer or silicon substrate;
The 3rd step, the p type single crystal silicon of deposit one deck high-dopant concentration or P type polysilicon in groove; Impurity concentration in the p type single crystal silicon of institute's deposit or the P type polysilicon is 5 * 10
16～1 * 10
17Every cubic centimetre in atom;
The 4th step, adopt diffusion technology that the p type impurity in p type single crystal silicon or the P type polysilicon is diffused into the sidewall and the bottom of groove, form a P type layer thereby make the sidewall of groove or sidewall and bottom become p type single crystal silicon by original n type single crystal silicon;
The 5th step, the dielectric layer of removal silicon chip surface;
In the 6th step, adopt dry etch process to anti-carve the silicon dioxide of silicon chip surface until etching into epitaxial loayer;
The 7th step is in the plain unformed silicon of silicon chip surface deposit one deck or plain polysilicon or medium or its any combination;
In the 8th step, remove plain unformed silicon or plain polysilicon or medium or its any combination on the epitaxial loayer.
As a further improvement on the present invention, in described the 1st step of method, the 2nd step, the 5th step, the 7th step, the 8th step, described medium is any combination of silicon nitride, silica, oxidized silicon nitride or three.
Described method is in the 3rd step, and in the monocrystalline silicon or polysilicon of institute's deposit, impurity concentration is 5 * 10
15～1 * 10
17Every cubic centimetre in atom, deposition thickness are 0.5～2 μ m.
Described method is in the 4th step, and described p type single crystal silicon or P type polysilicon also become silicon dioxide in high-temperature diffusion process;
Perhaps described method is in the 4th step, and increasing oxidation technology after High temperature diffusion technology is silicon dioxide with described p type single crystal silicon or P type polysilicon oxidation.
The 5th step and the 6th step of described method can also change into:
The 5th ' step is till the silicon dioxide film that the silicon dioxide that adopts dry etch process to anti-carve the silicon dioxide of silicon chip surface and groove top protrudes up to groove top is carved;
The 6th ' step, the dielectric layer and the silicon oxide layer of removal silicon chip surface.
Described method is in the 7th step, and the plain unformed silicon of institute's deposit or plain polysilicon or medium or its three's is any in conjunction with the described groove of filling, and does not have the cavity of sealing in the described groove.
The method of the invention has reduced the technological requirement of traditional P type epitaxy method to extension or depositing technics, can also obtain the seamless groove filling effect, thereby improves the reliability of the semiconductor device that adopts this kind technology.
Description of drawings
Fig. 1 is the cellular construction schematic diagram of super junction metal-oxide-semiconductor;
Fig. 2 a～Fig. 2 h is the silicon chip generalized section of each step of the present invention.
Description of reference numerals among the figure:
11 is N type heavily doped silicon substrate; 12 is N type epitaxial loayer; 13 is P type layer; 141 is silicon dioxide; 142 is trench filling; 15 is gate oxide; 16 is polysilicon gate; 17 is the P trap; 18 is P type heavily doped region; 19 is N type doped region (source electrode); 21 is inter-level dielectric; 22 is the source metal electrode; 23 is contact hole; 31 is silica; 32 is dielectric layer; 33 is groove; 34 is p type single crystal silicon or P type polysilicon; 35 is silicon dioxide; 36 is trench filling.
Embodiment
P type that replaces of the present invention and n type single crystal silicon structure comprise two kinds of situations, first kind is to form P type layer on N type epitaxial loayer and/or silicon substrate, and described P type layer is meant by p type single crystal silicon or P type polysilicon sidewall and/or the bottom p type single crystal silicon through diffuseing to form at groove; Second kind is to form N type layer on P type epitaxial loayer and/or silicon substrate, and described N type layer is meant by n type single crystal silicon or N type polysilicon sidewall and/or the bottom n type single crystal silicon through diffuseing to form at groove.Be that example describes in detail with first kind of situation only below, second kind of situation can be implemented according to first kind of situation fully.
The present invention forms P type alternately and the method for n type single crystal silicon structure comprises the steps:
The 1st step saw also Fig. 2 a, had one deck N type epitaxial loayer 12 on N type heavily doped silicon substrate 11, thermal oxide growth or deposit layer of silicon dioxide 31 on epitaxial loayer 12, deposit one deck dielectric layer 32 again on silicon oxide layer 31.Silicon oxide layer 31 is as the resilient coating of dielectric layer 32, and the thickness of silicon oxide layer 31 can be 150～300
Dielectric layer 32 can be any combination of silicon nitride, silica, oxidized silicon nitride or three etc., and thickness is 1000～3000
The 2nd step saw also Fig. 2 b, had etched groove 33 on silicon chip.The plane super junction metal-oxide-semiconductor device epitaxial thickness of general 600V is 40～50 μ m, and the degree of depth of groove 33 can be 40～50 μ m (penetrate epitaxial loayer 22, groove 33 bottoms are positioned at silicon substrate 11, shown in Fig. 2 b); Also can be 20-30 μ m (rest in the epitaxial loayer 22, groove 33 bottoms are positioned at epitaxial loayer 22, and are not shown).The width of groove 33 can be 1.5～5 μ m, decides according to the specific design of device.When etching groove 33, can utilize photoresist or dielectric layer 32 as mask layer.
Above-mentioned the 1st～2 step is to etch groove on silicon chip, and this two step can be thought preliminary step of the present invention.
In the 3rd step, see also Fig. 2 c, the p type single crystal silicon 34 of deposit one deck high-dopant concentration (being extension) in groove 33, perhaps the P type polysilicon 34 of deposit one deck high-dopant concentration in groove 33.Impurity concentration in described p type single crystal silicon or the P type polysilicon 34 can be 5 * 10
15～1 * 10
17Every cubic centimetre in atom (or ion), deposition thickness are 0.5～2 μ m.
The 4th step saw also Fig. 2 d, adopted diffusion technology that the p type impurity in p type single crystal silicon or the P type polysilicon 34 is diffused into the sidewall and the bottom of groove 33, needed the district here in two kinds of situation.First kind of situation, when groove 33 has penetrated epitaxial loayer 22, the operation of this step makes the sidewall of groove 33 become p type single crystal silicon (P type layer) by original n type single crystal silicon (epitaxial loayer 12), but the bottom of groove 33 still is a N type silicon substrate 11.This is because the doping content of N type silicon substrate 11 is generally 10
19The order of magnitude that atom is every cubic centimetre, 10
15～10
17The N type doping content of the p type impurity diffusion couple silicon substrate 11 that atom is every cubic centimetre is not influence almost.The P type layer of this moment exists only in the sidewall of groove 33, shown in Fig. 2 d.Second kind of situation, when groove 33 rests in the epitaxial loayer 22, the operation of this step makes the sidewall of groove 33 and bottom all become p type single crystal silicon (P type layer) by original n type single crystal silicon (epitaxial loayer 12).The P type layer of this moment is present in sidewall and bottom (not shown) of groove 33 simultaneously.
In the operation of this step, p type single crystal silicon or P type polysilicon 34 can be oxidized to silicon dioxide 35 simultaneously in high-temperature diffusion process.Perhaps, after High temperature diffusion technology, adopt oxidation technology that p type single crystal silicon or P type polysilicon 34 are oxidized to silicon dioxide 35.
The 5th step saw also Fig. 2 e, removed the dielectric layer 32 of silicon chip surface.When for example dielectric layer 32 is silicon nitride, can adopt wet corrosion technique, dry etch process or both combinations to remove.
The 6th step saw also Fig. 2 f, adopted dry etch process to anti-carve (return and carve) silicon dioxide 31 and the silicon dioxide 35 that protrudes from the silicon chip surface, stopped etching when etching into the upper surface of epitaxial loayer 12.This step for example can be adopted high density plasma etch technology.This step is removed near the protrusion position of silicon dioxide 35 groove 33 openings, thereby the opening of groove 33 is enlarged, and is convenient to follow-up groove be filled.
The 7th step, see also Fig. 2 g, in the plain unformed silicon of silicon chip surface deposit one deck (Amorphous silicon) 36, plain polysilicon 36, medium 36 or its any combination, dielectric layer 36 wherein can be silicon dioxide, silicon nitride, oxidized silicon nitride or its any combination etc.If this step filler 36 is a silica, then be combined into one deck with silicon dioxide 35, the deposit of this silica can adopt chemical vapor deposition (CVD) or high-density plasma chemical vapor deposition (HDPCVD) to improve filling capacity.If filler 36 is plain unformed silicon or plain polysilicon, then before deposit, form one deck 100～500 with oxidation technology or depositing technics at silicon chip surface earlier
The oxide layer of thickness (not shown).Anti-carve owing to have once before this step, so filler 36 can be with groove 33 seamless filled (being the cavity that there is not sealing in groove 33 inside) in this step.The width of opening part that the thickness of filler 36 is finished back groove 33 according to the 6th step decide, common deposition thickness be the 6th go on foot finish after 0.5～0.8 times of width of opening part of groove 33.
The 8th step saw also Fig. 2 h, removed the deposit 36 (being trench filling 36) on the epitaxial loayer 12.This step can adopt chemical mechanical milling tech, dry etch process to anti-carve or both combinations realize.
In the said method, the 5th step and the 6th step can change into:
The 5th ' step, adopt dry etch process to anti-carve the silicon dioxide 35 on (return and carve) groove 33 tops, to major general's silicon dioxide 35 till near the protrusion position groove 33 openings etches away, ideally silicon dioxide 35 can be etched into the upper surface that arrives at epitaxial loayer 12.This step can make the opening of groove 33 enlarge, and is convenient to follow-up groove be filled.
The 6th ' step, the dielectric layer 32 of removal silicon chip surface and silicon dioxide 31 are until the upper surface that arrives epitaxial loayer 12.If the 5th ' silicon dioxide 35 that anti-carves of step also on the upper surface of epitaxial loayer 12, also remove the silicon dioxide on the epitaxial loayer 12 35 simultaneously by this step.This step can be adopted wet corrosion technique, dry etch process, chemical mechanical milling tech or its any combination.
The above-mentioned the 5th ' step, the 6th ' step in, if the material of dielectric layer 32 is exactly a silicon dioxide, so the 5th ' step and the 6th ' step can merge, and unifiedly adopts that dry etching anti-carves, the technology of wet etching, cmp or its combination removes dielectric layer 32, silicon dioxide 31 and silicon dioxide 35 upper surface until arrival epitaxial loayer 12.
The present invention forms the P type alternately and the method for n type single crystal silicon structure, and its 3rd～4 step is filled the P type silicon of high concentration earlier in groove, p type impurity is diffused into the sidewall and/or the bottom of groove, at last with the P type silicon oxidation of being filled again; So just reduced the technological requirement of traditional P type epitaxy method to extension or depositing technics.Its 5th～7 step adopts earlier and anti-carves the silica that technology is removed the groove upper portion side wall, fills in groove again; Can obtain the seamless groove filling effect like this, thereby improve the reliability of the semiconductor device that adopts this kind technology.
Said method has only been introduced " forming P type layer on N type epitaxial loayer and/or silicon substrate ", if want " on P type epitaxial loayer and/or silicon substrate, forming N type layer ", can contrast said method, only need " P " in each step of said method and " N " exchange is got final product.
Same, " forming N type layer on P type epitaxial loayer and/or silicon substrate " also has differentiation:
A kind situation, P type that replaces and n type single crystal silicon structure are the N type layers that forms on P type silicon epitaxy layer, and described N type layer is meant the sidewall and the bottom of a groove that is made of n type single crystal silicon;
This moment, described groove passed dielectric layer, silicon dioxide layer and part epitaxial loayer in the 2nd step, and channel bottom is positioned at epitaxial loayer; In the 4th step, adopt diffusion technology with sidewall and the bottom of the N type diffusion of impurities in n type single crystal silicon or the N type polysilicon to groove, form a N type layer thereby make the sidewall of groove and bottom become n type single crystal silicon by original p type single crystal silicon.
B kind situation, P type that replaces and n type single crystal silicon structure are the N type layers that forms on P type silicon epitaxy layer and silicon substrate, and described N type layer is meant the sidewall of a groove that is made of n type single crystal silicon;
This moment, described groove passed dielectric layer, silicon dioxide layer and whole epitaxial loayer in the 2nd step, and channel bottom is positioned at silicon substrate; In the 4th step, adopt diffusion technology with sidewall and the bottom of the N type diffusion of impurities in n type single crystal silicon or the N type polysilicon to groove, form a N type layer thereby make the sidewall of groove become n type single crystal silicon by original p type single crystal silicon.
Adopt the method for the invention, and, can make plane super junction metal-oxide-semiconductor as shown in Figure 1 in conjunction with ripe VDMOS (vertical conduction MOS metal-oxide-semiconductor) processing technology.Be that example describes only below, see also Fig. 1 with 600 volts of plane super junction metal-oxide-semiconductors (VDMOS).
(resistivity is to have thick highly doped of one deck 40～50 μ m on 0.001～0.002ohmcm) the N type silicon substrate 11 (resistivity is 1～3ohmcm) N type epitaxial loayer 12 highly doped.This is a readiness, comprises successively that thereafter (thickness is 6000～10000 to deposit silicon dioxide as guard ring
Not shown); Guard ring is carried out ion to be injected;～the 8 step of the 1st step of the present invention (when carrying out for the 7th step, the impurity that the guard ring ion is injected spreads and pushes away trap simultaneously); (thickness is 800～1000 to form gate oxide 15
); (thickness is 2000～4000 to the deposit polysilicon usually
); Etch polysilicon gate 16; Ion injects and forms P trap 17 and P type heavily doped region 18; Ion injects and forms N type heavily doped region 19; (thickness is 8000～10000 to deposit interlayer dielectric layer 21
); Etching contact hole 23; (thickness is 20000～40000 to deposit source metal electrode layer 22
); Thinning back side and back face metalization (not shown) etc.
With N among said method and Fig. 1 and the exchange of P symbol, can obtain the manufacture craft of PMOS.And the method for the invention had both gone for planar device shown in Figure 1, also went for vertical-type device (not shown).
The described technology of above embodiment, step, numerical value only are signal, and any variation and the modification done under the prerequisite of not violating the principle of the invention, spirit and thought all should be regarded as within protection scope of the present invention.
Claims (9)
1. one kind forms the P type alternately and the method for n type single crystal silicon structure, it is characterized in that,
Described P type that replaces and n type single crystal silicon structure are the P type layers that forms at N type silicon epitaxy layer, and described P type layer is meant sidewall or the sidewall and the bottom of a groove that is made of p type single crystal silicon;
Described method comprises the steps:
The 1st step had one deck N type epitaxial loayer on N type heavily doped silicon substrate, thermal oxide growth or be deposited with layer of silicon dioxide on it is deposited with one deck dielectric layer again on it; The doping content of described N type heavily doped silicon substrate is 10
19The order of magnitude that atom is every cubic centimetre;
In the 2nd step, etching one groove on silicon chip passes dielectric layer, silicon dioxide layer, part or all of epitaxial loayer, and channel bottom is positioned at epitaxial loayer or silicon substrate;
The 3rd step, the p type single crystal silicon of deposit one deck high-dopant concentration or P type polysilicon in groove; Impurity concentration in the p type single crystal silicon of institute's deposit or the P type polysilicon is 5 * 10
15～1 * 10
17Every cubic centimetre in atom;
The 4th step, adopt diffusion technology that the p type impurity in p type single crystal silicon or the P type polysilicon is diffused into the sidewall and the bottom of groove, form a P type layer thereby make the sidewall of groove or sidewall and bottom become p type single crystal silicon by original n type single crystal silicon;
The 5th step, the dielectric layer of removal silicon chip surface;
In the 6th step, adopt dry etch process to anti-carve the silicon dioxide of silicon chip surface until etching into epitaxial loayer;
The 7th step is in any combination of the plain unformed silicon of silicon chip surface deposit one deck or plain polysilicon or medium or its three;
The 8th step, the plain unformed silicon on the removal epitaxial loayer or any combination of plain polysilicon or medium or its three.
2. the P type that formation according to claim 1 replaces and the method for n type single crystal silicon structure, it is characterized in that, described P type that replaces and n type single crystal silicon structure are the P type layers that forms on N type silicon epitaxy layer, and described P type layer is meant the sidewall and the bottom of a groove that is made of p type single crystal silicon;
Described method is in the 2nd step, and described groove passes dielectric layer, silicon dioxide layer and part epitaxial loayer, and channel bottom is positioned at epitaxial loayer;
Described method adopts diffusion technology that the p type impurity in p type single crystal silicon or the P type polysilicon is diffused into the sidewall and the bottom of groove in the 4th step, forms a P type layer thereby make the sidewall of groove and bottom become p type single crystal silicon by original n type single crystal silicon.
3. the P type that formation according to claim 1 replaces and the method for n type single crystal silicon structure, it is characterized in that, described P type that replaces and n type single crystal silicon structure are the P type layers that forms at N type silicon epitaxy layer, and described P type layer is meant the sidewall of a groove that is made of p type single crystal silicon;
Described method is in the 2nd step, and described groove passes dielectric layer, silicon dioxide layer and whole epitaxial loayer, and channel bottom is positioned at silicon substrate;
Described method adopts diffusion technology that the p type impurity in p type single crystal silicon or the P type polysilicon is diffused into the sidewall and the bottom of groove in the 4th step, forms a P type layer thereby make the sidewall of groove become p type single crystal silicon by original n type single crystal silicon.
4. the P type that formation according to claim 1 replaces and the method for n type single crystal silicon structure, it is characterized in that, in described the 1st step of method, the 2nd step, the 5th step, the 7th step, the 8th step, described medium is any combination of silicon nitride, silica, oxidized silicon nitride or three.
5. the P type that formation according to claim 1 replaces and the method for n type single crystal silicon structure is characterized in that, described method is in the 3rd step, and the monocrystalline silicon of institute's deposit or the deposition thickness of polysilicon are 0.5～2 μ m.
6. the P type that formation according to claim 1 replaces and the method for n type single crystal silicon structure is characterized in that, described method is in the 4th step, and described p type single crystal silicon or P type polysilicon also become silicon dioxide in diffusion technology;
Perhaps described method is in the 4th step, and increasing oxidation technology after diffusion technology is silicon dioxide with described p type single crystal silicon or P type polysilicon oxidation.
7. the P type that formation according to claim 6 replaces and the method for n type single crystal silicon structure is characterized in that, the 5th step and the 6th step of described method change into:
The 5th ' step, adopt dry etch process to anti-carve the silicon dioxide on groove top, etch away to the protrusion position of the silicon dioxide on major general's groove top;
The 6th ' go on foot, remove the dielectric layer and the silicon oxide layer of silicon chip surface, comprise the silicon dioxide on groove top, until arriving epitaxial loayer.
8. the P type that formation according to claim 1 replaces and the method for n type single crystal silicon structure, it is characterized in that, described method is in the 7th step, the plain unformed silicon of institute's deposit or plain polysilicon or medium or its three's is any in conjunction with the described groove of filling, and does not have the cavity of sealing in the described groove.
9. the P type that replaces according to any one described formation in the claim 1 to 8 and the method for n type single crystal silicon structure, it is characterized in that, described P type that replaces and n type single crystal silicon structure are to form N type layer at P type epitaxial loayer, and described N type layer is meant sidewall or the sidewall and the bottom of a groove that is made of n type single crystal silicon;
In the 1st～8 step of described method, alphabetical P and alphabetical N are exchanged.
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |