CN101882471A - Device and method for detecting word line defects - Google Patents

Abstract

The invention discloses a method for detecting a word line defect, which comprises the following steps of: starting a first word line so as to read a first data which is pre-stored in a storage unit; making the first word line positioned in a suspension state in a preset time, and writing a second data which is complementary to the first data in the storage unit; starting the first word line again so as to read a third data from the storage unit; and comparing the second data and the third data so as to judge whether an electric connection path is present between the first word line and the second word line.

Description

Device and method for detecting word line defects

technical field

The present invention relates to a detection device for a word line defect, more specifically, relates to a detection device for detecting whether a word line is short-circuited with other word lines to cause a defect.

Background technique

In the memory, the user can store data into a corresponding memory unit through a word line (Word Line) and a bit line (Bit Line). However, if a first word line and a second word line are short-circuited, when the user intends to store a data in a first memory cell corresponding to the first word line, the data will also be stored in the corresponding memory cell at the same time. A second memory cell on the second word line, in this way, the data originally stored in the second memory cell will be overwritten, causing the user to read wrong data when reading the second memory cell , causing inconvenience to users.

Contents of the invention

The invention provides a detection device for a word line defect. The detection device includes a first word line coupled to at least one memory cell; a second word line disposed adjacent to the first word line; and a controller coupled to the first word line and the second word line line, the controller first activates the first word line to read a first data pre-stored in the memory cell, the controller then makes the first word line in a floating state for a predetermined time, and then writes A second data complementary to the first data is sent to the memory cell, and then the controller activates the first word line again to read a third data from the memory cell, and compares the third data with the first Two data are used to determine whether there is an electrical connection path between the first word line and the second word line.

The present invention also provides a method for detecting a word line defect, wherein a memory cell is coupled to a first word line and a second word line adjacent to the first word line. The method includes (a) activating the first word line to read a first data pre-stored in the memory cell; (b) keeping the first word line in a floating state for a predetermined time, and then writing and the first data A second data complementary to the first data is sent to the memory cell; (c) reactivating the first word line to read a third data from the memory cell; and (d) comparing the second data with the third data to determine whether there is an electrical connection path between the first word line and the second word line.

Description of drawings

By referring to the foregoing description and the following accompanying drawings, the technical features and advantages of the present invention can be fully understood.

1 is a schematic diagram illustrating a detection device for word line defects of the present invention;

FIG. 2 is a flowchart illustrating a method for detecting word line defects of the present invention.

Among them, reference signs

100 word line defect detection device controller

120 Decoder

B ₁ , B ₂ bit lines

W ₁ , W ₂ word lines

P ₁ , P ₂ drive

M ₁₁ , M ₁₂ , M ₂₁ , M ₂₂ storage units

201～207 Steps

Detailed ways

Please refer to Figure 1. FIG. 1 is a schematic diagram illustrating a word line defect detection device 100 of the present invention. The detection device 100 includes a controller 110, a decoder 120, two drivers P ₁ and P ₂ , two word lines W ₁ and W ₂ , and two bit lines B ₁ and B ₂ , wherein the word lines W ₁ and W ₂ is adjacent.

The memory cells M ₁₁ and M ₁₂ are coupled to the word line W ₁ and are respectively coupled to the bit lines B ₁ and B ₂ ; the memory cells M ₂₁ and M ₂₂ are coupled to the word line W ₂ and are respectively coupled to the bit lines B ₁ and B ₂ .

Please refer to Figure 2. FIG. 2 is a flowchart illustrating a method 200 for detecting word line defects of the present invention. Assuming that the detection device 100 intends to detect whether the word line _W1 is defective, that is, the detection device 100 will determine whether there is an electrical connection path between the word line _W1 and the adjacent word line _W2 , then the detection The device 100 will perform the steps described in FIG. 2 . The details are as follows:

Step 201: the controller 110 controls the decoder 120 and the driver P ₁ to activate the word line W ₁ while keeping the word line W ₂ in a deactivated state;

Step 202: the controller 110 reads the data D ₁ stored in the corresponding storage unit M ₁₁ through the bit line B ₁ ;

Step 203: the controller 110 turns off the decoder 120 and the driver P ₁ for a predetermined time T _P , so that the word line W ₁ is in a suspended state (suspending);

Step 204: After the predetermined time T _P , the controller 110 turns on the driver P ₁ (the decoder 120 is still turned off), takes the complementary state (complementary) of the data D ₁ as the data D ₂ , and passes the bit line B ₁ to the Data D ₂ is written in storage unit M ₁₁ ;

Step 205: the controller 110 controls the decoder 120 and the driver P ₁ to enable the word line W ₁ again;

Step 206: the controller 110 reads the data D ₃ stored in the memory unit M ₁₁ through the bit line B ₁ ;

Step 207: The controller 110 determines whether there is an electrical connection path between the word line W ₁ and the adjacent word line W ₂ according to the data D ₁ and D ₃ .

The activation and deactivation of the word lines are performed by the decoder 120 and its corresponding driver. For example, if the word line W ₁ is to be activated, the decoder 120 needs to send a signal representing “enable” to the driver P ₁ , and the word line W ₁ will be activated; otherwise, if the word line W ₂ is to be deactivated, then The decoder 120 needs to send a signal representing “disable” to the driver P ₂ , so that the word line W ₂ will be deactivated. In addition, the activated word line W ₁ and the deactivated word line W ₂ are respectively driven to an activation potential V _ACT and a deactivation potential V _DEACT . For example, assuming that the activation potential V _ACT is a high potential (such as 5 volts), and the deactivation potential V _DEACT is a low potential (such as 0 volts), then when the word line W ₁ is activated, the potential on it is 5 volts. Volts; when the word line _W2 is deactivated, the potential on it is 0 volts. Alternatively, the activation potential V _ACT can be set to a low potential (such as 0 volts), and the non-activation potential V _DEACT can be set to a high potential (such as 5 volts), then when the word line W ₁ is activated, the potential on it is 0 volts ; When the word line _W2 is deactivated, the potential on it is 5 volts. A threshold potential V _TH is set between the activation potential V _ACT and the deactivation potential V _DEACT . When the potential on a word line falls between the activation potential V _ACT and the critical potential V _TH , the memory cell corresponding to the word line can be read/written by the corresponding bit line; otherwise, when a word line When the potential above falls between the non-activating potential V _ACT and the critical potential V _TH , the memory cell corresponding to the word line cannot be read/written by the corresponding bit line. Hereinafter, the activation potential V _ACT is set to 5 volts, the deactivation potential V _DEACT is 0 volts, and the threshold potential V _TH is 3 volts for convenience of description.

In step 201, the activated word line W ₁ represents that the potential on the word line W ₁ will be driven to 5 volts (V _ACT ), and the non-activated word line W ₂ represents that the potential on the word line W ₂ will be driven to 0 volts. (V _DEACT ).

In step 202, the word line _W1 is activated, and the memory cell _M11 can transmit the stored data _D1 to the controller 110 through the bit line _B1 .

In step 203, the controller 110 turns off the decoder 120 and the driver _P1 , so that the word line _W1 is in a floating state. Since the word line _W1 was activated and the word line _W2 was deactivated previously, the potentials on the word lines _W1 and _W2 are 5 and 0 volts, respectively. As mentioned above, the condition for the memory cell M ₁₁ to be read/written is that the potential on the word line W ₁ must be higher than 3 volts (threshold potential V _TH ). If there is an electrical connection path between the word line _W1 and _W2 , the potential on the word line _W1 will leak to the word line _W2 due to the electrical connection path, and gradually reduce the potential on the word line _W1 . . Therefore, in step 203, the purpose of suspending the word line _W1 for a period of time T _P is to determine whether there is an electrical connection path between the word lines _W1 and _W2 . In other words, if there is no electrical connection path between the word line _W1 and _W2 , then after step 203, the potential on the word line _W1 can still maintain 5 volts to allow the memory cell _M11 to read/write Writing: if there is an electrical connection path between the word lines _W1 and _W2 , after step 203, the potential on the word line _W1 will be reduced to such an extent that the memory cells cannot be read/written.

In step 204, the controller 110 turns on the driver P ₁ after the predetermined time T _P , and uses the complementary state of the data D ₁ as the data D ₂ , and writes the data D ₂ into the memory cell M through the bit line B _{1 11} in. That is, if the data _D1 is logic "1", then the data _D2 is logic "0"; if the data _D1 is logic "0", then the data _D2 is logic "1". Since the decoder 120 is still off at this time, the word line _W1 is not restarted (ie not re-driven to 5 volts). In this way, if there is an electrical connection path between the word lines _W1 and _W2 , the data _D2 cannot be written into the memory cell _M11 ; if there is no electrical connection path between the word lines _W1 and _W2 If the path is connected, the data D ₂ can be written into the memory cell M ₁₁ through the bit line B ₁ . More specifically, if there is an electrical connection path between the word lines _W1 and _W2 , after step 204, the data stored in the memory cell _M11 is still the previous data _D1 ; if the word lines _W1 and W2 There is no electrical connection path between ₂ , the data stored in the memory unit M ₁₁ becomes the data D ₂ .

In step 205 , the controller 110 turns on the decoder 120 and the driver P ₁ , and activates the word line W ₁ again, that is, in step 205 , the potential on the word line W ₁ is driven to 5 volts again. In this way, in step 206 , the controller 110 can read the data D ₃ stored in the memory unit M ₁₁ through the bit line B ₁ .

In step 207 , the controller 110 can compare the data D ₃ read in step 206 with the data D ₁ read in step 202 to determine whether there is an electrical connection path between the word lines W ₁ and W ₂ . More specifically, since in step 204, the controller 110 writes data D ₂ that is complementary to data D ₁ , therefore, if in step 204, data D ₂ is written successfully, then the data read in step 207 The output data D ₃ will be data D ₂ ; if in step 204 , the writing of data D ₂ fails, then the data D ₃ read in step 207 will be data D ₁ . In this way, the controller 110 can compare the data D ₃ and D ₁ to determine whether there is an electrical connection path between the word lines W ₁ and W ₂ . More specifically, if the data _D3 and _D1 are complementary, it means that the writing of the data _D2 in step 204 is successful, so the controller 110 can determine that there is no electrical connection between the word lines _W1 and _W2 . If the data D ₃ and D ₁ are of the same type, it means that the writing of the data D ₂ in step 204 failed, so the controller 110 can determine that there is an electrical connection between the word lines W ₁ and W ₂ path, and it is judged that the word line _W1 is defective.

To sum up, the word line defect detection device provided by the present invention can detect whether there is an electrical gap between adjacent word lines by suspending the word line for a period of time and then writing complementary data. The connecting path can effectively detect the defective word line, and provide greater convenience to the user.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (6)

1. A detection device for a word line defect, characterized in that it comprises: a first word line coupled to at least one memory cell; a second word line is disposed adjacent to the first word line; and A controller is coupled to the first word line and the second word line, the controller first activates the first word line to read a first data pre-stored in the memory unit, and then uses a For a predetermined time, make the first word line in a floating state, then write a second data complementary to the first data to the memory cell, and then the controller activates the first word line again to read from the memory cell A third data is taken out, and the third data is compared with the second data to determine whether there is an electrical connection path between the first word line and the second word line. 2. The detection device according to claim 1, wherein when the second data is different from the third data, the controller determines that the electrical connection path exists between the first word line and the second word line between two character lines. 3. The detection device according to claim 1, wherein the controller comprises: A first driver, corresponding to the first word line and a decoder, the decoder is coupled to the first word line and the second word line, the controller turns off the first driver and the decoder so that The first word line is in a floating state, and the controller turns on the first driver to write the second data into the memory unit when the decoder is turned off. 4. A method for detecting a word line defect, wherein a memory cell is coupled to a first word line and a second word line adjacent to the first word line, the method comprising: (a) enabling the first word line to read a first data pre-stored in the memory cell; (b) keeping the first word line in a floating state for a predetermined time, and then writing a second data complementary to the first data to the memory cell; (c) reactivating the first word line to read a third data from the memory cell; and (d) comparing the second data and the third data to determine whether there is an electrical connection path between the first word line and the second word line. 5. The method according to claim 4, wherein when the second data is different from the third data, it is determined that the electrical connection path exists between the first word line and the second word line . 6. The method according to claim 4, wherein a first driver corresponds to the first word line and a decoder is coupled to the first word line and the second word line, the step (b) Include: (b1) turning off the first driver and the decoder so that the first word line is in a floating state; and (b2) When the decoder is turned off, turn on the first driver to write the second data into the storage unit.

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