CN101281786B - Method and related apparatus for detecting breakage of character wire in memory array - Google Patents
Method and related apparatus for detecting breakage of character wire in memory array Download PDFInfo
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- CN101281786B CN101281786B CN2008100818490A CN200810081849A CN101281786B CN 101281786 B CN101281786 B CN 101281786B CN 2008100818490 A CN2008100818490 A CN 2008100818490A CN 200810081849 A CN200810081849 A CN 200810081849A CN 101281786 B CN101281786 B CN 101281786B
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Abstract
The present invention provides a method for detecting damaged character lines in a memory array, which comprises the following steps: writing first data into the corresponding memory unit, when a character line is coupled to a bias voltage source; writing second data different to the first data into the memory unit when the character line is decoupled from the bias voltage source; reading the data stored in the memory unit, and judging whether the character line is damaged or not according to the data read from the memory unit, the first data, and the second data. The device for detecting damaged character lines in a memory array comprises a first writing unit, a second writing unit, a reading unit, and a judging unit. The method and device for detecting damaged character lines in a DRAM memory array can help the user to detect whether there is short circuit among the character lines.
Description
Technical field
The present invention is relevant a kind of method and relevant apparatus that the character line loss is bad in the storage array of detecting, and more particularly, is relevant a kind of method and relevant apparatus that the character line loss is bad in the dynamic random access memory array of detecting.
Background technology
Please refer to Fig. 1, Fig. 1 is a dynamic RAM (Dynamic Random AccessMemory, DRAM) synoptic diagram of array 100; As shown in the figure, dynamic random access memory array 100 comprises character line (word line) WL1, WL2 and WL3, bit line (bit line) BL1, BL2 and BL3, switch SW 11, SW12, SW21, SW22, SW31 and SW32, and storage unit M11, M12, M21, M22, M31 and M32.When user's desire write a data in one storage unit, the current potential of character line will be promoted to a noble potential VH with the pairing switch opens of this storage unit, is written into the data of desiring to write again on the bit line of correspondence, so just data can be write.For instance, when user's desire with a data " 1 " during write storage unit M22, then the current potential of character line WL2 can be promoted to current potential VH so that switch SW 22 is opened, and makes storage unit M22 and bit line BL2 conducting, then just can be with data " 1 " write storage unit M22.Otherwise if data will not write, then the current potential on the character line can remain in an electronegative potential VL, and makes the switch of its corresponding storage unit all present closed condition.As shown in the figure, when user's desire during with data write storage unit M22, the current potential that has only character line WL2 is noble potential VH (meaning promptly has only switch SW 21, SW22 to be opened), and the current potential of all the other storage unit that is not written into pairing character line WL1 and WL3 is all electronegative potential VL.
And in the manufacture process of dynamic random access memory array, have impurity molecule unavoidably and exist.And impurity molecule can cause the short circuit between character line and the character line, and makes and to be caused the character line of short circuit can not reach desired current potential, and then pairing storage unit can't be stored data.As shown in Figure 1, impurity molecule P is present between character line WL1 and the WL2, causes character line WL1 and WL2 short circuit.Therefore, when the user desired to write character line WL1 or the pairing storage unit of WL2, the short circuit that will be caused because of impurity molecule P made to write failure.For instance, when the user desired to write data in storage unit M22, the current potential of character line WL2 can be promoted to noble potential VH, and all the other character line WL1, WL3 will be maintained at electronegative potential VL.Because impurity molecule P is with character line WL2 and WL1 short circuit, therefore just having leakage current flows to character line WL1 from character line WL2, and makes the current potential of character line WL2 descend gradually from current potential VH originally.
Please refer to Fig. 2, Fig. 2 is the synoptic diagram for the voltage on the description character line WL2; As shown in the figure, (when not having impurity molecule P to exist) in the ideal case, character line WL2 can be promoted to noble potential VH a period of time T1 (shown in dotted portion).And in fact owing to the influence of impurity molecule P, the current potential VH of character line WL2 is drop-down by the electronegative potential VL of character line WL1 gradually.When the current potential of character line WL2 dropped to critical potential VB, if this moment, write activity was not finished as yet, then switch SW 22 will be closed and data write storage unit M22 can't be caused to write failure.As shown in the figure, (be promoted to noble potential VH) after character line WL2 is activated, if behind the elapsed time T2, write activity is not finished as yet, then the current potential on the character line WL2 will drop to critical potential VB-and switch SW 21, SW22 are closed.Thus, the pairing storage unit of character line WL2 (storage unit M21 as shown, M22), its stored data just may produce mistake.And the user also can read wrong data when using such storage unit, causes user's inconvenience.
Summary of the invention
The object of the present invention is to provide a kind of method and apparatus that DRAM is detected in earlier stage of being used for, whether working properly with each character line in the detection of stored device, the storage errors of avoiding the damage owing to the character line to cause influence the user to the storage of data with read.
The invention provides the bad method of character line loss in a kind of detecting one storage array.Wherein, this storage array comprises the storage unit of a plurality of character lines and a plurality of correspondences.These a plurality of character lines comprise one first character line and a plurality of second character lines.The method includes the steps of: when this first character line is coupled to one first bias generator, pairing one first storage unit of this first character line is write one first data; This first character line and this first bias generator couple disconnection after, this first storage unit is write one second data that is different from this first data; Read the stored data of this first storage unit; And read data according to this and judge whether this first character line damages.
The present invention provides the bad arrangement for detecting of character line loss in a kind of storage array in addition.Wherein, this storage array comprises the storage unit of a plurality of character lines and a plurality of correspondences, and these a plurality of character lines comprise one first character line and a plurality of second character lines.This arrangement for detecting comprises one first writing unit, is used for when this first character line is coupled to one first bias generator, and pairing one first storage unit of this first character line is write one first data; One second writing unit, be used in this first character line and this first bias generator couple disconnection after, this first storage unit is write one second data that is different from this first data; One reading unit is used for reading the stored data of this first storage unit; And a judging unit, be used for reading data and judge whether this first character line damages according to this.
Bad method for detecting and the arrangement for detecting of character line loss in the dynamic random access memory memory array provided by the present invention, can allow the user detect which character line has by the situation of other character line short circuits.Not only allow the user avoid using and damage the storage unit that the character line is corresponded to, also can allow the user know that employed dynamic random access memory memory array diminishes the situation of batter unit line, and replaceable other good dynamic random access memory memory arrays provide the user convenience bigger to the dynamic random access memory memory array.
Description of drawings
Fig. 1 is the synoptic diagram for dynamic random access memory array;
Fig. 2 is the synoptic diagram for the voltage on the character line;
Fig. 3 is the bad method flow diagram of character line loss in the detecting dynamic random access memory array provided by the present invention;
Fig. 4 is a synoptic diagram of detecting the arrangement for detecting that the character line loss is bad in the storage array for the present invention.
Description of reference numerals:
100-dynamic random access memory memory array; The SW-switch; BL-bit line; WL-character line; The M-storage unit; The P-impurity molecule; VL, VH, VB-voltage; T1, T-2, TP-time; The 300-method; 301～306-step; VDD, VSS-bias generator; The 400-arrangement for detecting; 401,402-writing unit; The 403-reading unit; The 404-judging unit.
Embodiment
Therefore, the invention provides the bad method for detecting of character line loss in a kind of dynamic random access memory memory array, can allow the user detect which character line has by the situation of other character line short circuits.Can allow on the one hand the user avoid using and damage the storage unit that the character line is corresponded to, also can allow the user know that employed dynamic random access memory memory array diminishes the situation of batter unit line and replaceable other good dynamic random access memory memory arrays on the other hand.
Please refer to Fig. 3, and simultaneously with reference to figure 1; Fig. 3 is the process flow diagram for the method 300 that the character line loss is bad in the detecting dynamic random access memory memory array provided by the present invention; And whether the flow process of Fig. 3 is to damage and come judgment mode to carry out with the stored data of detecting storage unit M22 with the character line WL2 of detecting among Fig. 1.Detecting in the mode of the memory model of Fig. 1 is to be a demonstration example for convenience of description and only.Anyly all belong to category of the present invention with the spiritual identical method for detecting of method for detecting 300.The step of method for detecting 300 is described as follows:
Step 301: beginning;
Step 302: start character line WL2, and when starting character line WL2, storage unit M22 is write a data D1;
Step 303: start character line WL2 once again, and after starting character line WL2, just storage unit M22 is write the data D2 that is different from data D1;
Step 304: the data that reading cells M22 is stored;
Step 305:, judge whether character line WL2 damages according to the data that is read from storage unit M22;
Step 306: finish.
In step 302 and 303, data D1 and D2 are required to be different.For instance, if data D1 is " 1 " time, then data D2 just is " 0 ".Otherwise, if data D1 is " and 0 " time, then data D2 just is " 1 ".Below with data D1 be " 1 ", D2 for " 0 " be the demonstration example explanation.
In step 302, start character line WL2 and be promoted to current potential VH for current potential with character line WL2.And the method that the current potential of character line WL2 is promoted to current potential VH be can be character line WL2 is coupled to a bias generator with noble potential VH, so the current potential of character line WL2 just can be promoted to noble potential VH, and this moment, pairing switch SW 21, SW22 will be opened, again with data D1 " 1 " be written into bit line BL2.Thus, data D1 " 1 " just can be stored to storage unit M22.
In step 303, start character line WL2 and be promoted to current potential VH for current potential with character line WL2.And the method that the current potential of character line WL2 is promoted to current potential VH be can be character line WL2 is coupled to a bias generator with noble potential VH, so the current potential of character line WL2 just can be promoted to noble potential VH, and pairing switch SW 21, SW22 will be opened at this moment.And the difference of step 303 and step 302 is: after character line WL2 is started, step 303 can be with the couple disconnection of character line WL2 with the bias generator with noble potential VH, after a schedule time TP, again with data D2 " 0 " be written into bit line BL2.In other words, step 303 is for the current potential with character line WL2 is increased to after the current potential VH, makes character line WL2 present the state of unsteady (floating) again, rather than the current potential on the character line WL2 is fixed on noble potential VH.In addition, it should be noted that schedule time TP needs greater than time T B.Because except character line WL2 goes up current potential is the noble potential VH, the current potential on all the other character line WL1, WL3 is all electronegative potential VL.Therefore, when having impurity molecule P to exist in the middle of character line WL2 and character line WL1 or the WL3, after process schedule time TP, the current potential on the character line WL2 will drop to subcritical current potential VB gradually, and makes pairing switch SW 21, SW22 close.Afterwards again with data D2 " 0 " when being written into bit line BL2, just can't be with data D2 " 0 " write storage unit M22.Otherwise when all not having impurity molecule P to exist in the middle of character line WL2 and character line WL1 or the WL3, after process schedule time TP, the current potential on the character line WL2 will still can keep noble potential VH, and makes pairing switch SW 21, SW22 continue to open.Afterwards again with data D2 " 0 " when being written into bit line BL2, just can be with data D2 " 0 " write storage unit M22.
Therefore, according to step 302 and 303, in step 304, just can the data that storage unit M22 is stored read out.If the data that reads out for " 0 ", but then determining step 303 with data D2 " 0 " the action success of write storage unit M22, expression character line WL2 does not have any and short circuits other character lines.Otherwise, if the data that reads out is " 1 ", but determining step 303 data D2 then " 0 " baulk of write storage unit M22, and the storage unit M22 data D1 that write of storing step 302 only " 1 ", that is to say between character line WL2 and other character lines has impurity molecule to cause the situation of short circuit.Therefore, the data of reading according to step 304 is 0 or 1, in step 305, can judge just whether character line WL2 has damage.
In addition, method for detecting of the present invention also can be carried out at many bit lines simultaneously.For instance, in step 302, can be with data D1 " 1 " write storage unit M21, M22 simultaneously.In step 303, can be with data D2 " 0 " write storage unit M21, M22 simultaneously.In step 304, if the data of reading is " 11 ", represent that then bit line WL2 damages; Otherwise, if the data of reading is " and 00 ", represent that then bit line WL2 does not damage.
Please refer to Fig. 4, Fig. 4 is a synoptic diagram of detecting the arrangement for detecting 400 that the character line loss is bad in the storage array for the present invention; As shown in the figure, arrangement for detecting 400 comprises writing unit 401,402, reading unit 403, judging unit 404, one high bias generator VDD and a low bias generator VSS.High bias generator VDD is used to provide current potential VH, low bias generator VSS is used to provide current potential VL.Bias generator VSS is coupled to all the other character line WL1, WL3... etc.Writing unit 401 is used for when character line WL2 is coupled to bias generator VDD storage unit M22 being write data D1 " 1 ".Writing unit 402 be used for character line WL2 and bias generator VDD couple disconnection after, via a schedule time TP, just storage unit M22 is write data D2 " 0 ".Reading unit 403 is used for the stored data of reading cells M22.Judging unit 404 be used for judging data that reading unit 403 reads for " 0 " or " 1 ", and compare with data D1 and D2, whether damage to judge character line WL2.Thus, via arrangement for detecting 400 of the present invention, which character line loss just can judge has bad in the random access memory memory array, and the user is provided more information about employed memory array.
In sum, bad method for detecting and the arrangement for detecting of character line loss in the dynamic random access memory memory array provided by the present invention, can allow the user detect which character line has by the situation of other character line short circuits.Not only allow the user avoid using and damage the storage unit that the character line is corresponded to, also can allow the user know that employed dynamic random access memory memory array diminishes the situation of batter unit line, and replaceable other good dynamic random access memory memory arrays provide the user convenience bigger to the dynamic random access memory memory array.
Above embodiment only is preferred embodiment of the present invention, and it is illustrative for the purpose of the present invention, and nonrestrictive.Those skilled in the art carries out conversion, modification even equivalence to it under the situation that does not exceed spirit and scope of the invention, these changes all can fall into claim protection domain of the present invention.
Claims (8)
1. detect the bad method of character line loss in the storage array for one kind, wherein this storage array comprises the storage unit of a plurality of character lines and a plurality of correspondences, these a plurality of character lines comprise one first character line and a plurality of second character lines, said method comprising the steps of:
Start this first character line, this first character line is coupled to one first bias generator, meanwhile, pairing one first storage unit of this first character line is write one first data;
Start this first character line once again, the disconnection that couples with this first character line and this first bias generator, after a schedule time TP, this first storage unit is write one second data that is different from this first data, wherein, schedule time TP satisfies: when in the middle of the character line impurity being arranged, behind schedule time TP, the current potential on the character line drops to the subcritical current potential;
Read the stored data of this first storage unit; And
Read data according to this and judge whether this first character line damages.
2. method according to claim 1 is characterized in that, this reads described basis in the step that data judges whether this first character line damage, and when this reads data when identical with this first data, judges that this first character line damages.
3. method according to claim 1 is characterized in that, this reads described basis in the step that data judges whether this first character line damage, and when this reads data when identical with this second data, judges that this first character line does not damage.
4. method according to claim 1 is characterized in that, described first bias generator is the bias generator with noble potential, and described method also comprises these a plurality of second character line is coupled to a low bias generator that is different from this bias generator with noble potential.
5. the bad arrangement for detecting of character line loss in the storage array, this storage array comprises the storage unit of a plurality of character lines and a plurality of correspondences, and these a plurality of character lines comprise one first character line and a plurality of second character lines, and this arrangement for detecting comprises:
One first writing unit is used for when this first character line is coupled to one first bias generator, and pairing first storage unit of this first character line is write one first data;
One second writing unit, be used for this first character line and this first bias generator couple disconnection after, and via after the schedule time TP, this first storage unit is write one second data that is different from this first data, wherein, schedule time TP satisfies: when in the middle of the character line impurity being arranged, behind schedule time TP, the current potential on the character line drops to the subcritical current potential;
One reading unit is used for reading the stored data of this first storage unit; And
One judging unit is used for reading data according to this and judges whether this first character line damages.
6. arrangement for detecting according to claim 5 is characterized in that, when this reads data when identical with this first data, this first character line of this judgment unit judges damages.
7. arrangement for detecting according to claim 5 is characterized in that, when this reads data when identical with this second data, this first character line of this judgment unit judges does not damage.
8. arrangement for detecting according to claim 5, it is characterized in that, described first bias generator is the bias generator with noble potential, and described device also comprises a low bias generator that is different from this bias generator with noble potential, is used for being coupled to this a plurality of second character line.
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| CN2008100818490A CN101281786B (en) | 2008-05-08 | 2008-05-08 | Method and related apparatus for detecting breakage of character wire in memory array |
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| CN2008100818490A CN101281786B (en) | 2008-05-08 | 2008-05-08 | Method and related apparatus for detecting breakage of character wire in memory array |
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| US10714197B1 (en) * | 2019-04-18 | 2020-07-14 | Macronix International Co., Ltd. | Memory device and program verification method thereof |
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Granted publication date: 20100818 Termination date: 20180508 |