CN101873002B - Distributed integration oscillograph mother board and parallel bus structure - Google Patents

Abstract

The invention discloses a distributed integration oscillograph mother board and a parallel bus structure, belonging to a dynamic oscillographing device system. The mother board is a common active mother board, is provided with a large-scale integrated circuit chip, a control circuit and a sub oscillograph bus slot, and integrates a set of parallel buses which are controlled by corresponding control circuits. The parallel buses include a clock bus, a control bus, a state bus, a timing bus and a reset bus; the control circuits include an automatic detection and signal switching control circuit, a calculation control synchronous circuit, an oscillograph synchronous control circuit, a queue synchronous control circuit, a timing signal processing circuit and a system resetting circuit; and the clock bus is also connected with a clock automatic switching circuit of each sub oscillograph. An RS485 network, an RS422 network and an SPI synchronous series network with priority token rings are integrated on the mother board which is provided with an expending slot so as to form an expending system. By combining the distribution and the integration, the invention realizes strict synchronization of the oscillographs and has the advantages of high reliability, high system capacitance, favorable expandability, wide data transmission communication bands, distributed storage of files and convenient calculation and retrieval.

Description

Distributed integration oscillograph mother board and parallel bus structure

Affiliated technical field

The invention belongs to computer application field, relate to the dynamically big capacity wave recording device of high speed measurement-recording system, particularly parallel distributed of Computer Processing.

Background technology

Dynamically wave recording device is a kind of digitized high speed surveying record instrument.This instrument can carry out continual high-speed synchronous tracking sampling to a plurality of fast-changing coherent signal that the outside is inserted and detect; With the generation of condition of instant error, sudden change or certain particular event of catching signal to be detected, on request all correlation signals are carried out the Real-time and Dynamic record then and analyze.Because this instrument can be followed the tracks of for a long time multiparameter system and detect and record, and catch and find the fault of system to be detected or unusual automatically, so, got widely in electric power system especially and use in scientific research and each field of national economy.Present employed traditional oscillograph adopts principal and subordinate, centralized system configuration more.This system configuration is simple, realizes easily, but owing to receive the restriction of system configuration, inevitable deficiency is arranged:

1, poor reliability.Because what adopt is a kind of concentrated but not structure of distributing, risk is very concentrated, in case background computer breaks down, whole system can't operate as normal.

2, overall performance receives the restriction of system configuration and background computer performance.It at first is the restriction of power system capacity.Increase when measuring port number, when data traffic was increased to a certain degree, the communication between forward and backward machine was owing to the restriction of the bandwidth obstruction that becomes.Next is that the computing capability of separate unit background computer is limited.When data volume is increased to certain degree, single computer can't be accomplished the task of real-time calculating and record ripple.The 3rd is that data remote is influenced by bandwidth.Because all recorder datas all are to send local work station or far-end server to through background computer, so when data volume is too big, also can receive the influence of the network bandwidth.

Change above-mentioned deficiency, essential method is that original principal and subordinate, centralized structural change are parallel, distributed frame, promptly so-called distribution oscillograph device.And each sub-oscillograph works alone fully in the distribution oscillograph device; Except sampling and transfer of data; It calculates with recording ripple also is independently to be accomplished separately by each sub-oscillograph; Therefore, the strict synchronism that how each sub-oscillograph calculates with the record ripple in the assurance device is the problem that system design need be considered.And adopt public motherboard and parallel bus, and then be both to have made things convenient for compartment system integrated, guarantee the key technology of data sync simultaneously again.

Summary of the invention

The purpose of this invention is to provide a kind of motherboard and parallel bus structure; So that a plurality of sub-oscillographs can be realized installing concentratedly of modular when integrated distribution wave recording device; And through being integrated in the parallel bus on the active motherboard; Make each independent, the sub-oscillograph of concurrent working guarantees the strict synchronism of calculated data and the time precise marking of record data when accomplishing Distribution calculation and distributing the record ripple.

" can through the veneer wave recorder of parallel bus integrated distribution system " and " based on the method for synchronous of distributed-type integrated recorder parallel buses " that the present invention and the applicant apply for simultaneously constitute complete distributed-type integrated recorder system configuration and method jointly.

The objective of the invention is to reach like this: the shared motherboard of each sub-oscillograph is active motherboard in the integrated wave recording device that distributes.On motherboard, be equipped with in order to the large scale integrated chip of realizing complicated control logic and the bus slot of pegging graft sub-oscillograph and supervisor, simultaneously an also integrated cover is with the parallel bus of control logic on the motherboard.Also be provided with the parallel bus suitable on each sub-oscillograph in the device with motherboard.During work, each sub-oscillograph is plugged on the motherboard through bus plug correspondence successively, and with motherboard bus UNICOM.Bus, reset bus and power line when integrated parallel bus comprises clock bus, control bus, status bus, school on the said motherboard.Said control circuit comprises house dog Auto-Sensing and control signal commutation circuit, calculates synchronization control circuit, records ripple synchronization control circuit, formation synchronization control circuit, correcting delay signal treatment circuit and system reset circuit.Said control bus has 7, and status bus has 6.Wherein, The calculation control line is with computing mode line, formation train line and quene state line, record ripple control line and record the ripple condition line, record value control line is corresponding one by one with the token status line with record state of value line, definite value control line and definite value condition line and Token Control line, and all the other control buss are house dog control lines.2 signal line during when bus comprises the internal clock school during said school and external clock school.

Each sub-oscillograph bus slot all has own corresponding house dog Auto-Sensing and control signal commutation circuit on the motherboard, and the Auto-Sensing of each slot and commutation circuit structure are identical, and the house dog control line is connected to house dog Auto-Sensing and commutation circuit.Record ripple synchronization control circuit is made up of record ripple, record value and 3 kinds of circuit of definite value control jointly.Synchronously calculating control circuit by or door and d type flip flop form.Record value, record involve the definite value control circuit by or door and d type flip flop form.The formation synchronization control circuit is by selecting preferential automatic switchover link that 1 variable connector constituted with sub-oscillograph corresponding 2 and forming with door.Reset circuit divides two parts, and wherein a part is on sub-oscillograph, and another part is on motherboard.Circuit also divides two parts during the school, and wherein a part is on sub-oscillograph, and another part is on motherboard.Integrated several kinds of communication networks comprise communication network bus and correspondent control circuits on the motherboard; Wherein, looped network RS485 has priority token rings control.Motherboard is provided with the bus expansion slot, and N motherboard connects and composes the expanding system that N motherboard formed through the bus expansion cable.

The large scale integrated chip of installing on the said motherboard is that model is LC4512 at system programmable (In System Programmable is called for short ISP) CPLD device; Said sub-oscillograph bus slot has totally 8 of 0#-7#, and corresponding integrated sub-oscillograph has totally 8 of 0#-7#.Said systematic manager bus slot has 1, can connect an embedded management computer.

Said clock bus is meant a cover synchronised clock that is obtained by generation of same 4M crystal oscillator source and the frequency dividing circuit in motherboard ISP, is called system clock; In the ISP of sub-oscillograph, also adopt the synchronised clock that has produced a cover oneself in the same way simultaneously, be called local clock; System clock and local clock are incorporated into the input of firing the automatic switch-over circuit in sub-oscillograph ISP simultaneously; After the switching output through sub-oscillograph automatic switch-over circuit; Handle through pulsewidth shaping circuit and delay circuit again, finally be sent to the sample circuit of sub-oscillograph and the interruption input pin of digital signal processor DSP and microprocessor ARM.

Said system clock and local clock have 10KHz, 20mS, 100mS and 1S totally 4 tunnel clock signals respectively; Wherein, the 10KHz signal is as data latching and sample-synchronous signal; The 20mS pulse is as transfer of data synchronizing signal and the calculating segment sync of DSP to ARM; The 100mS clock is as calculating synchronously and the synchronous reference signal of formation; The 1S clock is synchronous and time synchronized reference signal as formation.Said system clock and local clock are incorporated into the input of automatic switch-over circuit simultaneously; 4 road signals that are meant system clock by received respectively 2 select 1 variable connector V74158 A0, B0, C0, D0 end; 4 road signals of local clock are received same 2 respectively and are selected A1, B1, C1, the D1 of 1 variable connector to hold; Local 10KHz signal is also received the counting end of the counter V74162 of automatic switch-over circuit simultaneously, and system 10KHz signal is received the clear terminal of same counter V74162.

2 signal line during when bus comprises the internal clock school during said school and external clock school.The internal clock correcting delay signal is from the branch or the pulse per second (PPS) output of the minimum sub-oscillograph calendar clock of numbering in the system; The external clock correcting delay signal is the GPS correcting delay signal, from the branch or the pulse per second (PPS) output of external GPS synchronised clock; Pulse control circuit when these two kinds of correcting delay signals are input to the school of firing in sub-oscillograph ISP is simultaneously selected to switch benchmark during as sub-oscillograph data markers and calendar clock school by sub-oscillograph automatically.

House dog Auto-Sensing and commutation circuit be by the signal leading edge detecting circuit, counter, and the R-S trigger, variable connector and failure indicating circuit constitute.Auto-Sensing and commutation circuit with the 0# groove are explained: 0U1,0U2,0U6 and 0U7 constitute the signal leading edge detecting circuit; 0U3 is a counter; 0U5 and 0U12 are the R-S trigger, and 0U4 8 the tunnel 2 selects 1 variable connector, and 0U12,0U13 and 0U14 constitute 0# groove failure indicating circuit.

Said calculating synchronization control circuit is meant from the calculating train line of each sub-oscillograph and condition line and is connected to the calculating synchronization control circuit of firing in motherboard ISP through bus plug; Wherein control line is at first through behind the pairing automatic switch-over circuit of each groove, connects by the mode of logical "or"; Calculate synchronization control circuit by or door 9U1 and d type flip flop 9U7 constitute; The input of 9U1 is promptly from the calculation control line behind each sub-oscillograph slot process automatic switch-over circuit; Its output is connected to the D end of d type flip flop 9U7, and the Q end output of d type flip flop 9U7 then is connected to the computing mode line of each sub-oscillograph slot.

Said record ripple synchronization control circuit is meant record value control line and condition line from each sub-oscillograph; Record ripple control line and condition line and definite value control line and condition line are connected respectively to record value synchronization control circuit, record ripple synchronization control circuit and the definite value synchronization control circuit fired in motherboard ISP through bus plug; Wherein 3 kinds of control lines divide into groups to connect by the mode of logical "or" at first through behind the pairing automatic switch-over circuit of each groove then.Record value, record involve the definite value control circuit by or door and d type flip flop form, wherein, the record duty control circuit by or door 9U2 and d type flip flop 9U8 form; Record ripple control circuit by or door 9U3 and d type flip flop 9U9 form; The definite value control circuit by or door 9U4 and d type flip flop 9U10 form.The input of 9U2,9U3 and 9U4 is promptly respectively from record value control line, record ripple control line and definite value control line behind each sub-oscillograph slot process automatic switch-over circuit; Its output is connected to the D end of d type flip flop 9U8,9U9 and 9U10 respectively, and the output Q end of d type flip flop then is connected to record state of value line, record ripple condition line and the definite value condition line of each sub-oscillograph slot respectively.

Said formation synchronization control circuit is formed by reaching with a door 9U6 with corresponding 8 the 2 preferential automatic switchover links that select 1 variable connector 0U11-7U11 to be constituted of sub-oscillograph; Wherein the A input of each variable connector all is connected to sub-oscillograph slot through the formation train line behind the automatic switch-over circuit; The B input then is connected to the output Z of the pairing variable connector of next slot; The output Z of 0 groove variable connector 0U11 receives and a door 9U6, then is connected to the formation synchronous regime line of each sub-oscillograph slot respectively with the output of door 9U6.Variable connector receives the control of S end, S=0, variable connector output Z tangential A; Otherwise Z tangential B.

Circuit is divided into two parts during said system school, part design on sub-oscillograph, pulse control circuit when comprising the calendar clock chip of sub-oscillograph self and firing split-second precision marking circuit and the school in ISP; Another part then designs on motherboard, comprises outside input pulse isolated variable circuit and the pulsewidth shaping circuit among the motherboard ISP on the motherboard, and this two signal line of pulse bus when bus and GPS school when being integrated in the system school on the motherboard.Pulse control circuit during sub-oscillograph is delivered in pulse output and the branch or the pulse per second (PPS) output of external GPS synchronised clock simultaneously during from the branch of sub-oscillograph calendar clock or second school school; Automatically select to switch benchmark during as sub-oscillograph data markers and calendar clock school by sub-oscillograph.In addition, an also integrated RS232 receives bus on the motherboard, and the RS232 serial ports of all sub-oscillographs all can be connected on the motherboard RS232 bus through slot in the device, receives the absolute time data from external equipment (GPS).

Said system reset circuit is divided into two parts, and a part of design realizes by the ISP on the sub-oscillograph on sub-oscillograph, and its function comprises that electrification reset, software watchdog reset, hardware watchdog resets, power failure resets and unit hand-reset etc.; The reset signal of sub-oscillograph output is also delivered on the motherboard reset bus through the 27C pin of bus plug simultaneously, is used for blocking in the reseting procedure corresponding sub-oscillograph Auto-Sensing and exports with the neutral signal of commutation circuit.Another part of reset circuit then designs on motherboard, by the ISP realization of motherboard; Its function comprises that the multimachine manual synchronization resets and supervisor or far-end reset (software reset).Multimachine manual synchronization reset circuit is by general reset button (S1), and reverse swing door (SU1), NOR gate (SU3), d type flip flop (SU4), (SU6), reverse swing door (SU5) reach with the pulse front edge differential circuit of door (SU7) composition and with door (SU8), NOR gate (SU10) and constitute; The pulse of SU10 output is connected on the motherboard reset bus, then the triple gate 0U16-7U16 output that resets of each groove of process respectively; This signal is connected on the reset signal pin of each sub-oscillograph through the 27C of each groove bus plug pin, and completion resets; Supervisor resets or far-end resets is through software control; By exterior I/O input pulse; Through SU2, SU3 among the motherboard ISP and the pulse front edge differential circuit of forming by SU4-SU7; Through SU9, SU10 output, respectively through the triple gate 0U16-7U16 output that resets of each groove, each sub-oscillograph resets at last again.

Integrated multiple communication network is meant RS485 network, RS422 network and SPI synchronous serial network on the said motherboard.

The RS485 net is a looped network, mainly is used for transmission and receiving time information between each sub-oscillograph, record ripple file file label, various control command and other shared data.RS485 network with priority token rings is like this design: in the system RS485 serial ports of all sub-oscillographs all the bus plug through separately be connected on the motherboard and realize interconnected through the RS485 bus on the motherboard; The RS485 port of wherein every estrade oscillograph all is a network node that receives Token Control in the network; Whenever the all-network node all can receive information; But have only a node can send information with token; Whenever, network node can obtain token through application, and groove number less node then can preferentially obtain token.The RS485 net is fired the control of the priority token rings control circuit in motherboard ISP.The Token Control circuit is made up of the Token Control door 0U10-7U10 that is connected in series and the token status detecting gate 0U15-7U15 that is connected in parallel and reverse swing door MU21; An input of each control gate is connected to the Token Control end behind the corresponding slot process automatic switch-over circuit on the motherboard, and another input then links to each other with the output of previous control gate; This port is also connected to an input of each slot corresponding token state-detection door simultaneously, and another input of token status detecting gate is then from the output of token status feedback door MU21.Cooperate token ring control, every estrade oscillograph has used 3 control ports, and wherein the ROW3 port of ARM is used to export the Token Control signal, and the ROW1 port is used to export the RS485 transmission and enables control signal, and the EGPIO8 port is used to receive the token status signal.

The RS422 net is principal and subordinate's net, mainly is used for sending the Debugging message and the error message of each sub-oscillograph.In the system RS422 serial ports of all sub-oscillographs all the bus plug through separately be connected with RS422 bus on the motherboard; Whenever these serial ports all are in the reception enabled, can receive the operational order from supervisor; But have only one to be in the transmission enabled, can send Debugging message or the error message of self to supervisor.Specifically be that the RS422 serial ports of which estrade oscillograph is in and sends enabled and controlled by the RS422 output control circuit.Output control circuit by supervisor I/O mouth, be installed in toggle switch and the decoder 74LS138 (MU17) that fire among motherboard ISPs of expansion on the panel and form; Wherein the output of supervisor I/O or panel toggle switch is connected to decoder input A0, A1, A2; The transmission that 8 outputs of decoder then are connected to the sub-oscillograph RS422 of 0#-7# mouth through bus plug respectively enables control end.During work,, can select to enable the RS422 transmit port of any estrade oscillograph through supervisor or panel toggle switch output encoder number.

SPI synchronous serial net is divided into Intranet and outer net; Intranet is integrated on each sub-oscillograph, mainly communicates by letter with the bidirectional high speed between the time mark high speed timing circuit with calendar clock and ARM with DSP, ARM as ARM; At this moment ARM decides, DSP, calendar clock or high speed timing circuit do from; Outer net then is integrated on the motherboard, and mainly as the bidirectional high speed communication between the sub-oscillograph, at this moment 0# oscillograph is decided, the sub-oscillograph of 1#-7# do from; Specifically be to select Intranet or outer net, and when selecting Intranet be select that from subtend then by the SPI decoder V74139 control of firing among sub-oscillograph ISP.

Also be provided with expansion slot on the said motherboard; The expansion slot of N motherboard couples together by daisy chaining through the bus expansion cable; And, just can constitute the expanding system that N motherboard formed being arranged in the terminating plug of pegging graft on the terminal expansion cable plug.

Record ripple, record value, definite value expand to calculation control line and corresponding state line: separately 8 the importing or be connected through expansion cable of 8 record ripple control lines, record value control line, definite value control line and calculation control lines on N motherboard; Synthesize respectively separately 8xN input or door; Or the output of door is connected to the D end of the corresponding control circuit d type flip flop of terminal motherboard; The output Q of d type flip flop holds then and is connected respectively to N motherboard record ripple condition line, record state of value line, definite value condition line and computing mode line separately through expansion cable, has so just formed one and can realize that 8xN estrade oscillograph calculates synchronously and the distribution record wave system system of synchronous record ripple.

The extended method of the synchronously preferential chain of formation can be explained with the expanding system with No. 0 and No. 1 two motherboards.During expansion, the output of the synchronously preferential chain of No. 0 slot formation of No. 1 motherboard is connected to the B input of No. 7 synchronous commutation circuit 7U11 of slot formation of No. 0 motherboard through expansion cable; The output of No. 0 synchronous commutation circuit 0U11 of slot formation of No. 0 motherboard then is connected to the formation synchronous regime line of No. 1 motherboard through expansion cable; The formation synchronous regime line of No. 1 motherboard is connected to the formation synchronous regime line of No. 0 motherboard through expansion cable simultaneously.Thereby the formation Synchronization Control chain of two motherboards is linked, form the preferential chain of an integral body.So having the system of 16 sub-oscillographs during operate as normal will be benchmark with the formation control line of No. 0 motherboard 0 work song oscillograph.And if No. 0 slot of No. 0 motherboard is not pegged graft sub-oscillograph or the sub-oscillograph of being pegged graft quits work for some reason, then system will be a benchmark with the formation control line of No. 0 motherboard 1 work song oscillograph.The rest may be inferred.This shows that in the 16 slot systems that form through expansion, No. 0 slot of No. 0 motherboard has the highest priority level.No. 7 slots of No. 1 motherboard then have minimum priority level.

The extended method of RS485 net and priority token rings can be explained with the expanding system with No. 0 and No. 1 two motherboards.During expansion, at first each motherboard RS485 looped network bus separately is communicated with through expansion cable.As for Token Control; Can the output of No. 7 slot token rings of No. 0 motherboard be connected to the input of No. 1 motherboard No. 0 slot token ring circuit 0U15 and 0U10 through expansion cable; The output of No. 7 slot token rings of No. 1 motherboard then is shorted to 12 pin through terminating plug 11 pin; Connect with the token status line of two motherboards then, thereby the token ring of two motherboards is linked, the token that forms an integral body preferentially encircles.So have during operate as normal in the system of 16 sub-oscillographs, for the highest, the token priority level of No. 1 motherboard 7 work song oscillographs is minimum with the token priority level of No. 0 motherboard 0 work song oscillograph.

The extended method of system synchronization clock is: connect through expansion cable, N motherboard clock bus separately is connected.At this moment in the system clock of each motherboard by decapacitation; Can not clock signal; Have only last motherboard that is plugged with terminating plug to be shorted to high level by the jumper in the terminating plug, thereby be enabled because of the control end that enables that its clock drives triple gate, can clock signal; This signal will be through the clock bus of all motherboards in the bus expansion cable drive system, thereby guarantees that whole expanding system uses unified synchronised clock.

The present invention has following significant advantage:

1, the present invention has adopted the mode of active motherboard and Integration Bus, will distribute and integrated combining, and has realized the distribution of wave recording device and integrated.Independent, the concurrent working of a plurality of sub-oscillographs ability realizes profile samples, Distribution calculation, distribution record ripple and distributed store in the device.Thereby expanded the capacity and the bandwidth of system effectively and greatly improved the reliability of installing.And owing to have the integrated characteristics of modular bus concurrently; A plurality of sub-oscillographs are concentrated and are plugged on the same motherboard in the system; And realize interconnectedly through the various buses on the motherboard, guaranteed the strict synchronism of working between accurate timing and each the sub-oscillograph of system easily.That is to say both had the big capacity of parallel distributed system, high bandwidth, low-risk advantage, have the advantage that the bus integrated system is simple in structure, be convenient to realize strict synchronism again based on the integrated wave recording device of the distribution of parallel bus.To distribute and integrated combining, be a kind of innovation.

2, it is both interconnected through the network realization that the active motherboard and the integrated bus structures that distribute make a plurality of sub-oscillograph of system, externally realizes data remote through network is independent again, or realize man-machine interaction through network through supervisor.A plurality of sub-oscillographs are reciprocity in mutual contact and contact with foreign countries co-relation in the distributed-type integrated recorder.It is a kind of innovation that this multimachine is concentrated the extranet structure with respect to the single site that traditional oscillograph adopted distributed whole network system configuration.The multimachine peer-to-peer network had both made things convenient for information sharing, guaranteed data bandwidth again, realizes big capacity, high bandwidth and low-risk for distributed-type integrated recorder further guarantee is provided.

3, the active motherboard and the integrated bus structures that distribute can guarantee the strict synchronism of data computation between each sub-oscillograph that works alone, and satisfy the asynchronous relevance of the sub-oscillograph of separate unit between data sampling, transmission, calculating and record ripple process again.For laying a good foundation in the computational methods of " segmentation is calculated to go up and guaranteed synchronously, on Distribution calculation, allows asynchronous ".

4, the present invention can adopt the son record ripple file of distributed store on each sub-oscillograph to constitute a complete record ripple file, and the way of this distribution file system also is a kind of innovation.The file size of each sub-oscillograph record is N/one of equal capacity tradition oscillograph record ripple file, and N is a sub-oscillograph number integrated in the device.The distribution file system access is more convenient, stores saferly, and single son record ripple file content is few; Mark is clear and definite; Help rapid analysis and location, reduce amount of calculation, transmission quantity and the memory space of system effectively the system failure, convenient simultaneously to the failure logging file retrieval and search.

Description of drawings

Fig. 1 is this distribution integration oscillograph mother board bus structures sketch mapes.

Fig. 2 is this distribution integration oscillograph mother board bus logic control circuit schematic diagram.

Fig. 3 is the wiring schematic diagram of this distribution integration oscillograph mother board bus and sub-oscillograph.

Fig. 4 is the synchronised clock automatic switch-over circuit figure of motherboard synchronised clock and sub-oscillograph.

Fig. 5 is house dog Auto-Sensing and control signal commutation circuit figure.

Fig. 6 is motherboard control line and condition line logic control circuit figure.

Circuit theory diagrams when Fig. 7 is the system school.

Fig. 8 is motherboard reset bus and reset circuit figure.

Fig. 9 is the RS485 network diagram with preferential token integrated on the motherboard.

Figure 10 is a RS422 network diagram integrated on the motherboard.

Figure 11 is a SPI synchronous serial network diagram integrated on the motherboard.

Figure 12 is a motherboard expansion sketch map.

Figure 13 is single motherboard line sketch map." A " expression expansion plug among the figure, " B " representes terminating plug.

Figure 14 is a plurality of motherboard line sketch mapes, and among the figure, " C " is expansion cable.

Figure 15 is the preferential chain bus expansion of a formation Synchronization Control sketch map.

Figure 16 is the expansion sketch map of RS485 net and priority token rings.

Embodiment

Present embodiment is an example with the dynamic oscillograph that distributed integration oscillograph mother board and parallel bus structure are used for electric power system, each numbering " number " consistent with " # " lexical or textual analysis, like No. 0 slot with the 0# slot.

The dynamic wave recording device of the so-called power failure of dynamic oscillograph that in electric power system, uses is used for the various parameters of transmission line, main transformer or generating set are uninterruptedly measured and analyzed.System parameters occur sudden change, unusual or when having the incident that satisfies the condition that preestablishes to take place device will start and record ripple; The Wave data of the various real-time measurement parameters before and after synchronous recording sudden change, the unusual or incident; And recorder data analyzed, calculates; Discriminating fault types and character, accurately the fault location position provides the report of record ripple.Simultaneously, the recorder data teletransmission that device also will be stored in local disk through network is done further to analyze and handle to data center.Nowadays, dynamically oscillograph has become a kind of special large-scale on-line monitoring equipment that power industry must be installed by regulation.

Owing to all there is strict temporal correlation in the electric power system between all measured signals, so must carry out synchronized sampling to all channel signals during measurement.And the association in time of incident of catching or sudden change in order to guarantee, device must guarantee to the analysis of each channel sample data and calculating synchronously, and guarantee that behind starting record ripple, the Wave data of each passage that is write down also is synchronous in time.Simultaneously, because the specific (special) requirements of power industry need be carried out the high-speed synchronous sampling to a plurality of parameters when dynamically oscillograph is worked, and image data is carried out real-time analysis, calculating and record ripple.Passage is many, sample rate is fast, precision is high, so it is all very big to relate to calculating, record, storage and data quantity transmitted owing to measure.The present invention guaranteed to all channel signal synchronized samplings, each channel sample data computation synchronously, and the Wave data of each passage that guarantees behind starting record ripple, to be write down also is synchronous in time, the complete needs that satisfy growing power industry.

Referring to Fig. 1, Fig. 2, Fig. 3.

The shared motherboard of the sub-oscillograph of each of distributed-type integrated recorder system is active motherboard, large scale integrated chip LC4512 is installed on motherboard realizes required complicated control logic.Be provided with 8 sub-oscillograph bus slots on the motherboard, 8 sub-oscillographs are through corresponding successively parallel being connected on the motherboard of bus plug.Also be provided with the bus slot of 1 supervisor on the motherboard, can connect a supervisory computer, whether supervisor can be selected to connect as required.Integrated parallel bus has been realized the interconnected of sub-oscillograph and for all sub-oscillographs shared clock and power supply is provided on the motherboard.The programmable chip and the control circuit that are integrated in system are that bus provides necessary control, sequential and logic.Also integrated RS485 net, RS422 net and SPI synchronous serial net are used for internal system communication on the motherboard.

Bus integrated on the motherboard has:

1. clock bus: 4 clock cables such as total 10KHz, 20mS, 100mS and 1S on the motherboard.The pulse signal of these four kinds of different frequencies is from same 4M crystal oscillator source, and the frequency dividing circuit in motherboard ISP obtains.These signals cause through the motherboard connection-peg among the ISP of sub-oscillograph, after signal automatic switch-over circuit and pulsewidth and delay processing, finally are connected respectively to the interruption input pin of sample circuit and digital signal processor DSP and microprocessor ARM.Be the operate as normal of sub-oscillograph and providing safeguard synchronously of whole system.

2. control line and condition line: have on the motherboard 7 control signal wires and 6 bar state holding wires altogether integrated.Wherein except the house dog control line; 6 remaining control signal wires are corresponding one by one with 6 bar state holding wires, are respectively calculation control line and condition line, formation train line and condition line, record ripple control line and condition line, record value control line and condition line, definite value control line and condition line and Token Control line and condition line.The house dog control line is from sub-oscillograph, and its state is used for distinguishing whether insert sub-oscillograph template on certain inserting groove of motherboard, and whether the sub-oscillograph that is inserted is in proper working order.The token signal line then is used for the Token Control and the reception of RS485 series connection communication network integrated on the motherboard.Remaining 5 pairs of holding wire is used for realizing system synchronization.Wherein calculation control line and computing mode line are used for realizing the segment sync that sub-oscillograph calculates.Record ripple, record value and definite value control line and condition line are used for realizing the precise synchronization of a plurality of sub-oscillograph record ripples under the different pieces of information recording mode.Formation train line and condition line be used for the control data formation synchronously.

3. bus during the school: 2 signal line during when bus comprises the internal clock school during school and external clock school.The internal clock correcting delay signal is claimed system's correcting delay signal again, and it is from the branch or the pulse per second (PPS) output of the minimum sub-oscillograph calendar clock of numbering in the system.The external clock correcting delay signal is the GPS correcting delay signal, from the branch or the pulse per second (PPS) output of external GPS synchronised clock.These two kinds of correcting delay signals are input in the sub-oscillograph simultaneously, are selected automatically to switch benchmark during as sub-oscillograph data markers and calendar clock school by sub-oscillograph.

4. reset bus: integrated reseting signal line on the motherboard.All sub-oscillographs both can reset separately respectively in the device, also can realize synchronous reset through the systematic reset signal line.The system reset function comprises that device electrification reset, software watchdog reset, hardware watchdog resets, power failure automatically resets, the unit hand-reset, the multimachine manual synchronization resets and supervisor or far-end reset.

5. power bus: device is equipped with the duplicate supply that can automatically switch, and provides ± 5V and ± 12 stabilized voltage power supplys to sub-oscillograph through the motherboard power bus.

Referring to Fig. 4.

Clock is the basis of distribution oscillograph operate as normal and parallel synchronous.Device has designed two cover synchronised clocks.The system clock that is produced by motherboard ISP chip, it is shared to offer in the device all sub-oscillographs through clock bus.By the local clock that the ISP chip of each sub-oscillograph produces, only offer the book oscillograph and use.Two cover clocks have adopted identical structure, and its output signal is also identical.All sub-oscillographs always are to use the synergic system clock that motherboard produces in the normal condition lower device.Group oscillograph debugging single board or only make veneer wave recorder and use to throw off motherboard work perhaps breaks down when motherboard, can't provide the sub-oscillograph of synergic system clock just to launch local clock.Automatic identification circuit switched system clock or local clock on the sub-oscillograph.

The 10KHz of system clock and local clock, 20mS, 100mS and 1S4 bar clock cable are incorporated into the input of automatic switch-over circuit simultaneously.Wherein 4 road of system clock signals by received respectively 2 select 1 variable connector V74158 A0, B0, C0, D0 end.4 road signals of local clock are received 2 respectively and are selected A1, B1, C1, the D1 of 1 variable connector V74158 to hold.Local 10KHz signal is also received the counting end of counter V74162 simultaneously, and system 10KHz signal is received the clear terminal of same counter.During work, if there is clock signal of system, then the 10KHz of system signal will be constantly to counter O reset.Counter carry end TC output 0, the S end of variable connector V74158 is 0.At this moment No. 0 port, i.e. clock signal of system are connected in variable connector output.If clock signal of system disappears, the clear terminal of counter V74162 does not have quenching pulse.This hour counter receives local 10KHz pulse, constantly but not zero clearing of counting.TC uprises and is latched at 1 level through certain hour counter carry end, and the S end of variable connector uprises.So its output is switched to port No. 1, promptly exports the local clock signal.When clock signal of system reappeared, the 10KHz signal of system clock can be immediately with counter O reset.So TC holds step-down, the S of variable connector holds also step-down.The output of variable connector switches back to port, output system clock again No. 0.

No matter be clock signal of system or local clock signal,, also will pass through pulsewidth shaping circuit and delay circuit and handle after variable connector output.These pulse signals finally are sent to the sample circuit of sub-oscillograph and the interruption input pin of digital signal processor DSP and microprocessor ARM.The 10KHz signal is mainly as data latching and sample-synchronous signal.The 20mS pulse is as transfer of data synchronizing signal and the calculating segment sync of DSP to ARM.The 100mS clock is as calculating synchronously and the synchronous reference signal of formation.The 1S clock is synchronous and clock synchronization reference signal as formation.

Referring to Fig. 2, Fig. 5, Fig. 6.

House dog Auto-Sensing circuit discerns whether be plugged with sub-oscillograph on the corresponding slot of motherboard and whether this sub-oscillograph is in proper working order automatically.Commutation circuit is not pegged graft the sub-oscillograph of sub-oscillograph or grafting at slot can the correlation function of sub-oscillograph and slot excises from the motherboard logic with correspondence automatically when shutting down for some reason, makes its unlikely operate as normal and system synchronization that influences other sub-oscillograph.Each slot all has own corresponding Auto-Sensing and commutation circuit on the motherboard, and the Auto-Sensing of each groove and commutation circuit structure are identical.With 0 groove circuit is example, and the Auto-Sensing and the commutation circuit of 0 groove are made up of 0U1-0U13.0U1,0U2,0U6 and 0U7 constitute the signal leading edge detecting circuit, and 0U3 is a counter, and 0U5 and 0U12 are the R-S trigger, and 0U4 8 the tunnel 2 selects 1 variable connector.0U12,0U13 and 0U14 constitute 0 groove failure indicating circuit.

When system worked on power, 0U5 output was put 1, and 0U4 output Y0-Y7 is switched to the B0-B7 input.Y0 is forced 1, and Y1-Y5 is forced 0.If do not peg graft sub-oscillograph on No. 0 slot, after this house dog input will be high always, and 0U7 output is low always.0U9 output then is high always.Y0 will remain 1, and Y1-Y5 will remain 0.Or the door 9U1-9U4 correspondence be input as 0, the slot decapacitation that this is equivalent to the sub-oscillograph of not pegging graft makes it not influence the Synchronization Control of other sub-oscillograph.When powering on, failure indicating circuit 0U12 output is also put 1 simultaneously.0U14 output 0.Or the door 9U5 be output as 0, driver ULN2003 correspondence is output as 1, system failure indicator light does not work.

If be plugged with sub-oscillograph on No. 0 slot, sub-oscillograph will regularly be exported the watchdog pulse signal of 1 and 0 alternate after the operate as normal.0U7 will export positive pulse.This pulse makes terminal count output CAO remain 0 on the one hand with counter 0U3 zero clearing always; Simultaneously again 0U5 is put 0.So 0U9 is output as 0,0U4 output Y0-Y7 is switched to the A0-A7 input.0 work song oscillograph will be exported various synchronous control signals and participation system synchronous working.

If 0 work song oscillograph breaks down after work a period of time and shuts down, no longer include watchdog pulse output, WDT with fixed dwell 1 or 0.No matter be the sort of situation, 0U7 will fix output 0.At this moment because the CD of counter 0U3 end is fixed as 0, counter is zero clearing no longer.So after about 60mS delay, the CAO output of counter 0U3 will become 1, thereby 0U4 output Y0-Y7 is switched to the B0-B7 input.Y0 is forced 1, and Y1-Y5 is forced 0.This just makes that the sub-oscillograph that breaks down is excised automatically from system, in order to avoid influence the normal synchronized work of other sub-oscillograph in the system.This moment, d type flip flop 0U12 was put 0,0 groove failure indicating circuit 0U14 output change 1, and driver ULN2003 correspondence is output as 0, and system failure indicator light LED1 lights, and has sub-oscillograph to break down in the indication mechanism.

The back recovers normal if 0 work song oscillograph of fault is automatically reset, and devotes oneself to work again, and then WDT will activate.So 0U7 will export positive pulse and remove zero clearing counter 0U3, thereby make terminal count output CAO return 0.0U5 is put 0 simultaneously, and 0U9 output becomes 0 by 1, and 0U4 output Y0-Y7 switches back to the A0-A7 input.So 0 work song oscillograph is the participation system synchronous working again.0U14 output simultaneously becomes 0, and LED1 extinguishes, and the sub-oscillograph that once broke down in the indication mechanism has recovered normal and devoted oneself to work again.

Referring to accompanying drawing 6.

Design a pair of calculating line synchro on the sub-oscillograph of distributed-type integrated recorder and realized parallel synchronous calculating, comprised a calculation control line and a computing mode line.Calculation control line on each sub-oscillograph is connected on the motherboard through connector, connects by the mode of logical "or".Calculate synchronization control circuit by or door 9U1 and d type flip flop 9U7 constitute.Wherein or the input of door be connected to the calculation control line after each sub-oscillograph slot passes through automatic switch-over circuit respectively.Its output then is connected to the D end of d type flip flop 9U7.D type flip flop output then is connected to the computing mode line of each sub-oscillograph slot respectively.During work, a straw cord for bundling up rice or wheat stalks oscillograph is in the calculating, then the calculation control line is drawn high, otherwise the output of calculation control line is low.Simultaneously, sub-oscillograph is getting into the state that needs the detection computations condition line before that calculates.If the computing mode line is 0, then expression does not have other sub-oscillograph to be in the calculating, and the book oscillograph can be initiated new one and taken turns calculating.And if the computing mode line is 1, then represent still to have in the present system sub-oscillograph to be in the calculating, can not initiate new one and take turns calculating, need to wait for.Since the calculation control line of all sub-oscillographs by " or " connect, so as long as there is a son record ripple to initiate to calculate, be high with its calculation control line, then or be output as height.And at first 20mS pulse front edge of closelying follow thereafter, the output Q of d type flip flop end will uprise, and promptly the computing mode line uprises.In the The whole calculations process, calculate control line and keep height, so as long as also have sub-oscillograph not accomplish calculating, or door output just is high.Even the sub-oscillograph that at this moment has has been accomplished calculating, but detect the computing mode line, can not initiate new one and take turns calculating, and must wait for for high.Have only when all sub-oscillographs and all accomplished epicycle calculating, after wherein the sub-oscillograph of last completion drags down its calculation control line, or door is exported just step-down.At first 20mS pulse front edge of closelying follow thereafter, the output Q of d type flip flop end is with step-down, and the computing mode line is step-down.

Referring to accompanying drawing 2,6.

Distribute and designed 3 pairs of control lines on the sub-oscillograph of integrated wave recording device and condition line is realized the parallel synchronous recording ripple, be respectively record value control line and condition line, record ripple control line and condition line and definite value control line and condition line.These control lines are connected on the motherboard through connector, divide into groups to connect by the mode of logical "or".Record value, record involve the definite value control circuit and synchronously calculating control circuit is the same, also by or and d type flip flop form.Wherein record duty control circuit by or door 9U2 and d type flip flop 9U8 form.Record ripple control circuit by or door 9U3 and d type flip flop 9U9 form.The definite value control circuit by or door 9U4 and d type flip flop 9U10 form.The input of 9U2,9U3 and 9U4 is respectively from record value control line, record ripple control line and definite value control line behind each sub-oscillograph slot process automatic switch-over circuit.The output of d type flip flop 9U8,9U9 and 9U10 then is connected to record state of value line, record ripple condition line and the definite value condition line of each sub-oscillograph slot respectively.

During work, a straw cord for bundling up rice or wheat stalks oscillograph has record ripple or the request of record value, and just that it is corresponding record ripple or record value control line are drawn high, or door 9U3 or 9U2 output uprise.And at first 20mS pulse front edge of closelying follow thereafter, the output Q of corresponding d type flip flop 9U8 or 9U9 end will uprise, and cause the state of record ripple or record state of value line to uprise.The ARM of each sub-oscillograph samples to condition line when response 20mS interrupts afterwards.Find that record ripple or record state of value line are high, showing has sub-oscillograph to propose synchronous record ripple or the request of record value synchronously in the system, so start the record ripple or the record value process of this machine immediately.

When record ripple or record value process finish, the son record ripple that sends record ripple or the request of record value drags down self record ripple or record value control line.After all son record ripples that send record ripple or the request of record value all drag down self record ripple or record value control line.Or door 9U3 or the corresponding output change 0 of 9U2.Then after first 20mS pulse front edge, the output Q of corresponding d type flip flop 9U8 or 9U9 end will become 0, cause the record ripple or record the state step-down of state of value line.The ARM of each sub-oscillograph samples to condition line when response 20mS interrupts afterwards.Find that record ripple or record state of value line are low, show that the request of record ripple in the system or record value is cancelled, so finish the record ripple or the record value process of this machine immediately.

The operation principle of definite value control circuit is identical with the operation principle of record ripple or record duty control circuit, and the definite value line is mainly used in and cooperates record swash and record value line with definite different recording mode.

Referring to Fig. 2, Fig. 6.

The formation synchronization control circuit selects preferential automatic switchover link that 1 variable connector 0U11-7U11 constituted by 2 and forms with a door 9U6.Wherein the A input of each variable connector all is connected to sub-oscillograph slot through the formation train line behind the automatic switch-over circuit.The B input then is connected to the output Z of the pairing variable connector of next slot.Variable connector receives the control of S end.When being plugged with sub-oscillograph and this sub-oscillograph on the slot when in proper working order, the Auto-Sensing circuit is output as 0, and the output Z of variable connector switches to input A.And when the sub-oscillograph work of not pegging graft sub-oscillograph on the slot or pegged graft was undesired, the Auto-Sensing circuit was output as 1, and the output Z of variable connector switches to input B, the pairing formation train line of just next slot.The effect of this control handoff links is in N sub-oscillograph slot, confirms a groove minimum automatically and is plugged with the slot of the sub-oscillograph of operate as normal, with the formation train line of this groove formation train line as system.This control line is connected to and door 9U6.The output of 9U6 is the formation synchronous regime line of system.

Formation synchronous working principle is following: after the starting of sub-oscillograph, the formation train line of self is drawn high, self still be among the initialization procedure to inform other sub-oscillograph.In case initialization finishes, sub-oscillograph just drags down the formation train line immediately, self has accomplished initially to inform other sub-oscillograph, and the initial pointer of its data formation has been dialled get back to 0, has entered into holding state.After getting into holding state, sub-oscillograph will be checked the state of formation synchronous regime line when each 100mS lock-out pulse arrives.If formation synchronous regime line is high, sub-oscillograph will continue standby.If formation synchronous regime line is low, the sub-oscillograph that has formation synchronous regime control in the then expression system has been accomplished initially, is in holding state; Perhaps this sub-oscillograph has begun normal calculating, but its data queue does not have accumulation this moment.No matter be the sort of situation, show that all the initial pointer of the sub-oscillograph of benchmark data queue has dialled back 0, and formation at present be sky, at this moment can incorporate system into.So sub-oscillograph will be provided with the software synchronization mark immediately, and activate the queue count pointer, thereby enter into the formation synchronous regime.

Referring to Fig. 7.

Circuit is used to the time synchronized of the system that guarantees during the school of system.Circuit is divided into two parts during the Circuits System school.Part design realizes required circuit by the ISP on the sub-oscillograph on sub-oscillograph.Another part design is on motherboard.It comprises outside input pulse isolated variable circuit and the pulsewidth shaping circuit among the motherboard ISP on the motherboard, and this two signal line of pulse bus when bus and GPS school when being integrated in the system school on the motherboard.In addition, an also integrated RS232 receives bus on the motherboard.The RS232 serial ports of all sub-oscillographs all can be connected on the motherboard RS232 bus through slot in the device, receives the data from external equipment, for example, and the time signal of GPS.

During work, pulse causes among the motherboard ISP behind isolated variable during the outside school sent here by the GPS synchronised clock.When delivering to GPS school integrated on the motherboard again after the pulsewidth shaping circuit is handled in ISP then on the pulse bus.Deliver among the ISP of each sub-oscillograph through the 32B pin of bus plug at last.Pulse signal when system also provides other one tunnel inner school simultaneously, it interrupts exporting from the alarm clock of each sub-oscillograph self calendar clock, i.e. 26 pin of calendar clock chip M41ST95, this signal also is sent among the ISP of sub-oscillograph.

In the course of work, pulse when sub-oscillograph ARM interrupts whether inserting the GPS school in the pin real-time detection system through INT0.Pulse when if the GPS school is arranged, ARM then exports 0 level through I/O mouth COL3, thereby connects and door U33, turn-offs simultaneously and door U34.So pulse is through delivering to the input A of bidirectional buffering door U36 with door U33 or door U35 during the GPS school.And if ARM pulse when not detecting the GPS school or detects pulse when having the GPS school originally, but this pulse disappears again for some reason, then exports 1 level through COL3, thereby turn-offs and a door U33, connects simultaneously and a door U34.So pulse is through delivering to the input A of bidirectional buffering door U36 with door U34 or door U35 during inner school.Bidirectional buffering door U36 receives the control of NOR gate U31 output.Under the normal operation, ARM is through ROW2 pin output watchdog pulse, so counter 0U37 is by the periodicity zero clearing, and its output CAO keeps low level.On the other hand, 0# oscillograph is exported 1 level through the ROW0 pin, thus NOR gate 0U31 output 1, thus open bidirectional buffering door U36.And other sub-oscillograph ROW0 pin is exported 0 level, and corresponding NOR gate 0U31 output 0 is so its bidirectional buffering door 0U36 separately is high-impedance state.At this moment no matter deliver to A end be outside (GPS) school the time pulse, or pulse during inner (calendar clock) school all will be delivered to through the output Z of 0# oscillograph bidirectional buffering door U36 on the BIO pin of EGPIO14 pin and DSP of ARM I/O mouth.The A end signal is simultaneously through the XB end of 0# oscillograph bidirectional buffering door, and the 23C pin of bus plug is when causing the system school of motherboard on the bus.And then through other sub-oscillograph 23C pin separately, the pulse signal is delivered to the XB end of each sub-oscillograph during high-ranking officers.And finally deliver on the BIO pin of EGPIO14 pin and DSP of each sub-oscillograph ARM I/O mouth.

When 0# oscillograph quit work for some reason, its ROW2 pin was no longer exported watchdog pulse.The output of the pulse front edge differential circuit of being made up of 0U23-0U26, i.e. the output of 0U26 will be fixed as low level.No longer zero clearing of counter 0U37, through the regular hour delay, its output CAO will be uprised by low.NOR gate 0U31 exports step-down, thereby turn-offs bidirectional buffering door 0U36.Pulse when after this other sub-oscillograph will no longer regularly be received the school in the system.Through certain delay; Next groove number less sub-oscillograph in the system finds that like 1# oscillograph 0# oscillograph has unusually, will be through ROW0 pin output high level; Connect the bidirectional buffering door 0U36 of self, take over 0 sub-# oscillograph pulse when system provides the school automatically.

And when not pegging graft sub-oscillograph on the 0# slot, after other sub-oscillograph works on power, pulse when can not receive regularly the school.Through certain delay, next groove number less sub-oscillograph will be taken over the pulse when system provides the school of 0# oscillograph equally automatically like 1# oscillograph in the system.The rest may be inferred by analogy for it.

Referring to accompanying drawing 8.

System reset circuit is divided into two parts.Part design realizes required circuit by the ISP on the sub-oscillograph on sub-oscillograph.Another part design realizes required circuit by the ISP of motherboard on motherboard.The system reset function comprises that device electrification reset, software watchdog reset, hardware watchdog resets, power failure resets, the unit hand-reset, the multimachine manual synchronization resets and supervisor or far-end reset etc.

The multimachine manual synchronization resets: on the device case front panel, system reset pad is installed also.Press this button and will produce a negative pulse.This negative pulse is admitted to motherboard ISP.Behind the pulse front edge differential circuit of forming through SU1, SU3 and by SU4-SU7, export through SU8, SU10 again.The pulse of SU10 output is sent on the motherboard reset bus, then through the triple gate 0U16-7U16 output that resets of each groove, is used to control the automatic switch-over circuit of each groove.This pulse also causes on the reset signal input pin of each sub-oscillograph through the bus plug of each groove simultaneously, and each sub-oscillograph is used to reset.

Supervisor or far-end reset: if system configuration has supervisor, perhaps accept far-end control, also can give an order through man-machine interaction, let supervisor or remote termination output pulse go the whole system that resets.At this moment pulse is admitted to motherboard ISP.Behind the pulse front edge differential circuit of forming through SU2, SU3 and by SU4-SU7, export through SU9, SU10 again.Through the triple gate 0U16-7U16 output that resets of each groove, be used to control the automatic switch-over circuit of each groove at last, and each sub-oscillograph that resets.

Referring to accompanying drawing 2, Fig. 9.

Integrated RS485 host will be used for command communication and the internal information exchange between the sub-oscillograph on the distributed integration oscillograph mother board.For example, during starting record ripple, 0# oscillograph will through the RS485 net to other all sub-oscillographs broadcast the file designation of up-to-date record ripple, and this system time constantly.Again such as, each sub-oscillograph can be regularly, through the RS485 net self working state is sent to other sub-oscillograph successively, with as the reference of all sub-oscillograph collaborative works in the system etc.

Fig. 9 is the RS485 network and is used to control the schematic diagram that sub-oscillograph sends the priority token rings that enables.As can be seen from the figure, all sub-oscillographs all are connected with RS485 bus on the motherboard through interface plug and realize interconnected in the device.The RS485 port of every estrade oscillograph is exactly a network node that receives token ring control.Design has guaranteed whenever all sub-oscillographs all are in the reception enabled simultaneously in this network, therefore can receive the information of broadcasting on the network simultaneously.But whenever can only there be an estrade oscillograph to be in the transmission enabled in the system.Specifically be that estrade oscillograph is in and sends enabled and controlled by the hardware token ring.Every estrade oscillograph is realized control through 3 ports.Wherein the ROW3 port of ARM is used to export the Token Control signal; The ROW1 port is used to export the RS485 transmission and enables control signal; The EGPIO8 port is used to receive the token status signal.Having only the ROW3 of working as, ROW1 and EGPIO8 is 1 simultaneously, and the input of 3 among the ISP just is 1 with the output (122 pin of ISP) of door, and at this moment the RS485 output port of this sub-oscillograph enables, thereby becomes the current transmitting terminal on the RS485 network.

Can know that from Fig. 2, Fig. 9 token ring is 8 and the door (0U10-7U10) that is connected in series, each is connected to corresponding slot through the Token Control end behind the automatic switch-over circuit with an input of door.Then link to each other with the output of door with another input of door with previous.This port is also connected to the input of the corresponding state-detection door 0U15-7U15 of each groove simultaneously.Another input of state-detection door 0U15-7U15 is then from the output of token status feedback door MU21.

During work, sub-oscillograph is detected token status through the token status line, and through Token Control line application token.Under the normal condition, each sub-oscillograph should put 0 with self Token Control line in the device, detects the token status line then.If this moment certain sub-oscillograph to detect the token status line be 1, have the lower sub-oscillograph of priority using token in the expression system, like non-special circumstances, should wait for.And if detect the token status line is 0, then representes not have in the present system sub-oscillograph use token or have the higher sub-oscillograph of priority using token.At this moment sub-oscillograph can be applied for token through self Token Control line is put 1.After filing an application, confirm to obtain whether token through detecting the token status line again.If this moment, the token status line was 0, expression does not obtain token as yet, needs to continue to wait for.And if detect the token status line is 1, then expression has obtained token.So this sub-oscillograph can with ROW1 put 1 finally enable self the RS485 output port.

With 0# oscillograph is that example is explained.If 0# oscillograph will use the RS485 net, should be earlier self Token Control line be put 0, detect the token status line then.If the token status line is 1, then explanation has other sub-oscillograph using the RS485 net at present.At this moment like no special circumstances, 0 sub-# oscillograph should be waited for.And if 0# oscillograph to detect the token status line be 0, then explanation does not have other sub-oscillograph to use the RS485 net at present.So 0 sub-# oscillograph puts 1, the application token with self Token Control line earlier.And then detection token status line.When detecting token status line=1, can enable the RS485 output port of self, and begin through RS485 net broadcast message.After finishing using, 0 sub-# oscillograph should put 0 with the ROW1 line earlier, decapacitation self RS485 output port, and then token control line ROW3 put 0, discharge token.The Token Control ring of this device has priority level.At any time, system can both always have the sub-oscillograph of the operate as normal of a groove minimum to can be used as the main website that RS485 nets, the work that comes coherent system in the assurance device.This has just greatly increased the reliability and device configuration flexibility of system works.

Referring to accompanying drawing 10.

RS422 netting gear integrated on the distributed integration oscillograph mother board has double action.When system was in test mode, sub-oscillograph sent Debugging message through the RS422 net to supervisor.And when system was in normal operating conditions, sub-oscillograph passed through the RS422 net to the error message of supervisor transmitting system.

All sub-oscillographs all are connected with RS422 network on the motherboard through interface plug in the device.Design has guaranteed whenever all sub-oscillographs all are in the reception enabled simultaneously in this network, therefore simultaneously the receiving management machine through the order of Web broadcast.But whenever can only there be an estrade oscillograph to be in the transmission enabled in the system, can sends information to supervisor.Specifically be that estrade oscillograph is in and sends enabled and confirmed by the output of decoder MU17.The code signal of 3 input A0 of decoder, A1, A2 is from supervisor I/O output or panel toggle switch.When K switch 2-3 broke off, decoder was controlled by supervisor.At this moment both can specify a certain sub-oscillograph to send information through man-machine interaction, supervisor be connected the RS422 transmit port of this sub-oscillograph through the I/O output encoder then; Also can adopt polling mode, by the automatic output encoder 0-7 of supervisor, thus all sub-oscillograph in the connection system successively.And when system is not equipped with supervisor, then can connect switch K2-3, and control decoder with toggle switch K2-0, K2-1, K2-2 then, select to connect different sub-oscillographs.At this moment the onsite user can obtain information from the serial ports of expanding panel through portable computer.

K1 is used for selecting RS422 or RS232 among the figure, with adaptive different supervisor interface.

Referring to accompanying drawing 11.

SPI synchronous serial net is divided into two parts.Promptly be integrated in the Intranet on each sub-oscillograph and be integrated in the outer net on the motherboard.Intranet is used for realizing in the same sub-oscillograph ARM communicate by letter with the bidirectional high speed between DSP, calendar clock and the shift register (20Mbps).ARM decides (Master) during work, and other is done from (Slave).ARM exports through EGPIO5 and two port controlling decoding circuits of ROW6 and selects from object.A1A0=10 selects DSP.A1A0=01 selects calendar clock.A1A0=11 selects shift register.When A1A0=00, then select outer net.Outer net can be used to realize that the bidirectional high speed between the sub-oscillograph of 0# oscillograph and other communicates by letter.At this moment 0 groove ARM decides, 1-7 groove ARM do from.During outer net work, 0 groove ARM at first sends the command frame that comprises the notch numbering to 1-7 groove ARM.Next the ARM that is called the roll gets through chip selection signal, sends data to 0 groove ARM then, thereby accomplishes master-slave communication one time.

Referring to accompanying drawing 12,13,14,15,16.

Though there are not bottleneck problems such as resource-constrained and data bandwidth restriction in distributed-type integrated recorder when System Expansion, receive the restriction of standard PC case installation dimension, only be designed with 10 the 96 accurate connection-pegs of pin mark on the motherboard at present.Therefore except extension socket and supervisor, 8 estrade oscillographs can be installed at most.Can insert 18 tunnel analog quantitys and 32 way switch amounts or not insert analog quantity and the 64 way switch amounts that only insert are calculated by every estrade oscillograph, the capacity of each motherboard and cabinet can be from 144 tunnel analog quantitys+256 way switch amounts to 0 tunnel analog quantity+different segmentations combinations the 512 way switch amounts.Bigger if desired capacity need be expanded through system bus and realize.So-called bus expansion promptly when realizing the vast capacity system, is used a plurality of cabinets and motherboard, and through expansion cable it being cascaded up constitutes more massive parallel bus distribution integrated system.

Figure 12 couples together the sketch map of a formation expanding system through bus cable by daisy chaining for N motherboard.For example calculate, can realize from the segmentation combination of the different capabilities of 1152 tunnel analog quantitys+2048 way switch amounts or 0 tunnel analog quantity+4096 way switch amounts by the expanding system of 8 cabinets.

Like Figure 13, when single motherboard construction system, only need on the extension socket of motherboard, to plug terminating plug and just can realize operate as normal.

The expansion of clock bus and record ripple bus: is example with clock bus on Figure 14 motherboard (comprising 1S, 100mS, 20mS, 10KHz signal) and record ripple control line with record ripple condition line.Visible by figure, connect through expansion cable, N motherboard clock bus separately is connected.At this moment in the system clock of each motherboard by decapacitation; Can not clock signal; Have only last motherboard that is plugged with terminating plug because its clock drive that triple gate is enabled can clock signal; This signal guarantees the clock synchronization of whole expanding system with the clock bus of all motherboards in the drive system.In the system N motherboard 8 record ripple control lines separately combine constituted the input of a 8xN end or door, or the output of door has then been received on N the motherboard record ripple condition line separately.So just formed one and can realize that 8xN estrade oscillograph records the distribution record wave system system of ripple synchronously.Other is identical with the wavy attitude line circuit structure of record with record ripple control line with the circuit structure of record state of value line, definite value control line and definite value condition line and calculation control line and computing mode line like record value control line; The extended mode of its bus is also identical, does not draw in detail among the figure.

The expansion of the preferential chain of formation Synchronization Control is referring to Figure 15.For brevity, the expansion of only having drawn 0# and two motherboards of 1# among the figure connects, and draws 0# on each motherboard, the synchronously preferential chain of the formation of a 6# and 7#3 slot.Visible by figure; The output of the synchronously preferential chain of 1# motherboard 0# slot formation is connected to the B input of the synchronous commutation circuit 7U11 of 0# motherboard 7# slot formation through expansion cable; The output of the synchronous commutation circuit 0U11 of 0# motherboard 0# slot formation then is connected to 22 pin of 1# motherboard extension socket, i.e. the formation synchronous regime line of 1# motherboard through expansion cable.Simultaneously 21 pin of 1# motherboard extension socket are connected to 22 pin of 0# motherboard extension socket, i.e. the formation synchronous regime line of 0# motherboard through cable.Thereby the formation Synchronization Control chain of two motherboards is linked, form the preferential chain of an integral body.So having the system of 16 sub-oscillographs during operate as normal will be benchmark with the formation control line of 0# motherboard 0# oscillograph.And if 0# motherboard 0# slot is not pegged graft sub-oscillograph or the sub-oscillograph of being pegged graft quits work for some reason, then system will be a benchmark with the formation control line of 0# motherboard 1# oscillograph.The rest may be inferred.This shows that in the 16 slot systems that form through expansion, 0# motherboard 0# slot has the highest priority level.1# motherboard 7# slot then has minimum priority level.

Shown in Figure 16 is the expansion connection sketch map of RS485 net and priority token rings.For brevity, the expansion of also only having drawn No. 0 and No. 1 two motherboards among the figure connects, and has also only drawn 0# on each motherboard, and 1# and 7#3 slot priority token rings connects.Visible by figure; The output of 0# motherboard 7# slot token ring is connected to the input of 1# motherboard 0# slot token ring circuit 0U15 and 0U10 through expansion cable; The output that 1# motherboard 7 is inserted # groove token ring then is shorted to 12 pin through terminating plug 11 pin; Connect with the token status line of two motherboards then, thereby the token ring of two motherboards is linked, the token that forms an integral body preferentially encircles.So have during operate as normal in the system of 16 sub-oscillographs, for the highest, the token priority level of # motherboard # work song oscillograph is minimum with the token priority level of the sub-oscillograph of 0# motherboard #.

Other bus in the system only need be communicated with bus corresponding on each motherboard through expansion cable when bus during like the school, reset bus expansion and get final product.

Claims (9)

1. distributed integration oscillograph mother board and parallel bus structure, it is characterized in that: the shared motherboard of each sub-oscillograph is active motherboard in the distributed-type integrated recorder; The large scale integrated chip that can realize complicated control logic is installed and the bus slot of peg graft sub-oscillograph and supervisor on motherboard; Simultaneously an also integrated cover is with the parallel bus of control logic on the motherboard; Also be provided with the parallel bus suitable on each sub-oscillograph in the device with motherboard; During work, each sub-oscillograph is plugged on the motherboard through bus plug correspondence successively, and with motherboard bus UNICOM; Bus, reset bus and power line when integrated parallel bus comprises clock bus, control bus, status bus, school on the said motherboard; Control circuit comprises house dog Auto-Sensing and control signal commutation circuit, calculates synchronization control circuit, records ripple synchronization control circuit, formation synchronization control circuit, correcting delay signal treatment circuit and system reset circuit;

Said control bus has 7, and status bus has 6; Wherein, The calculation control line is with computing mode line, formation train line and quene state line, record ripple control line and record the ripple condition line, record value control line is corresponding one by one with the token status line with record state of value line, definite value control line and definite value condition line and Token Control line, and all the other control buss are house dog control lines; 2 signal line during when bus comprises the internal clock school during said school and external clock school;

Each sub-oscillograph bus slot all has own corresponding house dog Auto-Sensing and control signal commutation circuit on the motherboard; And the house dog Auto-Sensing and the control signal commutation circuit structure of each slot are identical, and the house dog control line is connected to house dog Auto-Sensing and control signal commutation circuit; Record ripple synchronization control circuit is made up of record ripple, record value and 3 kinds of circuit of definite value control jointly; Calculate synchronization control circuit by or door and d type flip flop form; Record value, record involve the definite value control circuit by or door and d type flip flop form; The formation synchronization control circuit is by selecting preferential automatic switchover link that 1 variable connector constituted with sub-oscillograph corresponding 2 and forming with door; System reset circuit divides two parts, and wherein a part is on sub-oscillograph, and another part is on motherboard; The correcting delay signal treatment circuit also divides two parts, and wherein a part is on sub-oscillograph, and another part is on motherboard;

Integrated RS485 network, RS422 network and SPI synchronous serial network comprise communication network bus and correspondent control circuits on the motherboard; Wherein, the RS485 netting gear has priority token rings control; Motherboard is provided with the bus expansion slot, and N motherboard connects and composes the expanding system that N motherboard formed through the bus expansion cable;

The expansion of N motherboard is that the expansion slot of N motherboard couples together by daisy chaining through the bus expansion cable, and being arranged in the terminating plug of pegging graft on the terminal expansion cable plug, constitutes the expanding system that N motherboard formed;

The expansion of record ripple, record value, definite value and calculation control line and corresponding state line: separately 8 the importing or be connected of 8 record ripple control lines, record value control line, definite value control line and calculation control lines on N motherboard through expansion cable; Synthesize respectively separately 8 * N input or door; Or the output of door is connected to the D end of the corresponding control circuit d type flip flop of terminal motherboard, and the output Q end of d type flip flop then is connected respectively to separately record ripple condition line of N motherboard, records state of value line, definite value condition line and computing mode line through expansion cable.

2. distributed integration oscillograph mother board as claimed in claim 1 and parallel bus structure is characterized in that: said clock bus is meant a cover synchronised clock that is obtained by generation of same 4M crystal oscillator source and the frequency dividing circuit in motherboard ISP, is called system clock; In the ISP of sub-oscillograph, also adopt the synchronised clock that has produced a cover oneself in the same way simultaneously, be called local clock; System clock and local clock are incorporated into the input of firing the automatic switch-over circuit in sub-oscillograph ISP simultaneously; After the switching output through sub-oscillograph automatic switch-over circuit; Handle through pulsewidth shaping circuit and delay circuit again, finally be sent to the sample circuit of sub-oscillograph and the interruption input pin of digital signal processor DSP and microprocessor ARM.

3. distributed integration oscillograph mother board as claimed in claim 2 and parallel bus structure is characterized in that: said system clock and local clock have 10KHz, 20mS, 100mS and 1S totally 4 tunnel clock signals respectively; Wherein, the 10KHz signal is as data latching and sample-synchronous signal; The 20mS pulse is as transfer of data synchronizing signal and the calculating segment sync of DSP to ARM; The 100mS clock is as calculating synchronously and the synchronous reference signal of formation; The 1S clock is synchronous and time synchronized reference signal as formation; Said system clock and local clock are incorporated into the input of automatic switch-over circuit simultaneously; 4 road signals that are meant system clock by received respectively 2 select 1 variable connector V74158 A0, B0, C0, D0 end; 4 road signals of local clock are received same 2 respectively and are selected A1, B1, C1, the D1 of 1 variable connector to hold; Local 10KHz signal is also received the counting end of the counter V74162 of automatic switch-over circuit simultaneously, and system 10KHz signal is received the clear terminal of same counter.

4. distributed integration oscillograph mother board as claimed in claim 1 and parallel bus structure is characterized in that: 2 signal line are meant during when bus comprises the internal clock school during said school and external clock school: the internal clock correcting delay signal is from the branch or the pulse per second (PPS) output of the minimum sub-oscillograph calendar clock of numbering in the system; The external clock correcting delay signal is the GPS correcting delay signal, from the branch or the pulse per second (PPS) output of external GPS synchronised clock; Pulse control circuit when these two kinds of correcting delay signals are input to the school of firing in sub-oscillograph ISP is simultaneously selected to switch benchmark during as sub-oscillograph data markers and calendar clock school by sub-oscillograph automatically.

5. distributed integration oscillograph mother board as claimed in claim 1 and parallel bus structure; It is characterized in that: said house dog Auto-Sensing and control signal commutation circuit be by the signal leading edge detecting circuit, counter, R-S trigger; Variable connector and failure indicating circuit constitute; The house dog Auto-Sensing of zero groove and control signal commutation circuit be by the signal leading edge detecting circuit, counter 0U3, R-S trigger 0U5, R-S trigger 0U12; 8 the tunnel 2 select 1 variable connector 0U4 to constitute; Wherein, the signal leading edge detecting circuit is made up of d type flip flop 0U1, d type flip flop 0U2, reverse swing door 0U6, NOR gate 0U7, and zero groove failure indicating circuit is by R-S trigger 0U12, reverse swing door 0U13, constitute with a door 0U14.

6. distributed integration oscillograph mother board as claimed in claim 1 and parallel bus structure is characterized in that: calculation control line and computing mode line from each sub-oscillograph are connected to the calculating synchronization control circuit of firing in motherboard ISP through bus plug; Wherein the calculation control line is at first through behind the pairing automatic switch-over circuit of each groove, connects by the mode of logical "or"; Calculate synchronization control circuit by or door 9U1 and d type flip flop 9U7 constitute; The input of 9U1 is promptly from the calculation control line behind each sub-oscillograph slot process automatic switch-over circuit; Its output is connected to the D end of d type flip flop 9U7, and the Q end output of d type flip flop 9U7 then is connected to the computing mode line of each sub-oscillograph slot;

Record value control line and record state of value line from each sub-oscillograph; Record ripple control line and record ripple condition line and definite value control line and definite value condition line are connected respectively to record duty control circuit, record ripple control circuit and the definite value control circuit fired in motherboard ISP then through bus plug; Wherein said record value control line, record ripple control line and 3 kinds of control lines of definite value control line divide into groups to connect by the mode of logical "or" at first through behind the pairing automatic switch-over circuit of each groove then; Said record value, record involve the definite value control circuit by or door and d type flip flop form and to be meant: the record duty control circuit by or door 9U2 and d type flip flop 9U8 form; Record ripple control circuit by or door 9U3 and d type flip flop 9U9 form; The definite value control circuit by or door 9U4 and d type flip flop 9U10 form; Or door 9U2 or door 9U3 and or the input of door 9U4 promptly respectively from each sub-oscillograph slot through the record value control line behind automatic switch-over circuit, record ripple control line and definite value control line; Its output is connected to the D end of d type flip flop 9U8, d type flip flop 9U9 and d type flip flop 9U10 respectively, and the output Q end of d type flip flop 9U8, d type flip flop 9U9 and d type flip flop 9U10 then is connected to record state of value line, record ripple condition line and the definite value condition line of each sub-oscillograph slot respectively;

Said formation synchronization control circuit is reached with a door 9U6 by 8 the 2 preferential automatic switchover links that select 1 variable connector 0U11-7U11 to be constituted to be formed, and wherein the A input of each variable connector all is connected to sub-oscillograph slot through the formation train line behind the automatic switch-over circuit; The B input then is connected to the output Z of the pairing variable connector of next slot; The output Z of zero groove variable connector 0U11 receives and a door 9U6, then is connected to the quene state line of each sub-oscillograph slot respectively with the output of door 9U6; Each variable connector all receives the control of self control end S in the link; When being plugged with sub-oscillograph and this sub-oscillograph on the motherboard slot when in proper working order, S switches to A with Z, otherwise Z is switched to B.

7. distributed integration oscillograph mother board as claimed in claim 1 and parallel bus structure; It is characterized in that: said correcting delay signal treatment circuit divides two parts; Wherein a part of on sub-oscillograph, pulse control circuit and time mark high speed timing circuit when comprising calendar clock chip and firing the inside/outside school in ISP; Another part comprises outside input pulse isolated variable circuit and fires the pulsewidth shaping circuit in motherboard ISP on motherboard, and pulse bus two signal line when bus and GPS school when being integrated in the system school on the motherboard;

Said system reset circuit is divided into two parts, and a part is realized by the ISP on the sub-oscillograph on sub-oscillograph, comprises that electrification reset, software watchdog reset, hardware watchdog resets, power failure resets and the unit hand-reset; The reset signal of sub-oscillograph output is also delivered on the motherboard reset bus through the pin 27C of bus plug simultaneously; Another part of system reset circuit is on motherboard, by the ISP realization of motherboard; Comprise that the multimachine manual synchronization resets and supervisor or far-end reset; Multimachine manual synchronization reset circuit is by general reset button S1, and reverse swing door SU1, NOR gate SU3, d type flip flop SU4, SU6, reverse swing door SU5 reach with the pulse front edge differential circuit of door SU7 composition and with door SU8, NOR gate SU10 and constitute; The pulse of SU10 output is connected on the motherboard reset bus, exports through the triple gate that resets (0U16-7U16) of each groove respectively then; This signal is connected on the reset signal pin of each sub-oscillograph through the pin 27C of each groove bus plug, and completion resets; Supervisor resets or far-end resets is through software control; By exterior I/O input pulse; Pulse front edge differential circuit through the reverse swing door SU2 among the motherboard ISP, NOR gate SU3 and SU4-SU7 composition; Warp and door SU9, NOR gate SU10 output are exported through the triple gate that resets (0U16-7U16) of each groove respectively at last again, and each sub-oscillograph resets.

8. distributed integration oscillograph mother board as claimed in claim 1 and parallel bus structure is characterized in that: integrated RS485 network, RS422 network and SPI synchronous serial network on the said motherboard:

The RS485 net is a looped network, has the control of priority token rings: in the system RS485 serial ports of all sub-oscillographs all the bus plug through separately be connected on the motherboard and realize interconnected through the RS485 bus on the motherboard; The RS485 port of wherein every estrade oscillograph all is a network node that receives Token Control in the network; The RS485 net is fired the control of the priority token rings control circuit in motherboard ISP; The priority token rings control circuit is by the Token Control door (0U10-7U10) that is connected in series and token status detecting gate (0U15-7U15) that is connected in parallel and reverse swing door (MU21) formation; An input of each Token Control door is connected to the Token Control end behind the corresponding slot process automatic switch-over circuit on the motherboard; Another input then links to each other with the output of previous Token Control door; Be also connected to an input of each slot corresponding token state-detection door simultaneously, another input of token status detecting gate is then from the output of reverse swing door (MU21); Every estrade oscillograph has used 3 control ports, and wherein the ROW3 port of ARM is used to export the Token Control signal, and the ROW1 port is used to export the RS485 transmission and enables control signal, and the EGPIO8 port is used to receive the token status signal;

The RS422 net is principal and subordinate's net, in the system RS422 serial ports of all sub-oscillographs all the bus plug through separately be connected with RS422 bus on the motherboard; Send enabled and controlled by output control circuit, output control circuit by supervisor I/O mouth, be installed in the toggle switch on the expansion panel and the decoder 74LS138 that fires in motherboard ISP forms; Wherein the output of supervisor I/O or panel toggle switch is connected to decoder input A0, A1, A2; The transmission that 8 outputs of decoder then are connected to the sub-oscillograph RS422 of 0#-7# serial ports through bus plug respectively enables control end;

SPI synchronous serial net is divided into Intranet and outer net; Intranet is integrated on each sub-oscillograph; Outer net is integrated on the motherboard.

9. distributed integration oscillograph mother board as claimed in claim 1 and parallel bus structure is characterized in that: the large scale integrated chip of installing on the said motherboard is a system programmable CPLD device; Said sub-oscillograph bus slot has totally 8 of 0#-7#, and corresponding integrated sub-oscillograph has totally 8 of 0#-7#; The bus slot of said supervisor has 1, connects a supervisory computer.

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