CN101866930A - Word line-sharing contactless nanocrystalline split gate type flash memory and manufacturing method thereof - Google Patents
Word line-sharing contactless nanocrystalline split gate type flash memory and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a word line-sharing contactless nanocrystalline split gate type flash memory and a manufacturing method thereof. In the obtained flash memory device, two storage bit cells share one word line, different operating voltages are applied to the word line, a first control gate, a second control gate, a first bit line and a second bit line to read, program and erase the storage bit cells, and the bit line-sharing structure enables the split gate type flash memory to effectively reduce the area of a chip under the condition of keeping the electric isolation performance of the chip unchanged and simultaneously can avoid the over-erase problems. Meanwhile, the contactless design enables the flash memory device to have the characteristics of small size and process compatibility with the CMOS traditional process, thereby being beneficial to further reducing the size of the word line-sharing contactless nanocrystalline split gate type flash memory.
Description
Technical field
The present invention relates to semiconductor design and make the field, and be particularly related to a kind of contactless nanocrystalline gate-division type flash memory and manufacture method thereof of shared word line.
Background technology
Flash memory is convenient with it, the storage density height, and advantages such as good reliability become the focus of studying in the non-volatility memorizer.Since first flash memory products comes out from the 1980s, development and the demand of each electronic product along with technology to storing, flash memory is widely used in mobile phone, notebook, palmtop PC and USB flash disk etc. move and communication apparatus in, flash memory is a kind of non-volatility memory, its operation principles is to control the switch of gate pole passage to reach the purpose of storage data by the critical voltage that changes transistor or memory cell, make the data that are stored in the memory can be, and flash memory be a kind of special construction of electric erasable and programmable read-only memory because of power interruptions does not disappear.Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
Yet existing flash memory is in the high storage density of marching toward more, owing to be subjected to the restriction of program voltage, improve storage density by reduction of device size and will face very big challenge, thereby the flash memory of development high storage density is the important motive force of flash memory technology development.Traditional flash memory owing to be subjected to the restriction of structure, realizes that the program voltage of device further reduces to be faced with very big challenge in the high storage density of marching toward more.
Generally speaking, flash memory is the combination of grid dividing structure or stacking gate structure or two kinds of structures.Gate-division type flash memory is because its special structure, compare the stacking gate flash memory and all embody its particular performances advantage in programming with when wiping, therefore divide grid formula structure owing to have high programming efficiency, the structure of word line can be avoided advantages such as " cross and wipe ", uses particularly extensive.Thereby but since gate-division type flash memory with respect to the stacking gate flash memory many a word line make area of chip also can increase, the size that therefore how further reduces chip in the raising chip performance is to need the problem of solution badly.
Simultaneously, along with the memory device size is constantly dwindled continuous rising with storage density, the size that is formed at the contact hole in the inner layer dielectric layer also can become littler, yet this inner layer dielectric layer must keep rational thickness, make this contact hole need keep sizable depth-to-width ratio (depth/width), thereby make the contact point on the Semiconductor substrate occupy the sizable ratio of whole memory unit area, become the key factor that restriction memory device size and storage density further develop.
Summary of the invention
The present invention proposes a kind of contactless nanocrystalline gate-division type flash memory and manufacture method thereof of shared word line, its flush memory device that obtains can be under the constant situation of the electric isolation performance that keeps chip, dwindle area of chip effectively, also can avoid the problem of wiping simultaneously.
In order to achieve the above object, the present invention proposes a kind of contactless nanocrystalline gate-division type flash memory of shared word line, comprising:
Semiconductor substrate has the source region and the drain region that are provided with at interval on it;
Channel region is between described source region and drain region;
First bit line and second bit line are connected to described source region and drain region;
First nano-crystal floating gate is arranged at described channel region and source region top;
Second nano-crystal floating gate is arranged at described channel region and drain region top, and described first nano-crystal floating gate and second nano-crystal floating gate constitute first storage bit unit and second storage bit unit respectively;
First control gate and second control gate are arranged at described first nano-crystal floating gate and second nano-crystal floating gate top respectively;
Word line, above the described channel region and between described first nano-crystal floating gate and second nano-crystal floating gate, described word line both sides have arcuate structure and extend to described first bit line and second bit line top, and are connected with the second bit line top with described first bit line by insulating barrier.
Further, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied first storage bit unit and read voltage, realize that first storage bit unit reads.
Further, first storage bit unit that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 2V, 4V, 0V and 0.8V, realizes that first storage bit unit reads.
Further, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied second storage bit unit and read voltage, realize that second storage bit unit reads.
Further, second storage bit unit that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 4V, 2V, 0.8V and 0V, realizes that second storage bit unit reads.
Further, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the first storage bit unit program voltage, realize the programming of first storage bit unit.
Further, the first storage bit unit program voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 1.4V, 10V, 4V, 5V and 0V, realizes the programming of first storage bit unit.
Further, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the second storage bit unit program voltage, realize the programming of second storage bit unit.
Further, the second storage bit unit program voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 1.4V, 4V, 10V, 0V and 5V, realizes the programming of second storage bit unit.
Further, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the storage bit unit erasing voltage, realize that first storage bit unit and second storage bit unit wipe.
Further, the storage bit unit erasing voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 10.5V, 0V, 0V, 10.5V and 10.5V, realizes that first storage bit unit and second storage bit unit wipe.
In order to achieve the above object, the present invention also proposes a kind of contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line, comprises the following steps:
Semi-conductive substrate is provided, and deposits first oxide layer, floating boom nanometer crystal layer, second oxide layer, control gate polysilicon layer and silicon nitride layer successively;
Described silicon nitride layer is carried out dry etching until exposing described control gate polysilicon layer, form a plurality of grooves;
Described control gate polysilicon layer in the described groove is carried out dry etching, and further described second oxide layer of etching is until exposing described floating boom nanometer crystal layer;
Form the first side wall oxide skin(coating) in described recess sidewall deposition;
Described floating boom nanometer crystal layer in the described groove is carried out dry etching, and further described first oxide layer of etching is until exposing described Semiconductor substrate;
The Semiconductor substrate of bottom portion of groove is carried out ion inject, form bit line;
Form the second side wall oxide skin(coating) in described recess sidewall deposition;
At said structure surface deposition bit line polysilicon, to described bit line polysilicon grind and further dry etching reduce to below the described groove end face until the height of described bit line polysilicon;
At said structure surface deposition insulating barrier, and it is ground until filling up described groove;
Wet etching is removed described silicon nitride layer, and at said structure surface deposition the 3rd side wall oxide skin(coating);
Described the 3rd side wall oxide skin(coating) is carried out dry etching form first side wall, and further dry etching is removed part control gate polysilicon layer and part second oxide layer until exposing described floating boom nanometer crystal layer;
At said structure surface deposition the 4th side wall oxide, it is carried out dry etching form second side wall, and further dry etching is removed part floating boom nanometer crystal layer and wet etching part first oxide layer until exposing described Semiconductor substrate;
Deposition tunneling oxide layer and word line polysilicon on said structure.
Further, described first thickness of oxide layer is more than or equal to 40 dusts.
Further, the thickness of described floating boom nanometer crystal layer is 50 dusts～200 dusts.
Further, described second thickness of oxide layer is more than or equal to 100 dusts.
Further, the thickness of described control gate polysilicon layer is more than or equal to 600 dusts.
Further, the thickness of described silicon nitride layer is 2000 dusts～6000 dusts.
Further, the thickness of the described first side wall oxide skin(coating) is more than or equal to 1500 dusts.
Further, the thickness of the described second side wall oxide skin(coating) is more than or equal to 500 dusts.
Further, the thickness of described bit line polysilicon is more than or equal to 1900 dusts.
Further, the thickness of described insulating barrier is more than or equal to 4000 dusts.
Further, the thickness of described the 4th side wall oxide is more than or equal to 500 dusts.
Further, the thickness of described tunneling oxide layer is more than or equal to 100 dusts.
Further, the thickness of described word line polysilicon is more than or equal to 1900 dusts.
The contactless nanocrystalline gate-division type flash memory and the manufacture method thereof of the shared word line that the present invention proposes, the flush memory device that obtains is shared two storage bit unit and is used a word line, realize reading, programming and wiping by word line, first control gate, second control gate, first bit line and second bit line being applied different operating voltages to storage bit unit, the structure of share bit lines make gate-division type flash memory its can be under the constant situation of the electric isolation performance that keeps chip, dwindle area of chip effectively, also can avoid the problem of wiping simultaneously.Adopt contactless design simultaneously, it is little to make that flush memory device has size, and the characteristics of technology and CMOS traditional handicraft compatibility help device size and further dwindle.
Description of drawings
Figure 1 shows that the contactless nanocrystalline gate-division type flash memory structural representation of the shared word line of preferred embodiment of the present invention.
Fig. 2～Figure 13 shows that contactless nanocrystalline manufacturing method of split-gate type flash memory schematic diagram of the shared word line of preferred embodiment of the present invention.
Embodiment
In order more to understand technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
The present invention proposes a kind of contactless nanocrystalline gate-division type flash memory and manufacture method thereof of shared word line, its flush memory device that obtains can be under the constant situation of the electric isolation performance that keeps chip, dwindle area of chip effectively, also can avoid the problem of wiping simultaneously.
Please refer to Fig. 1, Figure 1 shows that the contactless nanocrystalline gate-division type flash memory structural representation of the shared word line of preferred embodiment of the present invention.The present invention proposes a kind of contactless nanocrystalline gate-division type flash memory of shared word line, comprising: Semiconductor substrate 10 has the source region 11 and the drain region 12 that are provided with at interval on it; Channel region 13 is between described source region 11 and drain region 12; First bit line 21 and second bit line 22 are connected to described source region 11 and drain region 12; First nano-crystal floating gate 31 is arranged at described channel region 13 and 11 tops, source region; Second nano-crystal floating gate 32 is arranged at described channel region 13 and 11 tops, drain region, and described first nano-crystal floating gate 31 and second nano-crystal floating gate 32 constitute first storage bit unit and second storage bit unit respectively; First control gate 41 and second control gate 42 are arranged at described first nano-crystal floating gate 31 and second nano-crystal floating gate, 32 tops respectively; Word line 50, above the described channel region 13 and between described first nano-crystal floating gate 31 and second nano-crystal floating gate 32, described word line 50 both sides have arcuate structure 51,52 and extend to described first bit line 21 and second bit line, 22 tops, and are connected with second bit line, 22 tops with described first bit line 21 by insulating barrier 61,62.
The preferred embodiment according to the present invention, first storage bit unit and second storage bit unit that described first nano-crystal floating gate 31 and second nano-crystal floating gate 32 constitute respectively are multi-crystal silicon floating bar.Polysilicon belongs to conductor, and traditional memory all is that the employing polysilicon is a storage medium, and it adopts and the general identical polysilicon of grid, therefore can be good at and the traditional handicraft compatibility; First bit line 21 of the present invention and second bit line 22, be directly connected in described source region 11 and drain region 12 respectively, and the mode that does not need to form contact point by the making contact hole on Semiconductor substrate 10 connects, design with non-contact-point, make flush memory device have littler size, help device size and further dwindle.
In the preferred embodiment of the present invention, there is electric current between source region 11 and drain region 12, to flow in the raceway groove 13, first storage bit unit that described first nano-crystal floating gate 31 and second nano-crystal floating gate 32 constitute respectively and second storage bit unit have or not charge storage can influence size of current in the raceway groove 13, when first storage bit unit that constitutes respectively when described first nano-crystal floating gate 31 and second nano-crystal floating gate 32 and second storage bit unit have electric charge, electric current is very little in the raceway groove 13, when otherwise first storage bit unit that constitutes respectively when described first nano-crystal floating gate 31 and second nano-crystal floating gate 32 and second storage bit unit do not have electric charge, electric current is very big in the raceway groove 13, setting raceway groove 13 interior little current status is " 0 ", setting raceway groove 130 interior current states is " 1 ", first storage bit unit that described like this first nano-crystal floating gate 31 and second nano-crystal floating gate 32 constitute respectively and second storage bit unit have or not the state of charge storage to can be used as differentiation storage " 0 " or " 1 " information state, realize the function that first storage bit unit and the second storage bit unit information stores read.
The preferred embodiment according to the present invention applies first storage bit unit to described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 respectively and reads voltage, realizes that first storage bit unit reads.
Further, first storage bit unit that described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 are applied reads voltage and is respectively 2.5V, 2V, 4V, 0V and 0.8V, realizes that first storage bit unit reads.
The preferred embodiment according to the present invention applies second storage bit unit to described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 respectively and reads voltage, realizes that second storage bit unit reads.
Further, second storage bit unit that described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 are applied reads voltage and is respectively 2.5V, 4V, 2V, 0.8V and 0V, realizes that second storage bit unit reads.
Source-drain electrodes voltage between source region 11 and drain region 12 is enough high, is enough to cause some high energy electron to cross insulation dielectric layer, and enters the storage space unit on the insulation dielectric layer, and this process is called hot electron and injects.And the composition of described insulation dielectric layer is the oxide of silicon or the nitride of silicon, as materials such as silicon dioxide or silicon nitrides, it is between first storage bit unit and second storage bit unit that Semiconductor substrate 10 and described first nano-crystal floating gate 31 and second nano-crystal floating gate 32 constitute respectively.
The preferred embodiment according to the present invention, described respectively word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 apply the first storage bit unit program voltage, realize the programming of first storage bit unit.In the preferred embodiment of the present invention, after applying programing work voltage, there is electronics 12 to flow to source region 11 in the raceway groove 13 from the drain region, portions of electronics is injected in first storage bit unit of described first nano-crystal floating gate, 31 formations by the hot electron injection mode, realizes the programming operation of first storage bit unit.
Further, the first storage bit unit program voltage that described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 are applied is respectively 1.4V, 10V, 4V, 5V and 0V, realizes the programming of first storage bit unit.
The preferred embodiment according to the present invention applies the second storage bit unit program voltage to described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 respectively, realizes the programming of second storage bit unit.In the preferred embodiment of the present invention, after applying programing work voltage, there is electronics 11 to flow to drain region 12 in the raceway groove 13 from the source region, portions of electronics is injected in second storage bit unit of second nano-crystal floating gate, 32 formations by the hot electron injection mode, realizes the programming operation of second storage bit unit.
Further, the second storage bit unit program voltage that described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 are applied is respectively 1.4V, 4V, 10V, 0V and 5V, realizes the programming of second storage bit unit.
The preferred embodiment according to the present invention, respectively described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 are applied the storage bit unit erasing voltage, realize that first storage bit unit and second storage bit unit wipe.Apply under the operating voltage condition at this, be stored in first storage bit unit that described first nano-crystal floating gate 31 and second nano-crystal floating gate 32 constitute respectively and electronics FN (Fowler-Nordheim) under high electric field of second storage bit unit and be tunneling to first bit line 21 and second bit line, 22 ends, flow away by first bit line 21 and second bit line, 22 ends, realize the erase operation of first storage bit unit and second storage bit unit.
The storage bit unit erasing voltage that further described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 is applied is respectively 10.5V, 0V, 0V, 10.5V and 10.5V, realizes that first storage bit unit and second storage bit unit wipe.
The present invention also proposes a kind of contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line, comprises the following steps:
Please refer to Fig. 2, the invention provides semi-conductive substrate 100, and deposit first oxide layer 110, floating boom nanometer crystal layer 120, second oxide layer 130, control gate polysilicon layer 140 and silicon nitride layer 150 successively; Wherein, the thickness of described first oxide layer 110 is more than or equal to 40 dusts, the thickness of described floating boom nanometer crystal layer 120 is 50 dusts～200 dusts, the thickness of described second oxide layer 130 is more than or equal to 100 dusts, the thickness of described control gate polysilicon layer 140 is more than or equal to 600 dusts, and the thickness of described silicon nitride layer 150 is 2000 dusts～6000 dusts.
Please refer to Fig. 3 again, described silicon nitride layer 150 is carried out dry etching until exposing described control gate polysilicon layer 140, form a plurality of grooves 200;
Please refer to Fig. 4, the described control gate polysilicon layer 140 in the described groove 200 is carried out dry etching, and further described second oxide layer 130 of dry etching is until exposing described floating boom nanometer crystal layer 120;
Please refer to Fig. 5, form the first side wall oxide skin(coating) 210 in the side wall deposition of described groove 200, the thickness of the described first side wall oxide skin(coating) 210 is more than or equal to 1500 dusts;
Please refer to Fig. 6 again, the described floating boom nanometer crystal layer 120 in the described groove 200 is carried out dry etching, and further described first oxide layer 110 of wet etching is until exposing described Semiconductor substrate 100;
And the Semiconductor substrate 100 of groove 200 bottoms is carried out ion inject, form bit line;
Then please refer to Fig. 7 and Fig. 8, form the second side wall oxide skin(coating) 220 in described groove 200 side wall deposition, the thickness of the described second side wall oxide skin(coating) 220 is more than or equal to 500 dusts;
And at said structure surface deposition bit line polysilicon 300, the thickness of described bit line polysilicon 300 is more than or equal to 1900 dusts, to described bit line polysilicon 300 grind and further dry etching reduce to below described groove 200 end faces until the height of described bit line polysilicon 300;
Please refer to Fig. 9, at said structure surface deposition insulating barrier 400, the thickness of described insulating barrier 400 is more than or equal to 4000 dusts, and it is ground until filling up described groove 200;
Please refer to Figure 10 again, wet etching is removed described silicon nitride layer 150, and at said structure surface deposition the 3rd side wall oxide skin(coating) 500;
Please refer to Figure 11, described the 3rd side wall oxide skin(coating) 500 is carried out dry etching form first side wall 510, and further dry etching is removed part control gate polysilicon layer 140 and part second oxide layer 130 until exposing described floating boom nanometer crystal layer 120;
Please refer to Figure 12 again, at said structure surface deposition the 4th side wall oxide (not shown), the thickness of described the 4th side wall oxide is more than or equal to 500 dusts, it is carried out dry etching form second side wall 610, and further etching is removed part floating boom nanometer crystal layer 120 and wet etching part first oxide layer 110 until exposing described Semiconductor substrate 100;
Please refer to Figure 13 at last, deposition tunneling oxide layer 700 and word line polysilicon 800 on said structure, and to its expose and dry etching to form word line, the thickness of described tunneling oxide layer 700 is more than or equal to 100 dusts, the thickness of described word line polysilicon 800 is more than or equal to 1900 dusts.
The contactless nanocrystalline gate-division type flash memory and the manufacture method thereof of the shared word line that the present invention proposes, the flush memory device that obtains is shared two storage bit unit and is used a word line, realize reading, programming and wiping by word line, first control gate, second control gate, first bit line and second bit line being applied different operating voltages to storage bit unit, the structure of share bit lines make gate-division type flash memory its can be under the constant situation of the electric isolation performance that keeps chip, dwindle area of chip effectively, also can avoid the problem of wiping simultaneously.Adopt contactless design simultaneously, it is little to make that flush memory device has size, and the characteristics of technology and CMOS traditional handicraft compatibility help device size and further dwindle.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (24)
1. the contactless nanocrystalline gate-division type flash memory of a shared word line is characterized in that, comprising:
Semiconductor substrate has the source region and the drain region that are provided with at interval on it;
Channel region is between described source region and drain region;
First bit line and second bit line are connected to described source region and drain region;
First nano-crystal floating gate is arranged at described channel region and source region top;
Second nano-crystal floating gate is arranged at described channel region and drain region top, and described first nano-crystal floating gate and second nano-crystal floating gate constitute first storage bit unit and second storage bit unit respectively;
First control gate and second control gate are arranged at described first nano-crystal floating gate and second nano-crystal floating gate top respectively;
Word line, above the described channel region and between described first nano-crystal floating gate and second nano-crystal floating gate, described word line both sides have arcuate structure and extend to described first bit line and second bit line top, and are connected with the second bit line top with described first bit line by insulating barrier.
2. the contactless nanocrystalline gate-division type flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied first storage bit unit and read voltage, realize that first storage bit unit reads.
3. the contactless nanocrystalline gate-division type flash memory of shared word line according to claim 2, it is characterized in that, first storage bit unit that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 2V, 4V, 0V and 0.8V, realizes that first storage bit unit reads.
4. the contactless nanocrystalline gate-division type flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied second storage bit unit and read voltage, realize that second storage bit unit reads.
5. the contactless nanocrystalline gate-division type flash memory of shared word line according to claim 4, it is characterized in that, second storage bit unit that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 4V, 2V, 0.8V and 0V, realizes that second storage bit unit reads.
6. the contactless nanocrystalline gate-division type flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the first storage bit unit program voltage, realize the programming of first storage bit unit.
7. the contactless nanocrystalline gate-division type flash memory of shared word line according to claim 6, it is characterized in that, the first storage bit unit program voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 1.4V, 10V, 4V, 5V and 0V, realizes the programming of first storage bit unit.
8. the contactless nanocrystalline gate-division type flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the second storage bit unit program voltage, realize the programming of second storage bit unit.
9. the contactless nanocrystalline gate-division type flash memory of shared word line according to claim 8, it is characterized in that, the second storage bit unit program voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 1.4V, 4V, 10V, 0V and 5V, realizes the programming of second storage bit unit.
10. the contactless nanocrystalline gate-division type flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the storage bit unit erasing voltage, realize that first storage bit unit and second storage bit unit wipe.
11. the contactless nanocrystalline gate-division type flash memory of shared word line according to claim 10, it is characterized in that, the storage bit unit erasing voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 10.5V, 0V, 0V, 10.5V and 10.5V, realizes that first storage bit unit and second storage bit unit wipe.
12. the contactless nanocrystalline manufacturing method of split-gate type flash memory of a shared word line is characterized in that, comprises the following steps:
Semi-conductive substrate is provided, and deposits first oxide layer, floating boom nanometer crystal layer, second oxide layer, control gate polysilicon layer and silicon nitride layer successively;
Described silicon nitride layer is carried out dry etching until exposing described control gate polysilicon layer, form a plurality of grooves;
Described control gate polysilicon layer in the described groove is carried out dry etching, and further described second oxide layer of etching is until exposing described floating boom nanometer crystal layer;
Form the first side wall oxide skin(coating) in described recess sidewall deposition;
Described floating boom nanometer crystal layer in the described groove is carried out dry etching, and further described first oxide layer of etching is until exposing described Semiconductor substrate;
The Semiconductor substrate of bottom portion of groove is carried out ion inject, form bit line;
Form the second side wall oxide skin(coating) in described recess sidewall deposition;
At said structure surface deposition bit line polysilicon, to described bit line polysilicon grind and further dry etching reduce to below the described groove end face until the height of described bit line polysilicon;
At said structure surface deposition insulating barrier, and it is ground until filling up described groove;
Wet etching is removed described silicon nitride layer, and at said structure surface deposition the 3rd side wall oxide skin(coating);
Described the 3rd side wall oxide skin(coating) is carried out dry etching form first side wall, and further dry etching is removed part control gate polysilicon layer and part second oxide layer until exposing described floating boom nanometer crystal layer;
At said structure surface deposition the 4th side wall oxide, it is carried out dry etching form second side wall, and further dry etching is removed part floating boom nanometer crystal layer and wet etching part first oxide layer until exposing described Semiconductor substrate;
Deposition tunneling oxide layer and word line polysilicon on said structure.
13. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, described first thickness of oxide layer is more than or equal to 40 dusts.
14. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, the thickness of described floating boom nanometer crystal layer is 50 dusts～200 dusts.
15. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, described second thickness of oxide layer is more than or equal to 100 dusts.
16. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, the thickness of described control gate polysilicon layer is more than or equal to 600 dusts.
17. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, the thickness of described silicon nitride layer is 2000 dusts～6000 dusts.
18. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, the thickness of the described first side wall oxide skin(coating) is more than or equal to 1500 dusts.
19. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, the thickness of the described second side wall oxide skin(coating) is more than or equal to 500 dusts.
20. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, the thickness of described bit line polysilicon is more than or equal to 1900 dusts.
21. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, the thickness of described insulating barrier is more than or equal to 4000 dusts.
22. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, the thickness of described the 4th side wall oxide is more than or equal to 500 dusts.
23. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, the thickness of described tunneling oxide layer is more than or equal to 100 dusts.
24. the contactless nanocrystalline manufacturing method of split-gate type flash memory of shared word line according to claim 12 is characterized in that, the thickness of described word line polysilicon is more than or equal to 1900 dusts.
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| CN103646949A (en) * | 2013-11-29 | 2014-03-19 | 上海华力微电子有限公司 | Floating gate transistor array and preparation method thereof |
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