CN101866837B - Method for ion diffusion and semiconductor device formation - Google Patents
Method for ion diffusion and semiconductor device formation Download PDFInfo
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- CN101866837B CN101866837B CN200910049561XA CN200910049561A CN101866837B CN 101866837 B CN101866837 B CN 101866837B CN 200910049561X A CN200910049561X A CN 200910049561XA CN 200910049561 A CN200910049561 A CN 200910049561A CN 101866837 B CN101866837 B CN 101866837B
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Abstract
The invention relates to a method for ion diffusion and semiconductor device formation, wherein the ion diffusion method comprises the following steps: implanting ions into a layer to be implanted to form an ion implanted layer; arranging the ion injection layer in an ultrasonic liquid groove to cause the ions to diffuse uniformly. In the invention, the ion injection layer is arranged in the ultrasonic liquid groove so as to cause the ions to diffuse uniformly. Transmission velocity of the ultrasonic is fast in liquid, thus liquid vibration can be generated without needing to raise liquid temperature; driven by the vibration energy, the ions can be diffused uniformly and the diffusion speed is accelerated, thereby reducing technology cost and improving technology efficiency.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device, relate in particular to the method that ions diffusion and semiconductor device form.
Background technology
At present, after the injection ion forms source/drain electrode or metal level injection ion in Semiconductor substrate, need employing thermal anneal process active ions make ions diffusion even, and repair the defective that produces in the ion implantation process.Thermal anneal process is heated rapidly to design temperature with wafer in the given time, carries out short time quick heat treatment method, and heat treatment time needs a few minutes usually, and the temperature of technological requirement is 700～1300 ℃.
Have now and in making the MOS transistor process, adopt thermal anneal process activation injection ion such as Fig. 1 to shown in Figure 3.With reference to figure 1, Semiconductor substrate 100 is provided, be formed with isolation structure 101 in the said Semiconductor substrate 100, the zone between the isolation structure 101 is an active area 102; Dopant ion in the Semiconductor substrate 100 of active area 102 forms dopant well 103; On the Semiconductor substrate 100 of active area 102, form gate dielectric layer 104 and grid 105 successively, said gate dielectric layer 104 constitutes grid structure 106 with grid 105.
As shown in Figure 2, be mask with grid structure 106, in Semiconductor substrate 100, carry out ion and inject formation source/drain electrode extension area 110 in Semiconductor substrate 100; Then, Semiconductor substrate 100 is put into annealing furnace, temperature is increased to 950 ℃, annealing time is 1 second～1 minute, makes ion even diffused in Semiconductor substrate 100 of injection.
As shown in Figure 3, form side wall 112 in grid structure 106 both sides; With side wall 112 and grid structure 106 is mask, in the Semiconductor substrate 100 of grid structure 106 both sides, carries out ion and injects formation source/drain electrode 114.At last, Semiconductor substrate 100 is put into annealing furnace, temperature is increased to 950 ℃, annealing time is 1 second～1 minute, carries out annealing process, makes the ions diffusion of injection even.
Having now at the ion implantation step adopts thermal anneal process to make ions diffusion even later on; Thermal anneal process need be handled under the temperature more than 600 ℃, and annealing time is 1～2 minute, and ion is fully spread; And repair when injecting because of high energy ion, collide formed defective.But because temperature is high, can cause that multiple ion dislocation and displacement are mutual to be substituted, make diffusion after, the CONCENTRATION DISTRIBUTION of ion can't reach the requirement of localization, and the poor stability of ion, has reduced the performance of semiconductor device.
Summary of the invention
The problem that the present invention solves provides the method for a kind of ions diffusion and semiconductor device formation, prevents that the CONCENTRATION DISTRIBUTION of ion from can't reach the requirement of localization, and the poor stability of ion.
For addressing the above problem, the method for a kind of ions diffusion of the present invention comprises: in layer to be injected, inject ion, form ion implanted layer; Ion implanted layer is put into the ultrasonic liquid groove, make ions diffusion even.
Optional, said liquid tank is that tank, alcohol trough, salt content are 3.5% seawater groove.Temperature in the said liquid tank is 0 ℃～30 ℃.
Optional, the speed of ultrasonic wave in liquid tank is 1100m/s～1600m/s.The vibration frequency of ultrasonic liquid groove is 100KHz～200MHz.
Optional, the ions diffusion time is 10 microseconds～20 second.
The present invention also provides a kind of formation method of semiconductor device, comprising: on Semiconductor substrate, form gate dielectric layer and grid successively, said gate dielectric layer and grid constitute grid structure; With the grid structure is mask, in the Semiconductor substrate of grid both sides, carries out ion and injects formation source/drain electrode extension area; The Semiconductor substrate of/drain electrode extension area active with forming is put into the ultrasonic liquid groove, makes ions diffusion even; After the grid structure both sides form side wall, in the Semiconductor substrate of grid structure and side wall both sides, carry out ion and inject formation source/drain electrode; The Semiconductor substrate of/drain electrode active with forming is put into the ultrasonic liquid groove, makes ions diffusion even.
Optional, said liquid tank is that tank, alcohol trough, salt content are 3.5% seawater groove.Temperature in the said liquid tank is 0 ℃～30 ℃.
Optional, the speed of ultrasonic wave in liquid tank is 1100m/s～1600m/s.The vibration frequency of ultrasonic liquid groove is 100KHz～200MHz.
Optional, the ions diffusion time is 10 microseconds～20 second.
Optional, said source/drain electrode extension area or source/drain electrode conduction type is the n type, injecting ion is n type ion.Said n type ion is phosphonium ion or arsenic ion.
Optional, said source/drain electrode extension area or source/drain electrode conduction type is the p type, injecting ion is p type ion.Said p type ion is boron ion, fluorine boron ion or indium ion.
Compared with prior art, the present invention has the following advantages: ion implanted layer is put into the ultrasonic liquid groove, make ions diffusion even.The speed that ultrasonic wave transmits in liquid is fast, and need fluid temperature not raise, and can make liquid produce vibration, and ion can even diffused under the ordering about of vibrational energy, and the diffusion velocity quickening, has reduced the technology cost, has improved process efficiency.
Description of drawings
Fig. 1 to Fig. 3 is the existing sketch map that adopts thermal anneal process in the MOS transistor process that forms;
Fig. 4 is the embodiment flow chart of a kind of ions diffusion method of the present invention;
Fig. 5 is the embodiment flow chart of semiconductor device formation method of the present invention;
Fig. 6 is the sketch map of the present invention's ultrasonic transmission speed in the different liquids groove;
Fig. 7 to Figure 12 is that the present invention forms employing ions diffusion implementation of processes illustration intention in the semiconductor device process.
Embodiment
The present invention puts into the ultrasonic liquid groove with ion implanted layer, makes ions diffusion even.The speed that ultrasonic wave transmits in liquid is fast, and need fluid temperature not raise, and can make liquid produce vibration, and ion can even diffused under the ordering about of vibrational energy, and the diffusion velocity quickening, has reduced the technology cost, has improved process efficiency.
Fig. 4 is the embodiment flow chart of a kind of ions diffusion method of the present invention.As shown in Figure 4, execution in step S1 injects ion in layer to be injected, forms ion implanted layer.
Said layer to be injected can be Semiconductor substrate, metal level or grid etc.Usually, the technology of injection ion can be in the step that forms dopant well, source/drain electrode extension area and source/drain electrode in Semiconductor substrate.
Execution in step S2 puts into the ultrasonic liquid groove with ion implanted layer, makes ions diffusion even.
Said liquid tank is that tank, alcohol trough, salt content are 3.5% seawater groove; Temperature in the liquid tank can be 0 ℃～30 ℃; Wherein, the transmission rate of ultrasonic wave in liquid tank is 1100m/s～1600m/s.The vibration frequency of ultrasonic liquid groove is 100KHz～200MHz.The ions diffusion time is 10 microseconds～20 second.
As shown in Figure 6 as specific embodiment, in liquid tank, put into water, water temperature is placed 0 ℃, at this moment ultrasonic wave transmission rate in tank is 1402m/s; In liquid tank, put into water, when water temperature was made as 20 ℃, ultrasonic wave transmission rate in tank was 1482m/s; And if in liquid tank, put into alcohol, temperature is placed 0 ℃, at this moment the transmission rate of ultrasonic wave in alcohol trough is 1130m/s; If what in liquid tank, put into is that salt content is 3.5% seawater, and temperature is when being set to 20 ℃, and the transmission rate of ultrasonic wave in the seawater groove is 1522m/s.Because the transmission rate of ultrasonic wave in aforesaid liquid is fast, makes the also corresponding quickening of vibration rate of liquid, promote the diffusion velocity of ion in Semiconductor substrate or other rete.
Fig. 5 is the embodiment flow chart of semiconductor device formation method of the present invention.As shown in Figure 5, execution in step S11 forms gate dielectric layer and grid successively on Semiconductor substrate, and said gate dielectric layer and grid constitute grid structure; Execution in step S12 is a mask with the grid structure, in the Semiconductor substrate of grid both sides, carries out ion and injects formation source/drain electrode extension area; Execution in step S13, the Semiconductor substrate of/drain electrode extension area active with forming is put into the ultrasonic liquid groove, makes ions diffusion even; Execution in step S14 after the grid structure both sides form side wall, carries out ion and injects formation source/drain electrode in the Semiconductor substrate of grid structure and side wall both sides; Execution in step S15, the Semiconductor substrate of/drain electrode active with forming is put into the ultrasonic liquid groove, makes ions diffusion even.
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 7 to Figure 12 is that the present invention forms employing ions diffusion implementation of processes illustration intention in the semiconductor device process.As shown in Figure 7, Semiconductor substrate 200 is provided, said Semiconductor substrate 200 can be silicon or silicon-on-insulator (SOI).In Semiconductor substrate, form isolation structure 201, said isolation structure 201 leaves (STI) structure or selective oxidation silicon (LOCOS) isolation structure for shallow trench isolation.Be active area 202 between isolation structure 201, dopant ion in the Semiconductor substrate 200 of active area 202 forms dopant well 203, if form the PMOS transistor, then Doped n-type ion in Semiconductor substrate 200 forms the n dopant well; And if form nmos pass transistor, then doped p type ion in Semiconductor substrate 200 forms the p dopant well.
On the Semiconductor substrate 200 of active area 202, form gate dielectric layer 204 and grid 205 successively, said gate dielectric layer 204 constitutes grid structure 206 with grid 205.The concrete technology that forms is: on Semiconductor substrate 200, form gate dielectric layer 204 with thermal oxidation method or chemical vapour deposition technique; Then on gate dielectric layer 204, form polysilicon layer with chemical vapour deposition technique or low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technology; On polysilicon layer, form photoresist layer, the definition gate pattern; With the photoresist layer is mask, and etch polysilicon layer and gate dielectric layer 204 form grid 205 to exposing Semiconductor substrate; Photoresist layer is removed in ashing.
The material of said gate dielectric layer 204 can be silica (SiO
2) or silicon oxynitride (SiNO) etc.At the following process node of 65nm, the characteristic size of grid is very little, gate dielectric layer 204 preferred high-k (high K) materials.Said hafnium comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.The thickness of gate dielectric layer 204 is that 15 dusts are to 60 dusts.
As shown in Figure 8, be mask with grid structure 206, in the Semiconductor substrate 200 of grid structure 206 both sides, carry out ion 210 and inject formation source/drain electrode extension area 208.
In the present embodiment, forming the PMOS transistor area, what in Semiconductor substrate 200, inject is p type ion, and said p type ion can be the boron ion; The scope of said p type ion implantation energy value is 500eV～1keV; Said p type ion implantation dosage scope is 3E14cm
-2～7E14cm
-2After the annealing, p type ion implantation concentration scope is 5E18cm
-3～1E20cm
-3
Forming nmos transistor region, what in Semiconductor substrate 200, inject is n type ion, and said n type ion can be phosphonium ion or arsenic ion; The scope of said n type ion implantation energy value is 1keV～3keV; Said n type ion implantation dosage scope is 5E14～1E15cm
-2After the annealing, n type ion implantation concentration scope is 1E19cm
-3～1E20cm
-3
As shown in Figure 9; The Semiconductor substrate 200 of/drain extension region 208 active with forming is put into ultrasonic liquid groove 220; Ultrasonic wave makes the liquid vibration in the liquid tank 220, accelerates to inject the diffusion velocity of ion, and makes the ions diffusion of formation source/drain extension region 208 even.Wherein, the temperature in the liquid tank 220 is 0 ℃～30 ℃, and the transmission rate of ultrasonic wave in liquid tank 220 is 1100m/s～1600m/s, and the vibration frequency of ultrasonic liquid groove is 100KHz～200MHz.The ions diffusion time is 10 microseconds～20 second.
In the present embodiment, as shown in Figure 6, in liquid tank, put into water, water temperature is placed 0 ℃, at this moment ultrasonic wave transmission rate in tank is 1402m/s; In liquid tank, put into water, when water temperature was made as 20 ℃, ultrasonic wave transmission rate in tank was 1482m/s; And if in liquid tank, put into alcohol, temperature is placed 0 ℃, at this moment the transmission rate of ultrasonic wave in alcohol trough is 1130m/s; If what in liquid tank, put into is that salt content is 3.5% seawater, and temperature is when being set to 20 ℃, and the transmission rate of ultrasonic wave in the seawater groove is 1522m/s.Because the transmission rate of ultrasonic wave in aforesaid liquid is fast, makes the also corresponding quickening of vibration rate of liquid, promote the diffusion velocity of ion in Semiconductor substrate or other rete.
Then,, form side wall 212 in grid structure 206 both sides with reference to accompanying drawing 10, the material of said side wall can for a kind of in silica, silicon nitride, the silicon oxynitride or they constitute.Optimize execution mode for one as present embodiment; Said side wall is that silica-silicon-nitride and silicon oxide is formed jointly, and concrete technology is: forming first silicon oxide layer, silicon nitride layer and second silicon oxide layer successively with chemical vapour deposition technique or physical vaporous deposition on the Semiconductor substrate 200 and on the grid structure 206; Then, that adopts dry etching eat-backs (etch-back) method etching second silicon oxide layer, silicon nitride layer and first silicon oxide layer to exposing Semiconductor substrate 200 and grid 205 surfaces, forms side wall 212.
Shown in figure 11, be mask with grid structure 206 and side wall 212, in the Semiconductor substrate 200 of grid structure 206 both sides, carry out ion and inject formation source/drain electrode 214.
In the present embodiment, forming the PMOS transistor area, what in Semiconductor substrate 200, inject is p type ion, and like boron ion, fluorine boron ion or indium ion etc., the scope of said ion implantation energy value is 500eV～700eV; The scope of said ion implantation dosage value is 5E14cm
-2～7E14cm
-2
In the present embodiment, forming nmos transistor region, what in Semiconductor substrate 200, inject is n type ion, and like phosphonium ion or arsenic ion etc., the scope of said ion implantation energy value is 1keV～3keV; The scope of said ion implantation dosage value is 5E14cm
-2～1E15cm
-2
Shown in figure 12, the Semiconductor substrate 200 of/drain electrode 214 active with forming is put into ultrasonic liquid groove 220, and ultrasonic wave makes the liquid vibration in the liquid tank 220, accelerates to inject the diffusion velocity of ion, and makes the ions diffusion of formation source/drain electrode 214 even.Wherein, the temperature in the liquid tank 220 is 0 ℃～30 ℃, and the transmission rate of ultrasonic wave in liquid tank 220 is 1100m/s～1600m/s, and the vibration frequency of ultrasonic liquid groove is 100KHz～200MHz.The ions diffusion time is 10 microseconds～20 second.
In the present embodiment, as shown in Figure 6, in liquid tank, put into water, water temperature is placed 0 ℃, at this moment ultrasonic wave transmission rate in tank is 1402m/s; In liquid tank, put into water, when water temperature was made as 20 ℃, ultrasonic wave transmission rate in tank was 1482m/s; And if in liquid tank, put into alcohol, temperature is placed 0 ℃, at this moment the transmission rate of ultrasonic wave in alcohol trough is 1130m/s; If what in liquid tank, put into is that salt content is 3.5% seawater, and temperature is when being set to 20 ℃, and the transmission rate of ultrasonic wave in the seawater groove is 1522m/s.Because the transmission rate of ultrasonic wave in aforesaid liquid is fast, makes the also corresponding quickening of vibration rate of liquid, promote the diffusion velocity of ion in Semiconductor substrate or other rete.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (16)
1. the method for an ions diffusion is characterized in that, comprising:
In layer to be injected, inject ion, form ion implanted layer;
Ion implanted layer is put into the ultrasonic liquid groove, make ions diffusion even.
2. the method for ions diffusion according to claim 1 is characterized in that, said ultrasonic liquid groove is that tank, alcohol trough, salt content are 3.5% seawater groove.
3. like the method for the said ions diffusion of claim 2, it is characterized in that the temperature in the said ultrasonic liquid groove is 0 ℃～30 ℃.
4. the method for ions diffusion according to claim 1 is characterized in that the speed of ultrasonic wave in the ultrasonic liquid groove is 1100m/s～1600m/s.
5. like the method for the said ions diffusion of claim 4, it is characterized in that the vibration frequency of ultrasonic liquid groove is 100KHz～200MHz.
6. the method for ions diffusion according to claim 1 is characterized in that, the ions diffusion time is 10 microseconds～20 second.
7. the formation method of a semiconductor device is characterized in that, comprising:
On Semiconductor substrate, form gate dielectric layer and grid successively, said gate dielectric layer and grid constitute grid structure;
With the grid structure is mask, in the Semiconductor substrate of grid both sides, carries out ion and injects formation source/drain electrode extension area;
The Semiconductor substrate of/drain electrode extension area active with forming is put into the ultrasonic liquid groove, makes ions diffusion even;
After the grid structure both sides form side wall, in the Semiconductor substrate of grid structure and side wall both sides, carry out ion and inject formation source/drain electrode;
The Semiconductor substrate of/drain electrode active with forming is put into the ultrasonic liquid groove, makes ions diffusion even.
8. like the formation method of the said semiconductor device of claim 7, it is characterized in that said ultrasonic liquid groove is that tank, alcohol trough, salt content are 3.5% seawater groove.
9. like the formation method of the said semiconductor device of claim 8, it is characterized in that the temperature in the said ultrasonic liquid groove is 0 ℃～30 ℃.
10. like the formation method of the said semiconductor device of claim 7, it is characterized in that the speed of ultrasonic wave in the ultrasonic liquid groove is 1100m/s～1600m/s.
11. the formation method like the said semiconductor device of claim 10 is characterized in that, the vibration frequency of ultrasonic liquid groove is 100KHz～200MHz.
12. the formation method like the said semiconductor device of claim 7 is characterized in that, the ions diffusion time is 10 microseconds～20 second.
13. the formation method like the said semiconductor device of claim 7 is characterized in that, said source/drain electrode extension area or source/drain electrode conduction type is the n type, and injecting ion is n type ion.
14. the formation method like the said semiconductor device of claim 13 is characterized in that, said n type ion is phosphonium ion or arsenic ion.
15. the formation method like the said semiconductor device of claim 7 is characterized in that, said source/drain electrode extension area or source/drain electrode conduction type is the p type, and injecting ion is p type ion.
16. the formation method like the said semiconductor device of claim 15 is characterized in that, said p type ion is boron ion, fluorine boron ion or indium ion.
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| CN200910049561XA CN101866837B (en) | 2009-04-17 | 2009-04-17 | Method for ion diffusion and semiconductor device formation |
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| CN200910049561XA CN101866837B (en) | 2009-04-17 | 2009-04-17 | Method for ion diffusion and semiconductor device formation |
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| CN101866837B true CN101866837B (en) | 2012-05-23 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6358823B1 (en) * | 2000-04-12 | 2002-03-19 | Institut Fuer Halbleiterphysik Frankfurt (Oder) Gmbh. | Method of fabricating ion implanted doping layers in semiconductor materials and integrated circuits made therefrom |
| CN1441468A (en) * | 2002-02-25 | 2003-09-10 | 旺宏电子股份有限公司 | Method of inhibiting short channel effect in semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6358823B1 (en) * | 2000-04-12 | 2002-03-19 | Institut Fuer Halbleiterphysik Frankfurt (Oder) Gmbh. | Method of fabricating ion implanted doping layers in semiconductor materials and integrated circuits made therefrom |
| CN1441468A (en) * | 2002-02-25 | 2003-09-10 | 旺宏电子股份有限公司 | Method of inhibiting short channel effect in semiconductor device |
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