CN101630642A - Method for manufacturing NMOS transistor - Google Patents
Method for manufacturing NMOS transistor Download PDFInfo
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- CN101630642A CN101630642A CN200810040568A CN200810040568A CN101630642A CN 101630642 A CN101630642 A CN 101630642A CN 200810040568 A CN200810040568 A CN 200810040568A CN 200810040568 A CN200810040568 A CN 200810040568A CN 101630642 A CN101630642 A CN 101630642A
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Abstract
A method for manufacturing an NMOS transistor comprises the following steps: forming a grid structure on a semiconductor substrate; forming an N-type source/drain extension area in the semiconductor substrates on the two sides of the grid structure; forming sidewalls on the two sides of the grid structure; forming an N-type source/drain in the semiconductor substrates on the two sides of the grid structure; and annealing the semiconductor substrate. The method for manufacturing the NOMS transistor simplifies the process sequence, reduces the manufacturing cost and reduces the heat budget of a semiconductor device.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the manufacture method of nmos pass transistor.
Background technology
Along with improving constantly of semiconductor device integrated level; its characteristic size reduces gradually; source/drain electrode and source/drain electrode extension area (Source/Drain Extension) correspondingly shoals; the degree of depth of the source/drain junction of current technological level requirement semiconductor device is less than 1000 dusts, and the degree of depth that finally may require to tie is at 200 dusts or the littler order of magnitude.
At present, the transient enhanced diffusion effect can produce when forming shallow junction, and the transient enhanced diffusion effect influence in follow-up side wall forming process be very big, therefore, usually when making NMOS, with annealing process repeatedly, with transient suppression enhancing diffusion effect.Concrete processing step is as follows:
With reference to shown in Figure 1, Semiconductor substrate 100 is provided, be formed with isolation structure 101 in the described Semiconductor substrate 100, the zone between the isolation structure 101 is a NMOS active area 102; Dopant ion in the Semiconductor substrate 100 of NMOS active area 102 forms P type dopant well 103; Form gate dielectric layer 104 and grid 105 on the Semiconductor substrate 100 of NMOS active area 102 successively, described gate dielectric layer 104 constitutes grid structure 106 with grid 105.
With reference to figure 2, then, be mask with grid structure 106, inject N type ion in the Semiconductor substrate 100, in the P type dopant well 103 of grid structure 106 both sides, form N type source/drain electrode extension area 108; Continuation is a mask with grid structure 106, in Semiconductor substrate 100, carry out bag shape and inject (Pocketimplant), described bag shape is injected the general angle that adopts and is injected between the ion of 0 to 45 degree, form bag shape injection region 110, the conductivity type opposite of the conduction type of described first bag of shape injection region 110 and N type source/drain electrode extension area 108, its degree of depth is between N type source/drain electrode extension area 108 and follow-up source/drain electrode.
The Semiconductor substrate 100 that will have each rete and device is put into annealing furnace 120, and Semiconductor substrate 100 is carried out the annealing first time, makes the ions diffusion of the Semiconductor substrate 100 of injecting NMOS active area 108 even.
Please refer to Fig. 3, form silicon oxide layers 112 in Semiconductor substrate 100 and grid structure 106 peripheries with physical vaporous deposition or chemical vapour deposition technique; Then, the Semiconductor substrate 100 that will have each rete and device is once more put into annealing furnace 120, and Semiconductor substrate 100 is carried out the annealing second time, prevents that the ion that injects Semiconductor substrate 100 from escaping, and eliminates the defective that silicon oxide layer deposited 112 backs form.
With reference to shown in Figure 4, on silicon oxide layer 112, form silicon nitride layer (not shown) with physical vaporous deposition or chemical vapour deposition technique; Silicon nitride layer and silicon oxide layer 112 are carried out etching formation side wall 114; Continuation is a mask with grid structure 106 and side wall 114, injects N type ion in Semiconductor substrate 100, forms N type source/drain electrode 116; The Semiconductor substrate 100 that will have each rete and device is put into annealing furnace 120, and Semiconductor substrate 100 is annealed for the third time, makes the N type ions diffusion of injection even.
In being 6410430 United States Patent (USP), the patent No. can also find more information relevant with technique scheme.
But in above-mentioned technology, carry out transient suppression enhancing diffusion effect by increasing thermal anneal process, annealing temperature is 900 ℃～1100 ℃, time is 1～10 second, so annealing under the high temperature, although annealing time is shorter, the heat budget that increases meeting increase semiconductor device of annealing number of times, and make processing step complicated, greatly increased the technology manufacturing cost.Even more serious is that complicated having increased of such annealing process injected the uncertainty that ion distributes again, makes that the short-channel effect in the device scaled down process is difficult to control more.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of nmos pass transistor, prevents complex manufacturing technology, technology cost height.
For addressing the above problem, the invention provides a kind of manufacture method of nmos pass transistor, comprise the following steps: on Semiconductor substrate, to form grid structure; In the Semiconductor substrate of grid structure both sides, form N type source/drain extension region; Form side wall in the grid structure both sides; In the Semiconductor substrate of grid structure both sides, form N type source/drain electrode; Semiconductor substrate is annealed.
Optionally, describedly be annealed into pulse annealing.Described annealing temperature is 1000 ℃ to 1100 ℃, and the time is 1 to 10 second.Described annealing temperature is 1070 ℃, and the time is 1.5 seconds.
Optionally, the step of described formation side wall comprises: form silicon oxide layer and silicon nitride layer on Semiconductor substrate successively; Etching oxidation silicon layer and silicon nitride layer.
Optionally, after formation source/drain extension region step, also be included in and form a bag shape injection region in the Semiconductor substrate of grid structure both sides.The degree of depth of described bag shape injection region between source/drain extension region and source/drain electrode, the conduction type of described bag of shape injection region and the conductivity type opposite of source/drain extension region or source/drain electrode.
Compared with prior art, such scheme has the following advantages: after forming N type source/drain extension region, silicon oxide layer and N type source/drain electrode, Semiconductor substrate is once annealed.Processing step is simplified, reduced manufacturing cost; Simultaneously, only once anneal, reduced the heat budget of semiconductor device; Simplify the annealing process step and reduced the uncertainty that the injection ion distributes again, controlled the short-channel effect in the device scaled down process.
Description of drawings
Fig. 1 to Fig. 4 is the schematic diagram that existing technology forms nmos pass transistor;
Fig. 5 is the embodiment flow chart that the present invention forms nmos pass transistor;
Fig. 6 to Figure 10 is the embodiment schematic diagram that the present invention forms nmos pass transistor;
Figure 11 is a relation between the shutoff leakage current (Ioff) of prior art and nmos pass transistor of the present invention and the saturation drive current (Idsat);
Figure 12 is near the ion doping concentration profile of source/drain electrode extension area of the present invention and prior art.
Embodiment
The present invention once anneals to Semiconductor substrate after forming N type source/drain extension region, silicon oxide layer and N type source/drain electrode.Processing step is simplified, reduced manufacturing cost; Simultaneously, only once anneal, reduced the heat budget of semiconductor device; Simplify the annealing process step and reduced the uncertainty that the injection ion distributes again, controlled the short-channel effect in the device scaled down process.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 5 is the embodiment flow chart that the present invention forms nmos pass transistor.As shown in Figure 5, execution in step S101 forms grid structure on Semiconductor substrate; Execution in step S102 forms N type source/drain extension region in the Semiconductor substrate of grid structure both sides; Execution in step S103 forms side wall in the grid structure both sides; Execution in step S104 forms N type source/drain electrode in the Semiconductor substrate of grid structure both sides; Execution in step S105 anneals to Semiconductor substrate.
Fig. 6 to Figure 10 is the embodiment schematic diagram that the present invention forms nmos pass transistor.With reference to accompanying drawing 6, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 can be silicon or silicon-on-insulator (SOI); Form isolation structure 201 in Semiconductor substrate, described isolation structure 201 is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Be NMOS active area 202 between isolation structure 201, dopant ion in the Semiconductor substrate 200 of NMOS active area 202 forms P type dopant well 203.
Form gate dielectric layer 204 and grid 205 on the Semiconductor substrate 200 of NMOS active area 202 successively, described gate dielectric layer 204 constitutes grid structure 206 with grid 205.The concrete technology that forms is: form gate dielectric layer 204 with thermal oxidation method or chemical vapour deposition technique on Semiconductor substrate 200; Then on gate dielectric layer 204, form polysilicon layer with chemical vapour deposition technique or low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technology; On polysilicon layer, form photoresist layer, the definition gate pattern; With the photoresist layer is mask, and etch polysilicon layer and gate dielectric layer 204 form grid 205 to exposing Semiconductor substrate; Photoresist layer is removed in ashing.
The material of described gate dielectric layer 204 can be silica (SiO
2) or silicon oxynitride (SiNO) etc.At the following process node of 65nm, the characteristic size of grid is very little, gate dielectric layer 204 preferred high-k (high K) materials.Described hafnium comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.The thickness of gate dielectric layer 204 is that 15 dusts are to 60 dusts.
In the present embodiment, form after the grid structure 206, can also be at the described grid structure 206 peripheral processing steps that form insulation material layer, described insulation material layer is silica for example, silicon nitride, silicon oxynitride etc., preferably, described insulation material layer is a silica.Described insulation material layer is used for the edge of grill-protected electrode structure 206, avoids taking place oxidation.
As shown in Figure 7, be mask with grid structure 206, in the Semiconductor substrate 200 of grid structure 206 both sides, carry out ion 210 and inject, form N type source/drain electrode extension area 208.Then, continuation is a mask with grid structure 206, in Semiconductor substrate 200, carry out bag shape and inject (Pocket implant), described bag shape is injected the general angle that adopts and is injected between the ion of 0 to 45 degree, form bag shape injection region 210, the conductivity type opposite of the conduction type of described first bag of shape injection region 210 and N type source/drain electrode extension area 208, its degree of depth is between N type source/drain electrode extension area 208 and follow-up source/drain electrode; Described bag shape injection technology can be used for improving the short-channel effect and the punch-through effect (punch through) of device.
In the present embodiment, what inject in Semiconductor substrate 200 is n type ion, and described n type ion can be phosphonium ion or arsenic ion; The scope of described n type ion implantation energy value is 1keV～3keV, concrete example such as 1keV, 1.5keV, 2keV, 2.5keV or 3keV etc.Described n type ion implantation dosage scope is 5E14～1E15cm
-2, concrete example such as 5E14cm
-2, 6E14cm
-2, 7E14cm
-2, 8E14cm
-2, 9E14cm
-2Or 1E15cm
-2Deng.
With reference to accompanying drawing 8, form silicon oxide layers 212 in Semiconductor substrate 200 and grid structure 206 peripheries with chemical vapour deposition technique or physical vaporous deposition; On silicon oxide layer 212, form silicon nitride layer 214 with chemical vapour deposition technique or physical vaporous deposition then.
In the present embodiment, the thickness of described silicon oxide layer 212 is 5nm～10nm, and concrete thickness is 5nm, 6nm, 7nm, 8nm, 9nm or 10nm etc. for example, preferred 7nm.
The thickness of silicon nitride layer 214 is 20nm～30nm, and concrete thickness is 20nm, 22nm, 24nm, 26nm, 28nm or 30nm etc. for example, preferred 26nm.
As shown in Figure 9, adopt dry etching eat-back (etch-back) method etches both silicon nitride layer 214 and silicon oxide layer 212 after, form side wall 216 in grid structure 206 both sides.
Then, be mask with grid structure 206 and side wall 216, in the Semiconductor substrate 200 of grid structure 206 both sides, carry out ion and inject, form N type source/drain electrode 218.
In the present embodiment, what inject in Semiconductor substrate 200 is n type ion, and as phosphonium ion or arsenic ion etc., the scope of described ion implantation energy value is 1keV～3keV; The scope of described ion implantation dosage value is 5E14cm
-2～1E15cm
-2
As shown in figure 10, last, the Semiconductor substrate 200 that will have each rete and device is put into annealing furnace 220, and Semiconductor substrate 200 is carried out annealing in process, makes the ions diffusion of injection even.
In the present embodiment, describedly be annealed into pulse annealing.Described annealing temperature is 1000 ℃ to 1100 ℃, for example 1000 ℃, 1010 ℃, 1020 ℃, 1030 ℃, 1040 ℃, 1050 ℃, 1060 ℃ 1070 ℃, 1080 ℃, 1090 ℃ of actual temps or 1100 ℃ etc.; Annealing time is 1 to 10 second, and concrete example is as 1 second, 2 seconds, 3 seconds, 4 seconds, 5 seconds, 6 seconds, 7 seconds, 8 seconds, 9 seconds or 10 seconds etc.As the preferred version of present embodiment, optional 1070 ℃ of annealing temperature, annealing time is 1.5 seconds.
In the present embodiment, after forming N type source/drain extension region 208, bag shape injection region 210, silicon oxide layer 212 and N type source/drain electrode 218, Semiconductor substrate 200 is once annealed, make the ions diffusion of injection even.Processing step is simplified, and has reduced manufacturing cost; Simultaneously, only once anneal the heat budget of the semiconductor device of reduction.
Figure 11 is a relation between the shutoff leakage current (Ioff) of prior art and nmos pass transistor of the present invention and the saturation drive current (Idsat).The present invention is when forming nmos pass transistor, relation is shown in curve II between the shutoff leakage current (Ioff) of nmos pass transistor and the saturation drive current (Idsat), wherein curve II correspondence is after forming N type source/drain electrode, just Semiconductor substrate is carried out annealing in process, annealing temperature is 1070 ℃, and annealing time adopted 10 seconds.Simultaneously, Figure 15 also is given in the shutoff leakage current (Ioff) of the nmos pass transistor after prior art is repeatedly annealed and the relation curve (curve I) between the saturation drive current (Idsat) in forming the nmos pass transistor process.As can be seen from Figure 15, the present invention is by the optimization to the annealing number of times, and down it turn-offs the cut-off current that leakage current (Ioff) all is lower than the nmos pass transistor that the repeatedly annealing of prior art forms to same saturation drive current (Idsat).The turn-off characteristic that has proved the nmos pass transistor that forms with method of the present invention improves obviously, helps reducing the leakage current of nmos pass transistor.
Figure 12 is near the ion doping concentration profile of source/drain electrode extension area of the present invention and prior art, and wherein, ordinate is the concentration (Log (Arsenic)) of lightly-doped source/drain electrode extension area arsenic ion, and abscissa Y is the fore-and-aft distance along Semiconductor substrate. is as shown in figure 12; The hole (shown in the double dot dash line) that mixes between the N-type source of the nmos pass transistor that forms with single annealing process of the present invention/drain extension region arsenic ion is larger than the hole (shown in the chain-dotted line) that mixes between the N-type source of the nmos pass transistor that forms with annealing process repeatedly with prior art/drain extension region arsenic ion, and the N-type source of the nmos pass transistor that forms with single annealing process of the present invention/drain extension region arsenic ion doping content (shown in the dotted line) is than the N-type source of the nmos pass transistor that forms with annealing process repeatedly with prior art/not exclusively coincidence of drain extension region arsenic ion doping content (shown in the solid line). But this can change by the injection degree of depth and the pressure that changes dopant ion, and therefore the nmos pass transistor that forms with annealing process of the present invention can not produce defective because of the improvement of annealing number of times.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (7)
1. the manufacture method of a nmos pass transistor is characterized in that, comprises the following steps:
On Semiconductor substrate, form grid structure;
In the Semiconductor substrate of grid structure both sides, form N type source/drain extension region;
Form side wall in the grid structure both sides;
In the Semiconductor substrate of grid structure both sides, form N type source/drain electrode;
Semiconductor substrate is annealed.
2. the manufacture method of nmos pass transistor according to claim 1 is characterized in that, describedly is annealed into pulse annealing.
3. the manufacture method of nmos pass transistor according to claim 2 is characterized in that, described annealing temperature is 1000 ℃ to 1100 ℃, and the time is 1 to 10 second.
4. the manufacture method of nmos pass transistor according to claim 3 is characterized in that, described annealing temperature is 1070 ℃, and the time is 1.5 seconds.
5. the manufacture method of nmos pass transistor according to claim 1 is characterized in that, the step of described formation side wall comprises:
On Semiconductor substrate, form silicon oxide layer and silicon nitride layer successively;
Etching oxidation silicon layer and silicon nitride layer.
6. the manufacture method of nmos pass transistor according to claim 1 is characterized in that, also is included in after formation source/drain extension region step and forms a bag shape injection region in the Semiconductor substrate of grid structure both sides.
7. the manufacture method of nmos pass transistor according to claim 6, it is characterized in that, the degree of depth of described bag shape injection region between source/drain extension region and source/drain electrode, the conduction type of described bag of shape injection region and the conductivity type opposite of source/drain extension region or source/drain electrode.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012097606A1 (en) * | 2011-01-17 | 2012-07-26 | 复旦大学 | Method of manufacturing field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012097606A1 (en) * | 2011-01-17 | 2012-07-26 | 复旦大学 | Method of manufacturing field effect transistor |
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Open date: 20100120 |