CN101853840A - Structure of embedded line substrate and manufacturing method thereof - Google Patents

Structure of embedded line substrate and manufacturing method thereof Download PDF

Info

Publication number
CN101853840A
CN101853840A CN 200910133258 CN200910133258A CN101853840A CN 101853840 A CN101853840 A CN 101853840A CN 200910133258 CN200910133258 CN 200910133258 CN 200910133258 A CN200910133258 A CN 200910133258A CN 101853840 A CN101853840 A CN 101853840A
Authority
CN
China
Prior art keywords
resin
substrate
resin bed
central core
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN 200910133258
Other languages
Chinese (zh)
Other versions
CN101853840B (en
Inventor
唐心陆
李德章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN 200910133258 priority Critical patent/CN101853840B/en
Publication of CN101853840A publication Critical patent/CN101853840A/en
Application granted granted Critical
Publication of CN101853840B publication Critical patent/CN101853840B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Structure Of Printed Boards (AREA)

Abstract

The invention discloses a manufacturing method of an embedded line substrate, comprises the following steps: providing a substrate; arranging a through hole penetrating through the substrate and a plurality of trenches arranged on the upper surface and the lower surface of the substrate; carrying out one-plating step on the substrate to fully plate a conductive material on the through hole and the trenches simultaneously, wherein the substrate is a thick resin substrate and comprises a center layer, a first resin layer and second layer, the first resin layer and the second layer which are with a certain thickness are arranged on the upper surface and the lower surface of the center layer, and the trenches are arranged on the first resin layer and the second resin layer; and the conductive material filled in the trenches is respectively flush with the surfaces of the first resin layer and the second resin layer.

Description

The structure of embedded line substrate and manufacture method thereof
Technical field
The invention relates to a kind of structure and manufacture method thereof of embedded line substrate, and particularly relevant for a kind of structure and manufacture method thereof with embedded line substrate of thick resin substrate.
Background technology
Integrated circuit (IC) structure packing technique is a ring important in the electronic industry, and the main function of electronic packaging is protection, support, line configuring and produces the heat radiation approach, and modularization of part and specification standards are provided.Nineteen ninety generation mainly be utilize the ball bar array (Ball Grid Array, packaged type BGA) carries out electronic packaging, its advantage is that thermal diffusivity is good and electrically good, pin count can roll up, and can effectively dwindle the packaging body area.
Yet, along with global personal computer, consumption electronic products and communication product constantly require compactly more will possess under the dynamical trend, the desired electrical characteristic of chip not only will be better, and overall volume is littler, but the number at I/O port is up to improve.Along with I/O quantity increases, integrated line pitch is dwindled, want on the BGA substrate, to arrange expeditiously that cabling becomes difficult, for example in point 18 technologies (live width 0.18 μ m) or the IC design of high speed (more than 800MHz), the trend that significantly increases I/O density is arranged.And cover one of structure dress mode that crystalline substance (Flip Chip) technology just can head it off, its have high I/O and good electrically, become one of main flow trend of support plate development now.Crystal covered carrier-board has been the product item that each support plate factory falls over each other to invest after 2006, and each downstream product has reached certain level to the employing rate of crystal covered carrier-board.Moreover, except that the demand of Flip Chip, the requirement of downstream product system combinationization will become clear day by day, so multi-chip module (Multi-chip Module, MCM) technology also will significantly improve the demand of MCM support plate, be expected together to become with crystal covered carrier-board the growth potentiality product in market.
And the microelectronics system demand that increases fast (particularly integrating the gain part about system size and chip) has also more been quickened chip-scale encapsulation (Chip Scale Packaging, CSP) employing of technology.Similarly be that the glutinous packing technique in surface (surface-mount packaging technology is called for short SMT) defeats Through-Hole Technology (through-hole technology) the same in the past gradually, the CSP technology also will replace the technology of SMT at present gradually.
Maturation along with chip-scale encapsulation (CSP) technology, pursue system type semiconductor packages mode-system in package (System in Package of performance and cost, SiP) also become the main flow of encapsulation technology, mainly be because the size of product is more and more littler, function is got over various, must use the SiP technology to satisfy the demand in market.System in package SiP has comprised chip (chip) or passive component (Passive Components) or other module has been carried out the structure dress.System in package has also comprised the multi-chip module encapsulation of different technologies such as PiP (Package in Package), PoP (Package on Package), plane or for saving the 3D storehouse encapsulation that area gets up difference in functionality chip stack (Stack), these all belong to the development category of system in package (SiP) technology, and the encapsulation of which kind of kenel of this usefulness is also looked application demand and difference to some extent.Therefore the definition of SiP is very extensive.In system in package (SiP) technology, employed joining technique also has a variety of, for example is that routing connects (Wire bonding), crystal covering type (Flip Chip) engages and use multiple joining technique (Hybrid-type) or the like.
With the naked crystalline substance of system in package (System in Package) is example, it can be with the naked crystalline substance of different digital or analog functuion, be linked on the chip support plate with projection (bump) or routing (wire bond) mode, bury passive component or line design in the existing part in this support plate, the support plate that this has electrical functionality is called conformability substrate (Integrated Substrate) or functional base plate (Functional Substrate).Please refer to Fig. 1, it illustrates a kind of schematic diagram of conformability substrate of traditional embedded line.Conventional substrate as shown in Figure 1 is that the upper and lower surface at a central core (core) 11 respectively forms first conductive layer 12 and second conductive layer 13, and the material of conductive layer for example is a metallic copper, and patterned conductive layer is to form the required line pattern of conformability substrate again.Therefore the material of central core 11 for example is that glass fibre and resin are formed, and glass fibre is soaked in resin liquid, and formed central core 11 is that the glass fibre staggered just like graticule mixes with the resin impregnation and form.And can on first conductive layer 12, for example form through hole (Via) 121 and 122 behind the patterned conductive layer, on second conductive layer 13, for example form through hole 131,132 and groove (trench) 133.Yet, its conductive pattern of conformability substrate of this kind aspect is to protrude in outside the central core 11, make the upper and lower surface of whole base plate present roughness, moreover the thickness of whole (comprising central core 11 and first and second conductive layer 12 and 13) is thicker, under this kind structure, to make the possibility of substrate thinning very little again, therefore be unfavorable for being applied on the miniature dimensions product.The demand lightening along with the size of application product and external form is more and more higher, and this kind has the demand that certain thickness conventional substrate structure can't meet market product in fact.
Summary of the invention
The present invention is relevant for a kind of structure and manufacture method thereof of embedded line substrate, and it carries out the substrate manufacturing with a thick resin substrate, with the board structure of formation tool flat surfaces, and the integral thickness reduction, meet high function of market product and lightening demand.
According to the present invention, a kind of manufacture method of embedded line substrate is proposed, comprising: a substrate is provided; Form a through hole (through hole) and several grooves (trench) at the substrate place, and through hole runs through substrate, those grooves then are formed at the upper surface and the lower surface place of substrate; With substrate is once electroplated (one-plating step), make through hole and those grooves plate a full electric conducting material simultaneously.
According to the present invention, (Thick Resin Core TRC), comprises a central core (central core), one first resin bed and one second resin bed to propose a kind of thick resin substrate.Central core has at least one glass fiber resin layer, and the thickness of glass fiber resin layer is about 10 μ m~50 μ m.First and second resin bed is formed at the upper and lower surface of central core respectively, and thickness is about 10 μ m~50 μ m respectively.
According to the present invention, the board structure on the road that proposes to sunken cord in a kind of two-layer comprises a central core, one first resin bed, one second resin bed and an electric conducting material.Central core comprises a glass fiber resin layer.First and second resin bed is formed at the upper and lower surface of central core respectively, and first, second resin bed place has several grooves.Electric conducting material is filled in those grooves, and the electric conducting material that is positioned at those grooves respectively with the flush of first, second resin bed.
According to the present invention, a kind of structure of embedded line substrate is proposed, comprise board structure, first and second solder layer and one second electric conducting material of a tool first electric conducting material.Wherein, board structure comprises a central core and is formed at one first resin bed and one second resin bed of central core upper and lower surface, and first, second resin bed place has several grooves.First electric conducting material is filled in those grooves, and first electric conducting material that is positioned at groove respectively with the flush of first, second resin bed.First, second solder layer is formed at respectively on first, second resin bed, and has several holes respectively to expose the part surface of first electric conducting material.Then be formed at those hole places of first, second solder layer as for second electric conducting material.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 illustrates a kind of schematic diagram of conformability substrate of traditional embedded line.
Fig. 2 A~2G illustrates the manufacture method of the embedded line substrate of one embodiment of the invention.
Fig. 3 illustrates the local enlarged diagram according to the thick resin substrate of a preferred embodiment of the present invention.
The primary clustering symbol description:
11: central core
12: the first conductive layers
13: the second conductive layers
121,122,131,132: through hole
20: thick resin substrate
201,301: central core
203,303: the first resin beds
205: the second resin beds
21a: the upper surface of substrate 20
21b: the lower surface of substrate 20
22: through hole
23a~23d, 25a~25c: groove
26: electric conducting material
206: the first solder layers
207: the second solder layers
208a~208c: metal level
Embodiment
The present invention proposes a kind of structure and manufacture method thereof of embedded line substrate, mainly be on a kind of surface of thick resin substrate, directly to carry out patterning step, as form through hole (through hole) and groove (trench), and utilize (one-plating step) mode of once electroplating, make through hole and groove plate a full electric conducting material simultaneously, carrying out subsequent treatment afterwards flushes electric conducting material and substrate surface in through hole and the groove, through solder layer with after suitably surface treatment is processed, finish the manufacturing of embedded line substrate of the present invention again.According to embedded line substrate proposed by the invention, not only integral thickness can reduce, and substrate surface smooth (not having the line pattern of projection), the therefore demand of very suitable small size application product.
The following embodiment that proposes according to the present invention is to describe the manufacture method of embedded line substrate of the present invention in detail.Yet the method that is proposed among the embodiment is the usefulness for illustrating only, is not the usefulness as limit protection range of the present invention.Moreover the icon of embodiment only illustrates the associated component of the technology of the present invention, omits unnecessary assembly, with clear demonstration technical characterstic of the present invention.
Please refer to Fig. 2 A~2G, it illustrates the manufacture method of the embedded line substrate of one embodiment of the invention.At first, provide a thick resin substrate (Thick Resin Core, TRC) 20, shown in Fig. 2 A.Thick resin substrate 20 comprises a central core (central core) 201,1 first resin bed 203 and one second resin bed 205.Central core 201 comprises the layer of glass resin bed at least, and its thickness is about 10 μ m~50 μ m.Actual required the adjusting of the visual application of the glass fiber resin number of plies, for example the glass fiber resin layer of 2 layers or 3 layers is as central core 201.First resin bed 203 and second resin bed 205 are formed at the upper surface and the lower surface of central core 201 respectively, and the thickness of first, second resin bed 203,205 is about 10 μ m~50 μ m respectively.When central core 201 has only the single glass fiber reinforced resin layer and has the about 10 μ m of minimal thickness, when first, second resin bed 203,205 also is respectively the about 10 μ m of minimal thickness, the gross thickness of the thick resin substrate 30 μ m that only have an appointment.When having triplex glass fiber reinforced resin layer and every layer, central core 201 has the about 50 μ m of thickness, when first, second resin bed 203,205 also has the about 50 μ m of thickness respectively, and the gross thickness of the thick resin substrate 250 μ m that have an appointment.Therefore, the total thickness of thick resin substrate is about 30 μ m~250 μ m.
The method for making of thick resin substrate 20 for example is that glass fibre is soaked in resin liquid, makes glass fibre and mixed with resin form central core 201, and forms first, second resin bed 203,205 of tool one thickness in central core 201 outsides.And the glass fiber resin layer of central core 201, with first, second resin bed 203,205 included resin materials for example be fluoram resin (Ammonium Bifluoride, ABF), bimaleimide resin (Bismaleimide, BT), the glass fabricbase have epoxy resin (FR4, FR5), Polyimide resin (polyimide, PI), liquid crystal polymer resin (LCP) or epoxy resin (Epoxy) etc.But the present invention also seldom limits this.
Then, form through hole (through hole) and groove (trench) at thick resin substrate 20 places shown in Fig. 2 A, wherein, through hole runs through substrate 20, and groove then is formed at the upper surface 21a and the lower surface 21b place of substrate 20.
Then be to form through hole 22 earlier to run through substrate 20 in this embodiment, shown in Fig. 2 B; Remove glass fibre and the resin swarf that is produced when forming through hole 22 afterwards.Form a plurality of groove 23a~23d and 25a~25c respectively in first resin bed 203 and second resin bed, 205 places again, shown in Fig. 2 C; Afterwards and the resin swarf that is produced when remove forming groove 23a~23d, 25a~25c.Make through hole 22 again and may make to bore and dig through the swarf (glass fibre and resin) that hole 22 produces and fall to groove 23a~23d, 25a~25c as making earlier groove 23a~23d, 25a~25c, and influence subsequent technique and product is electrical.Yet, the order of formation through hole 22 and groove 23a~23d, 25a~25c when the present invention is not specially limited actual fabrication.
In this embodiment, can utilize machine drilling (mechanical drill) mode or laser drill (laser drill) mode, form the through hole 22 shown in Fig. 2 B to punch substrate 20.If select the laser drill mode, the long wavelength laser that then can select to have higher-energy for example uses carbon dioxide laser (CO to form through hole 22 at substrate 20 places 2Laser).In addition, can preferably select for use and have a more low-energy short wavelength laser and cut out groove 23a~23d, 25a~25c shown in Fig. 2 C at first resin bed 203 and second resin bed, 205 places as ultraviolet laser or excimer laser (UV or Excimer Laser).The embodiment of the invention selects for use laser drill and cutting mode to form through hole 22 and groove 23a~23d, 25a~25c, do not need to use traditional gold-tinted technology, and be to use the laser of tool high-accuracy position system to process, therefore not only technology has the step of autoregistration (self-aligned), and the product of making also has self aligned advantage.
Then, shown in Fig. 2 D, substrate 20 is once electroplated (one-plating step), for example substrate 20 is soaked and place an electroplating bath, make all full electric conducting materials 26 of plating simultaneously of through hole 22 and groove 23a~23d, 25a~25c.Electric conducting material 26 for example is a metallic copper.Being different from tradition must use electroless plating (electroless deposition) mode to form end copper earlier for filling out plating hole/groove, re-using the metallide mode continues this space plating full, employed once plating of the embodiment of the invention can be plated through hole 22 and groove 23a~23d, 25a~25c full apace simultaneously, not only step simply also can shorten the overall flow time (quicker cycle time), and manufacturing cost is reduced.
Afterwards, shown in Fig. 2 E, remove the unnecessary electric conducting material 26 of upper surface 21a and lower surface 21b place of substrate 20, electric conducting material 26 surfaces that make plating fill in through hole 22 and groove 23a~23d, 25a~25c flush with the upper surface 21a and the lower surface 21b of substrate 20.In this embodiment, can utilize etching (etching) mode or mechanical lapping (mechanical grinding) mode to make surperficial thinning, to remove unnecessary electric conducting material 26 on the substrate 20.Also but Applied Electrochemistry attenuate (electrolytic thinning), micro-etching (flash etching) or ablated surface (surface ablation)/plasma cleaning alternate manners such as (plasma cleaning) reaches and removes the unnecessary electric conducting material and the purpose of planarization.The present invention also seldom limits this.
Then, form one first solder layer 206 and one second solder layer 207 respectively, and first solder layer 206, second solder layer 207 expose the part surface of the electric conducting material 26 at through hole 22 and groove place respectively at the upper surface 21a and the lower surface 21b of substrate 20.Shown in 2F figure, after forming, first solder layer 206 exposes the part surface of the electric conducting material 26 that is filled in groove 23b place; After forming, second solder layer 207 exposes the part surface of the electric conducting material 26 that is filled in groove 25a~25c place.Wherein, the thickness of first solder layer 206 and second solder layer 207 for example is respectively about 10 μ m~20 μ m.
In this embodiment; after forming first solder layer 206, second solder layer 207; the part surface that electric conducting material 26 at through hole 22 and groove 23b, 25a~25c place is exposed carries out a surface treatment; for example carry out an electroless plated metal technology (Bus-less metal finish); correspondingly to form metal level 208a~208c or coat of metal; shown in Fig. 2 G, to finish the making of embedded line substrate.Metal level 208a~the 208c or the material of coat of metal for example are to use the lead-free solder more harmless to environment.Wherein, lead-free solder comprises metal coating and organic coating.Metal coating is for example changed nickel gold (Electroless Nickel/Immersion Gold, ENIG), immersion silver (Immersion Silver, ImAg), immersion tin (Immersion Tin, ImSn) or selectivity zinc-plated (Selective Tin-Plating) etc.; Organic coating (coat of metal) for example the Organic Solderability protective agent (Organic Solderability Preservative, OSP).But the present invention need decide on the practical application situation when selecting finish materials not as limit
Manufacture method as the disclosed embedded line substrate of the above-mentioned embodiment of the invention, (first resin bed 203 and second resin bed 205) directly defines groove and forms through hole on the resin of thick resin substrate 20, and the line pattern of substrate (electric conducting material 26 shown in Fig. 2 E), as long as can reveal after removing unnecessary electric conducting material and planarisation step, and flush with resin surface fully.Therefore, compare with traditional embedded line substrate structure (as Fig. 1), the prepared substrate of the present invention does not have the line pattern of projection, but has smooth neat surface.Moreover, as described above, its total thickness of thick resin substrate that embodiment proposed is about 30 μ m~250 μ m, after a series of technology, the gross thickness of embedded line substrate is the thickness (about respectively 10 μ m~20 μ m) that thick resin substrate 20 thickness add first and second solder layer 206,207, is about 50 μ m~290 μ m.Therefore, the not only surfacing of the prepared embedded line substrate of the present invention, its integral thickness also can be reduced to below about 290 μ m, and very meeting application product day by day is tending towards compact demand.
In addition, etching in existing technology, swash and the ability of electroplating under, this embodiment more does further research for be shown in the groove size and shape that the resin bed place forms as Fig. 2 C.
Please refer to Fig. 3, it illustrates the local enlarged diagram according to the thick resin substrate of a preferred embodiment of the present invention.Wherein first resin bed 303 above central core 301 has several grooves.Indicated the three kind parameters relevant among Fig. 3, having comprised: groove wall thickness TS (trench wall thickness), groove width TW (trench width) and gash depth TD (trench depth) with groove dimensions.These three kinds of parameter values can impact for the characteristic of final products, and for example groove wall thickness TS is too thin, and cell wall has damage easily when carrying out subsequent technique; To be difficult for carrying out follow-up plated with conductive material and planarisation step if groove width is wide; And gash depth also can be subjected to the restriction of place resin layer thickness and plated with conductive material ability.
Therefore, according to one embodiment of the invention, the breadth depth ratio TW/TD of groove (aspect ratio) is about 4~1/4.Because embedded line substrate proposed by the invention can insert electric conducting material with the formation circuit in groove, so the breadth depth ratio TW/TD of groove can influence the signal integrity of circuit.And the breadth depth ratio of a plurality of grooves can be identical or different, and its exact numerical values recited is decided on application feature, and the present invention is not specially limited.For instance,, then can select lower breadth depth ratio numerical value for use, for example 1/2 or other is less than 1 numerical value if groove of the present invention will become protection frequency band circuit (guardband circuit) in application; If groove of the present invention will become conducting wire (conducting circuit) in application, then can select higher breadth depth ratio numerical value for use, for example 2 or other is greater than 1 numerical value.
Moreover in an embodiment, the wall thickness T S of each groove is about 5 μ m~15 μ m or 5 μ m~12 μ m; The width TW of each groove is about 5 μ m~15 μ m or 5 μ m~12 μ m.And for the circuit base plate (please refer to Fig. 2 F) of the about respectively 10 μ m of the thickness of selecting first and second solder layer 206,207 for use~20 μ m, gash depth TD is about 5 μ m~12 μ m.
Moreover, the wall thickness of groove and depth ratio TS/TD (aspect ratio) can influence the intensity of cell wall and then influence product yield (yield), and the stability (reliability) that also can influence product is as leakage current (leakage) or interference (cross-talking).Therefore, the wall thickness of groove and depth ratio can for example be about 4~1/4 in an embodiment.But the present invention is not specially limited this, and its exact numerical values recited is decided on application feature.For instance, if use sunken cord in the product requirement of the present invention high yield of road tool and high stability, then can select for use higher TS/TD proportionality as 2, and the wall thickness T S value of groove for example is 15 μ m; High yield of road tool and high stability if application product of the present invention does not have to sunken cord in the special requirement then can select for use the TS/TD proportionality that hangs down any as 1/2 (or more than 1/2), and the wall thickness T S value of groove can be selected 5 μ m (or more than 5 μ m).
In sum, the manufacture method of the embedded line substrate of the embodiment of the invention, on the resin of a thick resin substrate, directly define groove and form through hole, and utilize and once electroplate the plated with conductive material that forms groove and through hole simultaneously, and can form the line pattern of substrate after electric conducting material that the process removal is unnecessary and the planarisation step, and circuit flushes with resin surface.Therefore, according to the prepared embedded line substrate of the method for the embodiment of the invention, it has an even surface neatly, and integral thickness also declines to a great extent, and very meeting application product day by day is tending towards compact demand.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking accompanying Shen claims person of defining.

Claims (14)

1. the manufacture method of an embedded line substrate comprises:
One substrate is provided;
Form a through hole (through hole) and several grooves (trenches) at this substrate place, and this through hole runs through this substrate, those grooves then are formed at a upper surface and a lower surface place of this substrate; With
This substrate is once electroplated (one-plating step), make this through hole and those grooves plate a full electric conducting material simultaneously.
2. as the described manufacture method of claim l, this substrate that is wherein provided be a thick resin substrate (Thick Resin Core, TRC), its structure comprises:
One central core (central core); With
One first resin bed and one second resin bed are formed at the both sides up and down of this central core respectively.
3. manufacture method as claimed in claim 2 wherein forms this through hole earlier and runs through this substrate, forms those grooves in this first resin bed and this second resin bed place again.
4. manufacture method as claimed in claim 3 wherein utilizes a machine drilling (mechanical drill) mode or to swash boring (laser drill) mode, forms this through hole to punch this substrate.
5. manufacture method as claimed in claim 1 is wherein soaked this substrate and is placed an electroplating bath, makes this through hole and those grooves plate full this electric conducting material simultaneously.
One thick resin substrate (Thick Resin Core TRC), comprising:
One central core (central core) comprises a glass fiber resin layer, and the thickness of this glass fiber resin layer is about 10 μ m~50 μ m; With
One first resin bed and one second resin bed are formed at a upper surface and a lower surface of this central core respectively, and the thickness of this first, second resin bed is about 10 μ m~50 μ m respectively.
7. thick resin substrate as claimed in claim 6, wherein a gross thickness of this thick resin substrate is about 30 μ m~250 μ m.
8. thick resin substrate as claimed in claim 6, wherein this glass fiber resin layer and the included resin material of this first, second resin bed are fluoram resin (Ammonium Bifluoride, ABF), bimaleimide resin (Bismaleimide, BT), the glass fabricbase have epoxy resin (FR4, FR5), Polyimide resin (polyimide, PI), liquid crystal polymer resin (LCP) or epoxy resin (Epoxy).
9. thick resin substrate as claimed in claim 6, wherein this first, second resin bed more comprises several grooves (trench), and a breadth depth ratio of each groove is about 4~1/4.
10. sunken cord in the two-layer board structure on road comprises:
One central core (central core) comprises a glass fiber resin layer;
One first resin bed and one second resin bed be formed at a upper surface and a lower surface of this central core respectively, and this first, second resin bed place then have several grooves (trenches); With
One electric conducting material is filled in those grooves, and this electric conducting material that is positioned at those grooves respectively with the flush of this first, second resin bed.
11. the described board structure of claim 10, comprise that more at least one through hole runs through this first resin bed, this central core and this second resin bed, and this electric conducting material also is filled in this through hole, and this electric conducting material that is positioned at this through hole respectively with the flush of this first, second resin bed.
12. board structure as claimed in claim 10, wherein this central core (central core) comprises several layers glass fiber resin layer, the thickness of this glass fiber resin layer is about 10 μ m~50 μ m, and the thickness of this first, second resin bed is about 10 μ m~50 μ m respectively
13. board structure as claimed in claim 10, wherein a breadth depth ratio of each groove is about 4~1/4.
14. the structure of an embedded line substrate comprises:
One board structure comprises:
One central core (central core) comprises a glass fiber resin layer;
One first resin bed and one second resin bed be formed at a upper surface and a lower surface of this central core respectively, and this first, second resin bed place then have several grooves (trenches);
One first electric conducting material is filled in those grooves, and this first electric conducting material that is positioned at those grooves respectively with the flush of this first, second resin bed;
One first solder layer and one second solder layer are formed at respectively on this first, second resin bed, and this first, second solder layer has several holes respectively to expose the part surface of this first electric conducting material; With
One second electric conducting material is formed at those hole places of this first, second solder layer.
CN 200910133258 2009-04-01 2009-04-01 Structure of embedded line substrate and manufacturing method thereof Active CN101853840B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200910133258 CN101853840B (en) 2009-04-01 2009-04-01 Structure of embedded line substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200910133258 CN101853840B (en) 2009-04-01 2009-04-01 Structure of embedded line substrate and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN101853840A true CN101853840A (en) 2010-10-06
CN101853840B CN101853840B (en) 2012-10-31

Family

ID=42805217

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200910133258 Active CN101853840B (en) 2009-04-01 2009-04-01 Structure of embedded line substrate and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN101853840B (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543780A (en) * 2011-12-21 2012-07-04 深南电路有限公司 Manufacturing method of package substrate
CN103648243A (en) * 2013-12-13 2014-03-19 复旦大学 Method for preparing multilayer board in additive mode
WO2015149369A1 (en) * 2014-04-04 2015-10-08 魏晓敏 Printed circuit board
CN105210461A (en) * 2013-05-07 2015-12-30 海成帝爱斯株式会社 Method for forming substrate hole and apparatus for forming substrate hole
CN110223964A (en) * 2019-05-31 2019-09-10 王晗 A kind of heat sinking type chip fan-out structure and cooling scheme
CN110650589A (en) * 2018-06-26 2020-01-03 鹏鼎控股(深圳)股份有限公司 Manufacturing method of embedded circuit board
CN110752201A (en) * 2019-10-31 2020-02-04 京东方科技集团股份有限公司 Display back plate, preparation method thereof and display device
US10897816B2 (en) 2018-08-28 2021-01-19 Qing Ding Precision Electronics (Huaian) Co., Ltd Rigid-flex circuit board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19620095B4 (en) * 1996-05-18 2006-07-06 Tamm, Wilhelm, Dipl.-Ing. (FH) Process for the production of printed circuit boards
CN1835660A (en) * 2005-03-15 2006-09-20 杨合卿 Mfg method of precast type multi-layer circuit board

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543780B (en) * 2011-12-21 2014-10-08 深南电路有限公司 Manufacturing method of package substrate
CN102543780A (en) * 2011-12-21 2012-07-04 深南电路有限公司 Manufacturing method of package substrate
CN105210461B (en) * 2013-05-07 2018-03-30 海成帝爱斯株式会社 Substrate aperture forming method and substrate aperture forming apparatus
CN105210461A (en) * 2013-05-07 2015-12-30 海成帝爱斯株式会社 Method for forming substrate hole and apparatus for forming substrate hole
CN103648243A (en) * 2013-12-13 2014-03-19 复旦大学 Method for preparing multilayer board in additive mode
CN103648243B (en) * 2013-12-13 2016-05-25 复旦大学 A kind of multiple-plate addition preparation method
WO2015149369A1 (en) * 2014-04-04 2015-10-08 魏晓敏 Printed circuit board
CN110650589A (en) * 2018-06-26 2020-01-03 鹏鼎控股(深圳)股份有限公司 Manufacturing method of embedded circuit board
CN110650589B (en) * 2018-06-26 2020-11-03 鹏鼎控股(深圳)股份有限公司 Manufacturing method of embedded circuit board
US10897816B2 (en) 2018-08-28 2021-01-19 Qing Ding Precision Electronics (Huaian) Co., Ltd Rigid-flex circuit board
CN110223964A (en) * 2019-05-31 2019-09-10 王晗 A kind of heat sinking type chip fan-out structure and cooling scheme
CN110223964B (en) * 2019-05-31 2021-03-02 广东工业大学 Heat dissipation type chip fan-out structure and cooling scheme
CN110752201A (en) * 2019-10-31 2020-02-04 京东方科技集团股份有限公司 Display back plate, preparation method thereof and display device
CN110752201B (en) * 2019-10-31 2022-04-15 京东方科技集团股份有限公司 Display back plate, preparation method thereof and display device

Also Published As

Publication number Publication date
CN101853840B (en) 2012-10-31

Similar Documents

Publication Publication Date Title
CN101853840B (en) Structure of embedded line substrate and manufacturing method thereof
CN101887874B (en) Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
TWI658542B (en) Manufacturing method of polymer frame with rectangular cavity array
US7028400B1 (en) Integrated circuit substrate having laser-exposed terminals
TWI384925B (en) Structure of embedded-trace substrate and method of manufacturing the same
US7093356B2 (en) Method for producing wiring substrate
CN104332414A (en) Embedded chip manufacture method
JP6695066B2 (en) Polymer frame for chips such that the frame comprises at least one via in series with a capacitor
CN104269384A (en) Embedded Chip
CN102281702B (en) Substrate layout and forming method thereof
CN102867807A (en) Coreless packaging substrate and manufacturing method thereof
CN101409238A (en) Method for preparing seedless layer package substrate
US11257765B2 (en) Chip package structure including connecting posts and chip package method
CN101364586B (en) Construction for packaging substrate
US20110147058A1 (en) Electronic device and method of manufacturing electronic device
US6632734B2 (en) Parallel plane substrate
US8637972B2 (en) Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel
CN102446772B (en) Manufacture the method for semiconductor packages
CN202940226U (en) Package substrate
CN104105340A (en) Package substrate via hole structure and manufacture method
TWI652864B (en) Insert frame with polymer matrix and manufacturing method thereof
CN102931165B (en) The manufacture method of base plate for packaging
KR101034089B1 (en) core substrate and method for fabricating the same
US7611927B2 (en) Method of minimizing kerf width on a semiconductor substrate panel
CN101740403B (en) Packaging baseplate structure and manufacture method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant