CN101847095A - ASIC type IP core oriented method for realizing software programmable - Google Patents
ASIC type IP core oriented method for realizing software programmable Download PDFInfo
- Publication number
- CN101847095A CN101847095A CN200910080920A CN200910080920A CN101847095A CN 101847095 A CN101847095 A CN 101847095A CN 200910080920 A CN200910080920 A CN 200910080920A CN 200910080920 A CN200910080920 A CN 200910080920A CN 101847095 A CN101847095 A CN 101847095A
- Authority
- CN
- China
- Prior art keywords
- kernel
- core
- asic type
- software programmable
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000013461 design Methods 0.000 abstract description 13
- 238000013507 mapping Methods 0.000 abstract description 5
- 238000011161 development Methods 0.000 abstract description 3
- 230000008569 process Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 3
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The invention discloses a method for realizing software programmability facing an ASIC type IP core, which comprises the following steps: mapping an I/O port of an IP core with an address space of a main controller; and compiling HDL (high density hardware) codes for the signal waveform generator, analyzing the data attribute received by the bus interface, and generating a specific signal waveform for the IP core. By utilizing the invention, through the mapping of the CPU/MCU address space and the I/O port of the target IP core, the bus interface design of the target IP core end and the design of the signal waveform generator, the control program written by the high-level language is used for controlling the ASIC type IP core, thereby greatly facilitating the flexibility of the ASIC type IP core, simplifying the use difficulty, accelerating the development process of a user and having universal application significance.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, specifically, relate to a kind of method of examining existing software programmable towards special IC (ASIC) type intellecture property (IP).
Background technology
In the nearest more than ten years, along with the raising of ic manufacturing technology and system requirements, a focus of the software programmable of integrated circuit research becoming again.Existing extensive, ultra-large ASIC type IP kernel redesigns because of being not easy to, so it is carried out the ultimate challenge that software programmable is designed to the designer.
Characteristics such as ASIC type IP kernel has good reliability, cost is low, volume is little, low in energy consumption, but because of lacking the software programmable ability, make the method for utilizing hardware circuit that it is controlled or disposes lack dirigibility, increase user's use difficulty and construction cycle, can not satisfy fierce competitive market, especially true for ultra-large ASIC type IP kernel.Therefore, ASIC type IP kernel being carried out software programmable design, is to keep its existing performance advantage, and increases dirigibility, simplifies the practical way that the user uses complexity.
Carrying out the software programmable design at ASIC type IP kernel when, have two problems to solve: the one, how under the situation of IP kernel inside not being changed, to realize software programmable design to ASIC type IP kernel; The 2nd, how the software code instruction is changed into control signal or the configuration signal that IP kernel can be discerned, existing IP kernel inside is not changed, can remove time and cost expense that IP kernel designs, verifies from, have very strong realistic meaning and use value.
In order to overcome the above problems, the present invention proposes a kind of method that realizes software programmable towards ASIC type IP kernel.
Summary of the invention
(1) technical matters that will solve
Fundamental purpose of the present invention is to propose a kind ofly to realize the method for software programmable towards ASIC type IP kernel, with the software programmable design effort of the realization ASIC type IP kernel of simple and effective.
(2) technical scheme
For achieving the above object, the invention provides a kind of method towards ASIC type IP kernel realization software programmable, this method comprises:
Step 101: the I/O port of IP kernel and the address space of master controller are shone upon;
Step 102: write the HDL code that uses for the signal waveform maker, resolve the data attribute that bus interface receives, and produce concrete signal waveform, offer IP kernel and use.
In the such scheme, described step 101 specifically comprises: in master controller, be an amount of address space of this IP kernel distribution, and the address in this address space is corresponding one by one with the numerous control/configure/status/FPDP of this IP kernel.
In the such scheme, further comprise before the described step 101: according to the operation instructions of IP kernel, analyze the quantity of the required control signal of this IP kernel, configuration signal, data-signal, status signal, the type of selected address bus or data bus.
(3) beneficial effect
Utilize the present invention, by the mapping of CPU/MCU address space and target IP kernel I/O port, the Bus Interface Design of target IP kernel end and the design of signal waveform maker, realized controlling ASIC type IP kernel by the high level language control program, and realized designing based on the software programmable of LEON3+AHB towards ultra-large configurable dedicated data processor ASIC type IP kernel, greatly facilitate the dirigibility of ASIC type IP kernel, simplified the use difficulty, quicken user's performance history, had general significance of application.
Description of drawings
Fig. 1 is a method flow diagram of realizing software programmable towards ASIC type IP kernel provided by the invention;
Fig. 2 is an IP kernel packaging structure synoptic diagram;
Fig. 3 is the synoptic diagram based on the SoC of IP kernel;
Fig. 4 is with the process flow diagram of higher level lanquage realization to IP kernel control;
Fig. 5 is the control information synoptic diagram of the C language description in the software;
Fig. 6 is the required control word signal waveform synoptic diagram of IP kernel.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the method flow diagram towards ASIC type IP kernel realization software programmable provided by the invention, and this method comprises:
Step 101: the I/O port of IP kernel and the address space of master controller are shone upon;
Step 102: write the HDL code that uses for the signal waveform maker, resolve the data attribute that bus interface receives, and produce concrete signal waveform, offer IP kernel and use.
The present invention has adopted IP kernel packing (Wrapper) method or SoC (System-on-Chip) development approach shown in Figure 3 as shown in Figure 2.At first according to the operation instructions of IP kernel, analyze the quantity of its required control signal or configuration signal, data-signal, status signal, selected suitable bus standard (for example AMBA bus, spi bus etc.) is to satisfy IP kernel and the required bandwidth requirement of outer communication.For the ease of saying something herein, and use in the reality, suggestion is also selected master cpu (or MCU) type (as ARM or SPARC etc.) in selected bus type, and is especially true for the SoC implementation.Next, in CPU, be an amount of address space of target IP kernel distribution, and the numerous control/configure/status/FPDP of address in this space, address and IP kernel is mapped one by one, like this at CPU, the ASIC IP kernel is convenient to carry out the software code exploitation as Memory or I/O.At last, carry out actual hardware circuit exploitation, i.e. bus interface (Bus Interface) among Fig. 2 (or Fig. 3) and signal waveform maker (Signal Wave Generator) two modules.Bus Interface module realizes the correct communication with CPU, and Signal Wave Generator module is finished the translation between CPU software semanteme and the ASIC IP kernel hardware signal, for example the control word information that the software code among Fig. 5 is represented changes into the required hardware signal waveform of IP kernel shown in Figure 6.
Because of the sequential chart difference of the different PORT COM of IP kernel is bigger, so design Signal Wave Generator module becomes the emphasis and the difficult point of this method.More than work all finish after, the user just can utilize senior language such as C/C++ (needing the compiler Compiler of CPU/MCU to match) the ASIC IP kernel to be controlled or operation such as configuration easily, even can also further realize the control of DMA (direct memory access (DMA) data) and operating system to IP kernel, improved the development efficiency in the IP kernel use greatly, this is difficult to accomplish in original hardware controls mode.
Being CPU/MCU with the LEON3 processor below, is Bus with the AHB agreement in the AMBA bus, is IP kernel with ultra-large configurable dedicated data processor kernel, describes the implementation method of this software programmable in detail.In order to make this IP kernel receive control word or pending data that LEON3 sends smoothly, need add AHB Slaver interface (BusInterface) at original IP module top layer and receive the data message that transmits through AHB from LEON3, and carry out address space mapping according to the required I/O port of IP kernel, as shown in table 1, table 1 is the address mapping relation between LEON3 and the IP kernel.
Table 1
Write HDL code (Signal Wave Generator) with Verilog then, the address information according to Bus Interface receives parses data attribute, produces the corresponding signal waveform and enters IP kernel.In addition, for the expedited data processing speed, dma controller can also be set herein realize the DMA transmission mode.
Utilize the C code according to the required Starting mode of IP kernel, control word, input filter factor, input raw data (or starting dma controller) are set earlier, start IP kernel then and carry out data processing, data processing back is well carried out data output by the interrupt operation of the state change triggering LEON3 of status register.During specific design,, need between the different instruction of C code, insert necessary delay instruction because of the software and hardware Cycle data difference of different operating, synchronous to guarantee software and hardware.
The software program that writes, the LEON3 C code encoder (sparc-elf-gcc) that provides through Gaisler Research company compiles, and generates binary code, can carry out software and hardware combined debugging and application.
So far, the software programmable design of carrying out towards ASIC type IP kernel is all finished.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. realize the method for software programmable it is characterized in that this method comprises towards ASIC type IP kernel for one kind:
Step 101: the I/O port of IP kernel and the address space of master controller are shone upon;
Step 102: write the HDL code that uses for the signal waveform maker, resolve the data attribute that bus interface receives, and produce concrete signal waveform, offer IP kernel and use.
2. the method towards ASIC type IP kernel realization software programmable according to claim 1 is characterized in that described step 101 specifically comprises:
In master controller, be an amount of address space of this IP kernel distribution, and the address in this address space is corresponding one by one with the numerous control/configure/status/FPDP of this IP kernel.
3. the method towards ASIC type IP kernel realization software programmable according to claim 1 is characterized in that, further comprises before the described step 101:
According to the operation instructions of IP kernel, analyze the quantity of the required control signal of this IP kernel, configuration signal, data-signal, status signal, the type of selected address bus or data bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910080920A CN101847095A (en) | 2009-03-25 | 2009-03-25 | ASIC type IP core oriented method for realizing software programmable |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910080920A CN101847095A (en) | 2009-03-25 | 2009-03-25 | ASIC type IP core oriented method for realizing software programmable |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101847095A true CN101847095A (en) | 2010-09-29 |
Family
ID=42771721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910080920A Pending CN101847095A (en) | 2009-03-25 | 2009-03-25 | ASIC type IP core oriented method for realizing software programmable |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101847095A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106528927A (en) * | 2016-09-29 | 2017-03-22 | 北京深维科技有限公司 | Input output I/O process mapping method and device |
| CN110456708A (en) * | 2019-08-20 | 2019-11-15 | 北京精密机电控制设备研究所 | A kind of electromechanical servo control platform based on SOPC technology |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1763734A (en) * | 2005-11-10 | 2006-04-26 | 苏州国芯科技有限公司 | 8051 series microprocessor application system based on AMBA bus |
| CN101150393A (en) * | 2006-09-21 | 2008-03-26 | 北京中电华大电子设计有限责任公司 | A RSA coprocessor design method applicable SOC chip |
-
2009
- 2009-03-25 CN CN200910080920A patent/CN101847095A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1763734A (en) * | 2005-11-10 | 2006-04-26 | 苏州国芯科技有限公司 | 8051 series microprocessor application system based on AMBA bus |
| CN101150393A (en) * | 2006-09-21 | 2008-03-26 | 北京中电华大电子设计有限责任公司 | A RSA coprocessor design method applicable SOC chip |
Non-Patent Citations (1)
| Title |
|---|
| ZHI GUO ET AL.: "《Field Programmable Logic and Applications, 2006. FPL "06. International Conference on》", 30 August 2006 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106528927A (en) * | 2016-09-29 | 2017-03-22 | 北京深维科技有限公司 | Input output I/O process mapping method and device |
| CN106528927B (en) * | 2016-09-29 | 2019-07-30 | 京微齐力(北京)科技有限公司 | Input and output I/O process mapping method and device |
| CN110456708A (en) * | 2019-08-20 | 2019-11-15 | 北京精密机电控制设备研究所 | A kind of electromechanical servo control platform based on SOPC technology |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104866452B (en) | Multi-serial extension method based on FPGA and TL16C554A | |
| CN101344870B (en) | FIFO control module with strong reusability and method for managing internal memory | |
| CN101859289B (en) | Method for accessing external memory using off-chip memory access controller | |
| CN104809094A (en) | SPI (Serial Peripheral Interface) controller and communication method for SPI controller | |
| CN104050067A (en) | Method and device for operation of FPGA (Field Programmable Gate Array) in MCU (Microprogrammed Control Unit) chip | |
| Ma et al. | Design and implementation of APB bridge based on AMBA 4.0 | |
| CN101847095A (en) | ASIC type IP core oriented method for realizing software programmable | |
| CN100343778C (en) | Transferring data between differently clocked busses | |
| CN101131715A (en) | Micro-processor IP nuclear design method for navigation system | |
| CN106709116B (en) | Method and device for generating RTL (real time language) level IP (Internet protocol) core | |
| US8659318B1 (en) | Systems and methods for implementing tristate signaling by using encapsulated unidirectional signals | |
| CN105512072A (en) | Conversion device based on APB (advanced peripheral bus) and OPB (on-chip peripheral bus) | |
| US20220147097A1 (en) | Synchronization signal generating circuit, chip and synchronization method and device, based on multi-core architecture | |
| CN106445879B (en) | A kind of SoC devices | |
| Edwards | SHIM: A language for hardware/software integration | |
| CN111710357B (en) | MTP unit read-write control circuit of MCU | |
| US20170212861A1 (en) | Clock tree implementation method, system-on-chip and computer storage medium | |
| Jolfaei et al. | High speed usb 2.0 interface for fpga based embedded systems | |
| CN103984263B (en) | A kind of compatible ISA, the general dsp module of pci bus interface and collocation method | |
| CN105676995A (en) | Method for achieving low power consumption of three-dimensional measurement chip | |
| Jianping et al. | High-speed FPGA-based SOPC application for currency sorting system | |
| Sarekokku et al. | Design and Implementation of APB Bridge based on AMBA AXI 4.0 | |
| CN105740179A (en) | Parallel data acquisition system | |
| CN110110362B (en) | Method for designing chip by using embedded command | |
| US7809861B1 (en) | System memory map decoder logic |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20100929 |