CN101826470B - 一种倒装焊高散热球型阵列封装方法 - Google Patents
一种倒装焊高散热球型阵列封装方法 Download PDFInfo
- Publication number
- CN101826470B CN101826470B CN2010101634006A CN201010163400A CN101826470B CN 101826470 B CN101826470 B CN 101826470B CN 2010101634006 A CN2010101634006 A CN 2010101634006A CN 201010163400 A CN201010163400 A CN 201010163400A CN 101826470 B CN101826470 B CN 101826470B
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- China
- Prior art keywords
- chip
- packaging
- radiation
- substrate
- chip bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010101634006A CN101826470B (zh) | 2010-04-29 | 2010-04-29 | 一种倒装焊高散热球型阵列封装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010101634006A CN101826470B (zh) | 2010-04-29 | 2010-04-29 | 一种倒装焊高散热球型阵列封装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101826470A CN101826470A (zh) | 2010-09-08 |
CN101826470B true CN101826470B (zh) | 2011-08-10 |
Family
ID=42690307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN2010101634006A Active CN101826470B (zh) | 2010-04-29 | 2010-04-29 | 一种倒装焊高散热球型阵列封装方法 |
Country Status (1)
Country | Link |
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CN (1) | CN101826470B (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110911365A (zh) * | 2019-10-28 | 2020-03-24 | 北京时代民芯科技有限公司 | 一种倒装焊封装散热结构及制造方法 |
CN111574967A (zh) * | 2020-05-06 | 2020-08-25 | 苏州通富超威半导体有限公司 | 散热材料、应用该散热材料的芯片封装组件及制备方法 |
FR3127629A1 (fr) * | 2021-09-24 | 2023-03-31 | Stmicroelectronics (Grenoble 2) Sas | Elément dissipateur de chaleur |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4959900A (en) * | 1988-07-20 | 1990-10-02 | Matra | Mounting of electronic microcomponents on a support |
US5280409A (en) * | 1992-10-09 | 1994-01-18 | Sun Microsystems, Inc. | Heat sink and cover for tab integrated circuits |
US5990552A (en) * | 1997-02-07 | 1999-11-23 | Intel Corporation | Apparatus for attaching a heat sink to the back side of a flip chip package |
-
2010
- 2010-04-29 CN CN2010101634006A patent/CN101826470B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4959900A (en) * | 1988-07-20 | 1990-10-02 | Matra | Mounting of electronic microcomponents on a support |
US5280409A (en) * | 1992-10-09 | 1994-01-18 | Sun Microsystems, Inc. | Heat sink and cover for tab integrated circuits |
US5990552A (en) * | 1997-02-07 | 1999-11-23 | Intel Corporation | Apparatus for attaching a heat sink to the back side of a flip chip package |
Also Published As
Publication number | Publication date |
---|---|
CN101826470A (zh) | 2010-09-08 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C53 | Correction of patent for invention or patent application | ||
CB03 | Change of inventor or designer information |
Inventor after: Wu Xiaochun Inventor before: Wu Xiaochun Inventor before: Tao Yujuan |
|
COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: WU XIAOCHUN TAO YUJUAN TO: WU XIAOCHUN |
|
C56 | Change in the name or address of the patentee | ||
CP03 | Change of name, title or address |
Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 30 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |