CN101819250B - System for boundary scan experiment - Google Patents
System for boundary scan experiment Download PDFInfo
- Publication number
- CN101819250B CN101819250B CN 201010131889 CN201010131889A CN101819250B CN 101819250 B CN101819250 B CN 101819250B CN 201010131889 CN201010131889 CN 201010131889 CN 201010131889 A CN201010131889 A CN 201010131889A CN 101819250 B CN101819250 B CN 101819250B
- Authority
- CN
- China
- Prior art keywords
- test
- boundary scan
- chip
- function
- link
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a method, a system and a target device for boundary scan experiment. The test target device comprises a TAP input end, a BS chip slot, a slot for a chip to be tested an a TAP output end, wherein the TAP input end is used for receiving externally input TAP test bus signals; the BS chip slot is connected with the TAP input end and is used for bearing a BS chip; the slot for the chip to be tested is connected with the BS chip slot through a jumper switch and is used for bearing the chip to be tested; and the TAP output end is connected with the BS chip slot and is used for feeding back test signals to an external TAP. The invention provides an experiment platform for learning and practicing to learners of the boundary scan technique, and can provide experiment of multiple test patterns based on all the boundary scan test standards.
Description
Technical field
The present invention especially for the boundary scan testing experimental technique of teaching with real standard, is a kind of boundary scan experimental technique, system and destination apparatus about the Boundary-scan test technology field concretely.
Background technology
Boundary scan technique is a kind of testability designing technique, and its basic thought is on pin of chip, to increase register cell connected in series, realizes can control and controllability signal.Boundary scan testing is one of the most effective means of testing in the present electronic circuit test, obtains more and more widely attention and application, becomes the content that many Test Engineers and relevant learner must learn and grasp.
But because the test structure relative complex of boundary scan technique, the generation of test vector and the analysis of test response are grasped more complicated, in practical application, require the tester to have suitable hardware and software basis; On the other hand, except the relevant technical standard of boundary scan, also do not have to be directed against specially the study and the experimental provision of boundary scan technique on the market, bring inconvenience to the beginner.
Summary of the invention
The embodiment of the invention provides a kind of boundary scan experimental technique, system and destination apparatus, uses so that the learner can grasp the basic hardware structure of boundary scan testing, the production method of test vector and the analytical approach of test response etc. faster.
One of the object of the invention is, a kind of boundary scan experimental technique is provided, and this method comprises: obtain the boundary scan testing program; Function and sequential according to the boundary scan testing program generate the test bus signal; Be input to the test bus signal in the boundary scan testing link that is connected with gating switch, boundary scan BS chip and chip under test through test access port TAP; According to the open/close state of the corresponding gating switch of the function strobe of boundary scan testing program, so that the boundary scan link of test bus signal through correspondence turns back to TAP; The test bus signal that TAP is returned is analyzed and is diagnosed, and outputs test result.
One of the object of the invention is, a kind of boundary scan experimental system is provided, and this system comprises: boundary scan master control set and boundary scan object of experiment device; The boundary scan master control set comprises: the test procedure acquiring unit is used to obtain the boundary scan testing program; The test signal generation unit is used for generating the test bus signal according to the function and the sequential of boundary scan testing program; Tap cell is used for the test bus signal is inputed to boundary scan object of experiment device; Test result output unit, the test bus signal that is used for that tap cell is returned is analyzed and is diagnosed, and outputs test result; Boundary scan object of experiment device comprises: the boundary scan testing link that is connected with gating switch, boundary scan BS chip and chip under test; Be used to receive the test bus signal of tap cell input; And according to the open/close state of the corresponding gating switch of the function strobe of boundary scan testing program, so that the boundary scan link of test bus signal through correspondence turns back to tap cell.The function of boundary scan testing program comprises: bunch test function, interconnecting test function, self-test function or analog circuit test function; Wherein, Boundary scan object of experiment device comprises: bunch test function module; Be used for open/close state according to the corresponding gating switch of bunch test function gating of boundary scan testing program; So that the BS chip is surrounded on around the chip under test of non-boundary Scan Architecture, the test bus signal turns back to described tap cell through four BS chips; The interconnecting test functional module is used for the open/close state according to the corresponding gating switch of interconnecting test function strobe of said boundary scan testing program, so that the test bus signal turns back to tap cell through two BS chips; The self-test function module is used for the open/close state according to the corresponding gating switch of self-test function gating of boundary scan testing program, so that the test bus signal turns back to tap cell through a slice BS chip; The device that comprises in the test link of bunch test function has: as 4 SN74BCT8373 of BS chip (102a, 102b, 102c, 102d), and being set to of gating switch: jumper switch JP1, JP3, JP4 and JP5 are closed, and JP2 breaks off; The path of test link is: the TDO4 port of the TDI port of AVR single-chip microcomputer → SN74BCT8373 chip 102a → SN74BCT8373 chip 102b → SN74BCT8373 chip 102c → SN74BCT8373 chip 102d → AVR single-chip microcomputer; The test link of described interconnecting test function comprises: as the SN74BCT8373 chip 102a and the SN74BCT8373 chip 102b of BS chip; And being set to of gating switch: jumper switch JP1, JP3, JP4 and JP5 break off, and JP2 is closed; The path of test link is: the TDO4 port of the TDI port of AVR single-chip microcomputer → SN74BCT8373 chip 102a → SN74BCT8373 chip 102b → AVR single-chip microcomputer; The device that comprises in the test link of described self-test function has: as the SN74BCT8373 chip 102a of BS chip; And being set to of gating switch: jumper switch JP1, JP3, JP4 and JP2 break off, and the path of test link is: the TDO4 port of the TDI port of AVR single-chip microcomputer → SN74BCT8373 chip 102a → AVR single-chip microcomputer; The device that comprises in the test link of described analog circuit test function has: STA400, and the path of test link is: the TDO0 port of the TDI port → STA400 of AVR single-chip microcomputer → simulating signal sample circuit → STA400 → AVR single-chip microcomputer.
One of the object of the invention is, a kind of boundary scan object of experiment device is provided, and this object of experiment device comprises: the input end among the TAP is used to receive the TAP test bus signal of outside input; The BS chip pocket is used to carry the BS chip; The chip under test slot is used to carry chip under test; Output terminal among the TAP is used to export test response signal; Gating switch according to the open/close state of the corresponding gating switch of the function strobe of boundary scan testing program, makes BS chip and/or chip under test form the boundary scan testing link.
The present invention has been for the learner of boundary scan technique provides the experiment porch of study and real standard, can provide based on all boundary scan testing standards, the experiment of many test patterns.The method that the present invention adopts multilink to select has realized in a cover goal systems, can carrying out multiple boundary scan testing pattern experiment, comprising: the interconnecting test of digital circuit, bunch test, functional test, build-in test, signal sampling etc.; The discrete component parameter testing of mimic channel, interconnecting test etc.Greatly saved the hardware spending of object of experiment system, and simple in structure being easy to realized.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the process flow diagram of embodiment of the invention boundary scan experimental technique;
Fig. 2 is the structured flowchart of embodiment of the invention boundary scan experimental system;
Fig. 3 is the structured flowchart of embodiment of the invention boundary scan master control set;
Fig. 4 is the structured flowchart of embodiment of the invention boundary scan object of experiment device;
Fig. 5 is bunch test synoptic diagram of embodiment of the invention boundary scan object of experiment device;
Fig. 6 is the interconnecting test synoptic diagram of embodiment of the invention boundary scan object of experiment device;
Fig. 7 is the self-test synoptic diagram of embodiment of the invention boundary scan object of experiment device;
Fig. 8 is the analog circuit test synoptic diagram of embodiment of the invention boundary scan object of experiment device.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
As shown in Figure 1, the boundary scan experimental technique of the specific embodiment of the invention comprises: obtain boundary scan testing program (step S101); Function and sequential according to the boundary scan testing program generate test bus signal (step S102); Be input to the test bus signal in the boundary scan testing link that is connected with gating switch, boundary scan BS chip and chip under test (step S103) through test access port TAP; According to the open/close state of the corresponding gating switch of the function strobe of boundary scan testing program, so that the boundary scan link of test bus signal through correspondence turns back to TAP (step S104); The test bus signal that TAP is returned is analyzed and is diagnosed, and (step S105) outputs test result.
As shown in Figure 2, boundary scan experimental system of the present invention comprises: boundary scan master control set and boundary scan object of experiment device.
As shown in Figure 3, the boundary scan master control set mainly comprises: CPU 201 (AVR single chip computer AT mega128), boundary scan testing bus master controller 202 (SN74ACT8990); Power supply 205 (from stabilized voltage supply, getting 5v and 3.3v) is respectively the AVR single-chip microcomputer and SN74ACT8990 provides power supply; Reset circuit 209 carries out reset operation to AVR single-chip microcomputer and SN74ACT8990; Clock 210 comprises: 12,000,000 and 6,000,000 two external clocks are respectively the AVR single-chip microcomputer and SN74ACT8990 provides clock signal; Storer 211 carries out accessing operation through the AVR single-chip microcomputer to storer 211; Serial ports 206 (RS232 serial communication circuit) comprising: two serial ports paths are used for carrying out communication with host computer and other peripherals; LCD display 207 is as the interface of man-machine interaction in the test process; ISP program download circuit 208 downloads to test procedure and code in the AVR single-chip microcomputer, the control whole test system; Jtag interface 203 comprises TDI, TDO, TCK and tms signal, the interface of test bus; Analog measurement interface 204 (STA400 circuit) provides the test interface when analog part tested.
The test subscriber downloads to test procedure and test code in the AVR single-chip microcomputer in the boundary scan governor circuit through the ISP port.The AVR single-chip microcomputer is according to the function and the sequential requirement of program, and control SN74ACT8990 produces test bus signal (TDI, TDO, TMS and tck signal).The test bus signal that is produced is used to realize the interconnecting test, bunch test, build-in test of digital circuit part etc.
As shown in Figure 4, the boundary scan object of experiment device of present embodiment comprises: the input end of TAP interface 104 is used to receive the outside TAP test bus signal of importing; The BS chip (102a, 102b, 102c and 102d) that BS chip pocket and slot carry is connected with the input end of TAP interface 104, is used to carry the BS chip; The chip under test slot, (103a, 103b, 103c, 103d and 103e) is connected with the BS chip pocket through jumper switch, is used to carry chip under test 101; The output terminal of TAP interface 104 is connected with the BS chip pocket, is used for to the TAP of outside feedback test signal.Simulating signal sample circuit 105; Be used for receiving the test bus signal of input end input of Simulation with I/O interface 106 of TAP; And according to the analog signal sampling of test bus signal to border scan test destination apparatus; With the analog signal conversion of gathering is test response signal, turns back to the output terminal in Simulation with I/O interface 106 of TAP.
The boundary scan object of experiment device of present embodiment can mainly be made up of 51 SCM systems, 74BCT8373 group and simulation circuit-under-test.51 SCM systems and typical digital circuit of the common formation of 74BCT8373 group.Method through multiloop is selected in this typical circuit, can constitute interconnecting test, bunch test, build-in test and analog circuit test scan chain circuit, experimentizes respectively.
The fundamental of boundary scan technique is exactly on the pin border with the boundary scan link encirclement circuit-under-test of a serial and element, to realize observation and the control to circuit-under-test and element signal.Therefore, different link selection will cause the difference of measurand difference and test pattern.For these reasons, the way that in the object of experiment system, adopts multiloop boundary scan link to select has realized in same system, carries out multiple test experiments model selection.
Like Fig. 2 and shown in Figure 5, JP is the wire jumper interface, selects the path of data stream through wire jumper; Thumb-acting switch is used as to SN74BCT8373 (1) and SN74BCT8373 (3) sets fixing 0/1 input; Dotted portion is boundary scan link (test bus signal TCK, tms signal are received respectively on the TCK and TMS pin of each SN74BCT8373, figure part omitted), and this link comprises a TDO end and five TDI ports, respectively correspondence five kinds of links; The LED light group is used to show the output high-low level situation of P0 and P2 port.The hardware of various test links is formed and test function is gone into down:
1) bunch test function
The device that comprises in the test link: as SN74BCT8373 (1), SN74BCT8373 (2), SN74BCT8373 (3) and the SN74BCT8373 (4) of BS chip.
The setting of gating switch: jumper switch JP1, JP3, JP4 and JP5 are closed; JP2 breaks off.
The path of test link: TDI → SN74BCT8373 (1) → SN74BCT8373 (2) → SN74BCT8373 (3) → SN74BCT8373 (4) → TDO4.
Test function: the boundary-scan architecture of four SN74BCT8373 has been realized the covering of 51 single-chip microcomputer input and output pins is used for the checking of bunch test.
2) interconnecting test function
Test link comprises: as the SN74BCT8373 (1) and the SN74BCT8373 (2) of BS chip.
The setting of gating switch: jumper switch JP1, JP3, JP4 and JP5 break off; JP2 is closed.
The path of test link: TDI → SN74BCT8373 (1) → SN74BCT8373 (2) → TDO4.
Test function: the interconnecting test between the boundary-scan architecture chip of two SN74BCT8373.
3) self-test or build-in test function
The device that comprises in the test link: as the SN74BCT8373 (1) of BS chip.
The setting of gating switch: jumper switch JP1, JP3, JP4 and JP2 break off.
The path of test link: TDI → SN74BCT8373 (1) TDO4.
Test function: the chip that monolithic → SN74BCT8373 (1) is had boundary-scan architecture carries out self-test (RUNTEST) or build-in test (INTEST).
4) simulating signal sample circuit test function
The device that comprises in the test link: STA400.
The path of test link: TDI → STA400 → simulating signal sample circuit → STA400 → TDO0.
Test function: typical mimic channel in the destination apparatus is carried out the test based on boundary scan.
As shown in Figure 5; In above-mentioned interconnecting test and build-in test; Can utilize thumb-acting switch the pumping signal input to be set to tested BS chip; Tested BS chip responds the pumping signal of input, the output test response signal, and show the test response result or test response signal is turned back to MCU through TAP through led array and analyze and diagnose.
Bunch test is the functional test of non-boundary scanning device, is an important test function of present stage boundary scan testing.Bunch general adopt " the virtual data channel method " of test, basic test thought is: the boundary scanning device through around the non-boundary scanning device to be measured provides TCH test channel, realizes that test vector loads and test response reads and Treatment Analysis.
The functional structure chart of bunch test experiments module is as shown in Figure 2.Four groups of universal input and output port of AT89S51 all link to each other with the SN74BCT8373 that a slice has a boundary-scan architecture, therefore can on the I/O of single-chip microcomputer port, apply excitation or catch response through boundary-scan architecture, are used for bunch test to AT89S51.Bunch test experiments module concerns all kinds of faults is set through regulating wire jumper between four SN74BCT8373 chips and 51 single-chip microcomputers.
As shown in Figure 6, interconnecting test is used to detect line and plate level interconnect fault between each integrated circuit, comprises short circuit (bridging fault), open circuit and fixed logic fault.The output Q [0..7] of SN74BCT8373 in the interconnecting test experiment module (1) and the input D [0..7] of SN74BCT8373 (2) interconnection, as shown in Figure 2.Through the wire jumper relation between SN74BCT8373 (1) and the SN74BCT8373 (2) is set, the fixed logic fault can be set, open fault and short trouble.
As shown in Figure 7; The basic skills of the build-in test in boundary scanning device and the electronic system is: with the boundary scan cell of test vector serial-shift to device or circuit board data input pin; Test master sends " close beta instruction " to circuit and (INTEST) orders; The test response of series read-out data output end then, it is compared with correct response can obtain test result.
Employing is verified this test function to the mode that monolithic SN74BCT8373 carries out close beta.In Board Under Test, select No. 3 links, only have SN74BCT8373 (1) to be in the boundary scan link of whole Board Under Test and, level signal on its input port is set as input stimulus through thumb-acting switch with its gating.
As shown in Figure 8, select No. 0 link will realize boundary scan testing experiment to mimic channel.STA400 can select 1 or one 4 to select 1 multiplexer as two 2 through configuration under normal duty.Under test pattern, this device can provide 9 pins that meet the IEEE1149.4 standard to be used for mixed signal test, can accomplish simulation and the interconnecting test of mixed signal circuit, the parameter testing and the functional test of discrete component.
The embodiment of the invention is that the learner of boundary scan technique provides the experiment porch of a study with real standard, can provide based on all boundary scan testing standards, the experiment of many test patterns.The method that the present invention adopts multilink to select has realized in a cover goal systems, can carrying out multiple boundary scan testing pattern experiment, comprising: the interconnecting test of digital circuit, bunch test, functional test, build-in test, signal sampling etc.; The discrete component parameter testing of mimic channel, interconnecting test etc.Greatly saved the hardware spending of object of experiment system, and simple in structure being easy to realized.
Used specific embodiment among the present invention principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as limitation of the present invention.
Claims (2)
1. a boundary scan experimental system is characterized in that, described system comprises: boundary scan master control set and boundary scan object of experiment device;
Described boundary scan master control set comprises:
The test procedure acquiring unit is used to obtain the boundary scan testing program;
The test signal generation unit is used for generating the test bus signal according to the function and the sequential of said boundary scan testing program;
Tap cell is used for described test bus signal is inputed to described boundary scan object of experiment device;
Test result output unit, the test bus signal that is used for that said tap cell is returned is analyzed and is diagnosed, and outputs test result;
Described boundary scan object of experiment device comprises:
Be connected with the boundary scan testing link of gating switch, boundary scan BS chip and chip under test; Be used to receive the test bus signal of said tap cell input; And according to the open/close state of the corresponding gating switch of the function strobe of said boundary scan testing program, so that the boundary scan testing link of described test bus signal through correspondence turns back to described tap cell;
The function of said boundary scan testing program comprises: bunch test function, interconnecting test function, self-test function or analog circuit test function;
Wherein, described boundary scan object of experiment device comprises:
Bunch test function module; Be used for open/close state according to the corresponding gating switch of bunch test function gating of said boundary scan testing program; So that described BS chip is surrounded on around the chip under test of non-boundary Scan Architecture, the test bus signal turns back to described tap cell through four BS chips;
The interconnecting test functional module is used for the open/close state according to the corresponding gating switch of interconnecting test function strobe of said boundary scan testing program, so that described test bus signal turns back to described tap cell through two BS chips;
The self-test function module is used for the open/close state according to the corresponding gating switch of self-test function gating of said boundary scan testing program, so that described test bus signal turns back to described tap cell through a slice BS chip;
The device that comprises in the test link of described bunch of test function has: as SN74BCT8373 (102a), SN74BCT8373 (102b), SN74BCT8373 (102c) and the SN74BCT8373 (102d) of BS chip; And being set to of gating switch: jumper switch JP1, JP3, JP4 and JP5 are closed, and JP2 breaks off; The path of test link is: the TDO4 port of the TDI port → SN74BCT8373 (102a) of AVR single-chip microcomputer → SN74BCT8373 (102b) → SN74BCT8373 (102c) → SN74BCT8373 (102d) → AVR single-chip microcomputer;
The test link of described interconnecting test function comprises: as the SN74BCT8373 (102a) and the SN74BCT8373 (102b) of BS chip; And being set to of gating switch: jumper switch JP1, JP3, JP4 and JP5 break off, and JP2 is closed; The path of test link is: the TDO4 port of the TDI port → SN74BCT8373 (102a) of AVR single-chip microcomputer → SN74BCT8373 (102b) → AVR single-chip microcomputer;
The device that comprises in the test link of described self-test function has: as the SN74BCT8373 (102a) of BS chip; And being set to of gating switch: jumper switch JP1, JP3, JP4 and JP2 break off, and the path of test link is: the TDO4 port of TDI port → SN74BCT8373 (the 102a) → AVR single-chip microcomputer of AVR single-chip microcomputer;
The device that comprises in the test link of described analog circuit test function has: STA400, and the path of test link is: the TDO0 port of the TDI port → STA400 of AVR single-chip microcomputer → simulating signal sample circuit → STA400 → AVR single-chip microcomputer.
2. system according to claim 1 is characterized in that, described boundary scan object of experiment device also comprises:
The simulating signal sample circuit; Be used to receive the test bus signal of said tap cell input; And according to the analog signal sampling of described test bus signal to described boundary scan object of experiment device; With the analog signal conversion of gathering is test response signal, turns back to described tap cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010131889 CN101819250B (en) | 2010-03-23 | 2010-03-23 | System for boundary scan experiment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010131889 CN101819250B (en) | 2010-03-23 | 2010-03-23 | System for boundary scan experiment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101819250A CN101819250A (en) | 2010-09-01 |
| CN101819250B true CN101819250B (en) | 2012-12-19 |
Family
ID=42654418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010131889 Expired - Fee Related CN101819250B (en) | 2010-03-23 | 2010-03-23 | System for boundary scan experiment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101819250B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102419415B (en) * | 2011-08-31 | 2014-07-02 | 北京时代民芯科技有限公司 | TAP (Test Access Port) interface optimization circuit based on boundary scanning circuit |
| CN104601697A (en) * | 2015-01-14 | 2015-05-06 | 浪潮电子信息产业股份有限公司 | Method for resource optimization of cloud experiment platform |
| CN105301479B (en) * | 2015-11-17 | 2017-12-01 | 中国航天科技集团公司第九研究院第七七一研究所 | A kind of variable chain length dynamic boundary Scan Architecture and method based on switch matrix control |
| CN106940956A (en) * | 2017-05-12 | 2017-07-11 | 师秦高雪 | A kind of electric signal transmission process shows simulation system |
| CN111579974B (en) * | 2020-06-09 | 2021-09-03 | 中国电子科技集团公司第十四研究所 | Embedded system for realizing boundary scan test and test method |
| CN114999562A (en) * | 2022-08-01 | 2022-09-02 | 深圳英集芯科技股份有限公司 | Method and system for testing digital logic chip by scan chain and electronic equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1580801A (en) * | 2003-08-04 | 2005-02-16 | 华为技术有限公司 | Boundary scanning-measuring method for circuit board |
-
2010
- 2010-03-23 CN CN 201010131889 patent/CN101819250B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1580801A (en) * | 2003-08-04 | 2005-02-16 | 华为技术有限公司 | Boundary scanning-measuring method for circuit board |
Non-Patent Citations (1)
| Title |
|---|
| 张西多.基于IEEE1149.4标准的混合电路边界扫描测试技术与方法的研究.《中国优秀硕士学位论文全文数据库 信息科技辑》.2006,(第10期),第2、8、24-26、29、38、49、50页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101819250A (en) | 2010-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101819250B (en) | System for boundary scan experiment | |
| US6988232B2 (en) | Method and apparatus for optimized parallel testing and access of electronic circuits | |
| CN105474178B (en) | Verifying and debugging based on programmable interface | |
| CN106649101B (en) | A kind of ICE automatization test system and test method | |
| US20040068699A1 (en) | Single board DFT integrated circuit tester | |
| CN101509948A (en) | Automobile electronic test system and test method thereof | |
| US7656726B2 (en) | Memory with improved BIST | |
| CN204789908U (en) | Circuit board automatic test system based on labVIEW | |
| CN103699017A (en) | Simulation test system and simulation test method for interface equipment of simulator in nuclear power station | |
| RU2402822C2 (en) | Stand for studying microcontroller control systems | |
| CN105469678B (en) | Synthesis experiment platform and its construction method based on NI myDAQ | |
| CN102353867A (en) | Interconnection test equipment and method | |
| CN201773514U (en) | Boundary scanning experiment target device and experimental system | |
| CN107526351A (en) | A kind of universal fault filling method and its device based on JTAG | |
| Sedmark | Boundary-scan: beyond production test | |
| Clark et al. | Infrastructure IP for configuration and test of boards and systems | |
| CN115656876A (en) | Micro short circuit test circuit and test method | |
| CN102565664B (en) | Evaluation method for testing coverage rate | |
| Jurj et al. | Hybrid testing of a solar tracking equipment using in-circuit testing and JTAG debugging strategies | |
| US20150039955A1 (en) | Systems and methods for Analog, Digital, Boundary Scan, and SPI Automatic Test Equipment | |
| Van Ngo et al. | Use of JTAG boundary-scan for testing electronic circuit boards and systems | |
| CN102645609B (en) | Joint test action group (JTAG) link circuit test device and test method of JTAG chain circuit test device | |
| CN116859894B (en) | Automatic test method for helicopter internal electronic regulator based on multi-agent technology | |
| CN109766292A (en) | A kind of jtag interface multiplexing functions circuit | |
| CN203054114U (en) | Electric-stress-applying aging device for product of class of PXI bus digital meter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121219 Termination date: 20130323 |