CN114999562A - Method and system for testing digital logic chip by scan chain and electronic equipment - Google Patents
Method and system for testing digital logic chip by scan chain and electronic equipment Download PDFInfo
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- CN114999562A CN114999562A CN202210917281.1A CN202210917281A CN114999562A CN 114999562 A CN114999562 A CN 114999562A CN 202210917281 A CN202210917281 A CN 202210917281A CN 114999562 A CN114999562 A CN 114999562A
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Abstract
The application provides a method, a system and an electronic device for testing a digital logic chip by a scan chain, wherein the system comprises: the singlechip flash memory is used for storing binary data of the scanning test; the singlechip is used for extracting the binary data from the flash memory of the singlechip after the chip to be tested is in a scanning mode and transmitting the binary data to the chip to be tested; the tested chip is used for feeding back a reply signal to the singlechip according to the binary data; and the singlechip is also used for determining whether the tested chip is qualified or not according to the reply signal. The technical scheme provided by the application has the advantage of low cost.
Description
Technical Field
The invention relates to the field of electronic equipment, in particular to a method and a system for testing a digital logic chip by using a scan chain and electronic equipment.
Background
The scan chain (SCAN CHAIN) test is a test method aiming at common digital logic chips, which sends out predefined excitation signals to the chip from the outside in a test starting mode through a test circuit pre-arranged in a digital logic part, and judges whether the digital logic part of the chip is normal or not by comparing output signals of the chip.
The existing SCAN CHAIN Test digital logic chip is implemented based on an FPGA (Field-Programmable Gate Array) or ATE (Automatic Test Equipment) machine, and the scheme is high in cost.
Disclosure of Invention
The embodiment of the invention provides a method, a system and electronic equipment for testing a digital logic chip by using a scan chain, which can realize SCAN CHAIN test of the digital logic chip by using a single chip microcomputer, thereby reducing the test cost.
In a first aspect, an embodiment of the present invention provides a scan chain test digital logic chip system, where the system includes: a singlechip, a chip to be tested and a singlechip flash memory, wherein,
the singlechip flash memory is used for storing binary data of the scanning test;
the singlechip is used for extracting the binary data from the flash memory of the singlechip after the chip to be tested is in a scanning mode and transmitting the binary data to the chip to be tested;
the tested chip is used for feeding back a reply signal to the singlechip according to the binary data;
and the singlechip is also used for determining whether the tested chip is qualified or not according to the reply signal.
In a second aspect, an embodiment of the present invention provides an implementation method for testing a digital logic chip by using a scan chain, where the method includes the following steps:
after the single chip microcomputer is initialized, controlling a chip to be tested to enter a scanning mode;
the single chip microcomputer extracts pre-stored binary data of the scanning test from the flash memory and injects the binary data into a chip to be tested;
the single chip microcomputer receives a reply signal fed back by the tested chip according to the binary data, and the single chip microcomputer determines whether the tested chip is qualified or not according to the reply signal.
In a third aspect, an electronic device is provided, where the electronic device includes a single chip, and the single chip is configured to execute an implementation method for testing a digital logic chip by using the scan chain provided by the second reverse side.
The embodiment of the invention has the following beneficial effects:
it can be seen that, when the SCAN CHAIN chain in the embodiment of the present application SCANs, the chip-related PIN inputs and outputs signals, where SCAN EN is an enable signal, and the PIN is set to a high level, which triggers the internal SCAN chain; the SCAN CLK is a signal output by the single chip IO and aims to provide a clock synchronization signal for the chip IP5516 to be tested; the SCAN IN is a signal output by the IO of the single chip microcomputer, and the signal inputs a high level or a low level to a chip to be tested when a CLK signal is turned each time according to a binary file downloaded into a FLASH of the single chip microcomputer; the SCAN OUT is an output signal of an internal scanned logic chain after the potential is injected into the IP5516 SCAN IN end every time, whether the logic chain of the current chip (namely the chip to be tested) can work normally or not can be known through comparing the signal with a binary file downloaded into a single chip FLASH, and the test cost is reduced by realizing SCAN CHAIN test of the digital logic chip through the single chip.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a scan chain test digital logic chip system;
FIG. 2 is a schematic diagram of a scan chain test digital logic chip system provided in the present application;
FIG. 3 is a schematic diagram of the logic states provided herein;
FIG. 4 is a schematic diagram of a scan chain test circuit provided in the present application;
FIG. 5 is a flowchart of an implementation method of a scan chain test digital logic chip provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," and "fourth," etc. in the description and claims of the invention and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, result, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a scan chain test digital logic chip system, as shown in fig. 1, the system may specifically include: the device comprises a test device and a chip to be tested, wherein the chip to be tested can be a digital logic chip, and the test device can be specifically: the testing device is used for performing Scan chain scanning on the tested chip, receiving a scanning result returned by the tested chip, and determining whether the tested chip passes or not according to the scanning result.
Based on an ATE scanning circuit, the advantages are simple circuit, concise programming, high price, huge ATE volume and inconvenient use. The SCAN CHAIN scan circuit based on FPGA has the advantages of simplicity, portability and the disadvantages of the need of designing the excitation source based on hardware description language programming, complex and not universal design, and the relative price of FPGA is also relatively expensive, so the cost of SCAN CHAIN test digital logic chip system as shown in FIG. 1 is high.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a scan chain test digital logic chip system provided in the present application, and as shown in fig. 2, the system may specifically include:
a single chip microcomputer, a chip to be tested and a single chip microcomputer flash (flash memory), wherein,
the singlechip flash is used for storing binary data of the Scan test;
the singlechip is used for extracting the binary data from the singlechip flash after the tested chip is in a Scan mode and transmitting the binary data to the tested chip;
the tested chip is used for feeding back a reply signal to the singlechip according to the binary data;
and the singlechip is also used for determining whether the tested chip is qualified or not according to the reply signal.
For example, the single chip microcomputer may specifically include: STM32, or GD32 PIN TO PIN.
For example, the Scan mode performed by the chip under test may specifically include:
the singlechip controls the tested chip to enter a Scan mode through a control interface (such as an IIC interface).
For example, the chip to be tested may specifically be: IP5516 (bluetooth headset charging bay power management chip of english-centered core) or other chips under test (bluetooth headset charging bay power management chips of other manufacturers).
For example, the binary data of the Scan test may specifically include: SCAN EN (SCAN enable) binary data, SCAN CLK (SCAN clock) binary data, SCAN IN (SCAN IN) binary data, and the reply signal may be: SCAN OUT (SCAN OUT) binary data.
The specific logic state diagram is shown in fig. 3.
When the SCAN CHAIN chain SCANs, the chip outputs and inputs signals of the relevant PIN, wherein SCAN EN is an enable signal, and the internal SCAN chain is triggered only when the PIN is set to be at a high level; the SCAN CLK is a signal output by the single chip IO and aims to provide a clock synchronization signal for the chip IP5516 to be tested; the SCAN IN is a signal output by the IO of the single chip microcomputer, and the signal inputs a high level or a low level to a chip to be tested when a CLK signal is turned each time according to a binary file downloaded into a FLASH of the single chip microcomputer; the SCAN OUT is an output signal of the scanned logic chain inside the chip to the outside after the potential is injected into the IP5516 SCAN IN end each time, and whether the logic chain of the current chip (i.e. the chip to be tested) can work normally can be known by comparing the signal with a binary file downloaded into a single chip FLASH. The test speed of 100Mhz can be realized to the maximum based on the environment of STM32, and the test speed of 50Mhz can be realized to the maximum based on the GD32 environment, and the SCAN CHAIN test digital logic chip is realized through the singlechip in the embodiment of the application, so that the test cost is reduced.
Referring to fig. 4, fig. 4 is a schematic diagram of an SCAN CHAIN test circuit provided by the present application, which is composed of SCAN CLK, SCAN EN, SCAN IN, and SCAN OUT as shown IN fig. 4, where SCAN CLK, SCAN IN, SCAN EN are input PINs and SCAN OUT is output PINs for the IP5516 being tested.
Referring to fig. 5, fig. 5 is a flowchart of an implementation method for testing a digital logic chip SCAN CHAIN according to the present application, where the method is shown in fig. 5, and specifically includes the following steps:
step S501, after the single chip microcomputer is initialized, controlling a chip to be tested to enter a Scan mode;
step S502, the singlechip extracts pre-stored binary data of Scan test from the flash and injects the binary data into a chip to be tested;
step S503, the single chip microcomputer receives a reply signal fed back by the chip to be tested according to the binary data, and the single chip microcomputer determines whether the chip to be tested is qualified or not according to the reply signal.
For example, the binary data of the Scan test may specifically include: the SCAN EN binary data, SCAN CLK binary data, and SCAN IN binary data, wherein the reply signal may be: SCAN OUT binary data.
The type of the single chip microcomputer and the type of the chip to be tested may be specifically described in the embodiment shown in fig. 2, and are not described herein again.
For example, the step of determining whether the chip under test is qualified according to the reply signal by the single chip microcomputer may specifically include:
and when the single chip microcomputer determines that the reply signal is wrong, determining that the chip to be tested is unqualified, and when the reply signal is correct, determining that the chip to be tested is qualified.
The above error or correct mode may specifically be: when SCAN EN is high level, the SCAN OUT binary data is consistent with the SCAN IN binary data, if so, the reply signal is determined to be correct, and if not, the reply signal is determined to be incorrect.
The application also provides an electronic device, which comprises a single chip microcomputer, wherein the single chip microcomputer is used for executing the steps of the method shown in the figure 5.
The present application also provides a computer-readable storage medium, in which a computer program is stored, which, when running on a single chip, performs the method provided in the embodiment shown in fig. 5.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the order of acts, as some steps may be performed in other orders or concurrently according to the present invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that the acts and modules illustrated are not necessarily required to practice the invention.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A scan chain test digital logic chip system, the system comprising: a single chip microcomputer, a chip to be tested and a single chip microcomputer flash memory, wherein,
the singlechip flash memory is used for storing binary data of the scanning test;
the singlechip is used for extracting the binary data from the flash memory of the singlechip after the chip to be tested carries out the scanning mode and transmitting the binary data to the chip to be tested;
the tested chip is used for feeding back a reply signal to the singlechip according to the binary data;
and the singlechip is also used for determining whether the tested chip is qualified or not according to the reply signal.
2. The system of claim 1,
and the singlechip is specifically used for controlling the tested chip to enter a scanning mode through the control interface.
3. The system of claim 1,
the binary data of the scan test specifically includes: scanning enable SCAN EN binary data, scanning clock SCAN CLK binary data and scanning input SCAN IN binary data; the above-mentioned reply signal is: SCAN OUT binary data.
4. The system of claim 3,
and the singlechip is specifically used for judging whether the SCAN output SCAN OUT binary data is consistent with the SCAN input SCAN IN binary data when the SCAN enable SCAN EN is at a high level, if so, determining that the tested chip is qualified, and if not, determining that the tested chip is unqualified.
5. An implementation method for testing a digital logic chip by using a scan chain is characterized by comprising the following steps:
after the single chip microcomputer is initialized, controlling a chip to be tested to enter a scanning mode;
the single chip microcomputer extracts pre-stored binary data of the scanning test from the flash memory and injects the binary data into a chip to be tested;
the single chip microcomputer receives a reply signal fed back by the tested chip according to the binary data, and the single chip microcomputer determines whether the tested chip is qualified or not according to the reply signal.
6. The method of claim 5, wherein the controlling the tested chip to enter Scan mode
The single chip microcomputer controls the tested chip to enter a scanning mode through the control interface.
7. The method of claim 5,
the binary data of the scan test specifically includes: scanning enable SCAN EN binary data, scanning clock SCAN CLK binary data and scanning input SCAN IN binary data; the above-mentioned reply signal is: SCAN OUT binary data.
8. The method of claim 7, wherein the determining whether the tested chip is qualified according to the reply signal by the single chip microcomputer specifically comprises:
when the SCAN enable SCAN EN is at a high level, whether the SCAN output SCAN OUT binary data is consistent with the SCAN input SCAN IN binary data or not is determined, if so, the tested chip is determined to be qualified, and if not, the tested chip is determined to be unqualified.
9. An electronic device, comprising a single chip, wherein the single chip is configured to execute the method for implementing the scan chain test digital logic chip according to any one of claims 5 to 8.
10. A computer-readable storage medium, in which a computer program is stored which, when run on a single chip, performs the method according to any one of claims 5-8.
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| CN202210917281.1A CN114999562A (en) | 2022-08-01 | 2022-08-01 | Method and system for testing digital logic chip by scan chain and electronic equipment |
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| CN101819250A (en) * | 2010-03-23 | 2010-09-01 | 徐磊 | Method, system and target device for boundary scan experiment |
| CN104133171A (en) * | 2014-07-31 | 2014-11-05 | 中国人民解放军空军预警学院 | Simple boundary scan test system and method based on single-chip microcomputer |
| CN109557458A (en) * | 2018-12-26 | 2019-04-02 | 中国电子科技集团公司第四十研究所 | One kind being suitable for electronic equipment digital-to-analog circuit embedded test system |
| CN111337820A (en) * | 2020-04-24 | 2020-06-26 | 江西联智集成电路有限公司 | Digital chip scan chain test method, device, equipment and medium |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101819250A (en) * | 2010-03-23 | 2010-09-01 | 徐磊 | Method, system and target device for boundary scan experiment |
| CN104133171A (en) * | 2014-07-31 | 2014-11-05 | 中国人民解放军空军预警学院 | Simple boundary scan test system and method based on single-chip microcomputer |
| CN109557458A (en) * | 2018-12-26 | 2019-04-02 | 中国电子科技集团公司第四十研究所 | One kind being suitable for electronic equipment digital-to-analog circuit embedded test system |
| CN111337820A (en) * | 2020-04-24 | 2020-06-26 | 江西联智集成电路有限公司 | Digital chip scan chain test method, device, equipment and medium |
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