CN101808460B - Routing method for PCB and PCB - Google Patents
Routing method for PCB and PCB Download PDFInfo
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- CN101808460B CN101808460B CN201010143614.7A CN201010143614A CN101808460B CN 101808460 B CN101808460 B CN 101808460B CN 201010143614 A CN201010143614 A CN 201010143614A CN 101808460 B CN101808460 B CN 101808460B
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Abstract
The invention discloses a routing method for a PCB and the PCB. The routing method comprises the following steps: determining line delay of gating signals of the PCB relative to clock signals; setting the routing of the gating signals of the PCB and the routing of the clock signals of the PCB, so that the length difference between the routings corresponds to the line delay. Through the technical scheme provided by the invention, the PCB has a relatively loose routing space, and a receiver can receive data signals in a correct time sequence simultaneously.
Description
Technical field
This method relates to art of printed circuit boards, particularly for wiring method and the PCB of PCB.
Background technology
Along with the extensive raising of system complexity and integrated level, the operating frequency of bus has also reached or has exceeded 50MHz, and what have even exceedes 100MHz.At present, the clock frequency of approximately 50% design exceedes 50MHz, and nearly 20% design dominant frequency exceedes 120MHz.When system works is during at 50MHz, to produce transmission line effect and problems of Signal Integrity, and in the time that system clock reaches 120MHz, unless used High-speed Board Design knowledge, otherwise the PCB based on conventional method design cannot work, therefore, High-speed Board Design technology has become the design means that electronic system design Shi Bixu takes.
It has been generally acknowledged that if the frequency of Digital Logical Circuits reaches or exceedes 45MHz-50MHz, and the circuit being operated on this frequency accounts for the component that whole electronic system is certain (such as 1/3), just become high speed circuit.In fact, the harmonic frequency at signal edge is higher than the frequency of signal itself, it is the unexpected result that the fast-changing rising edge of signal and trailing edge (or saltus step of title signal) have caused signal transmission, therefore, if agreement transmission line propagation delay is greater than the rise time of 1/2 digital signal drive end conventionally, think that this type of signal is high speed signal and produces transmission line effect.The length of pcb board upward wiring can affect effective transmission of signal, and the time delay meeting that long PCB cabling causes affects the sequential of receiving terminal.
Prior art adopts following two kinds of methods conventionally to PCB layout: 1, strictly isometric to clock signal and gating signal wiring.2, the wiring difference of the upper clock signal of PCB and gating signal is less than 500 inches.Through the actual verification to PCB cabling, as long as meet the requirement of the time delay of drive end and receiving terminal clock signal and gating signal simultaneously, be to allow the time delay of upper PCB clock signal and gating signal to be controlled within certain scope.Therefore, no matter adopt above-mentioned which kind of existing PCB layout method, it is all the circuit design from drive end and receiving terminal, guarantee the sequential of receiving terminal by controlling relation between clock signal and gating signal, but ignored time delay on PCB cabling to controlling the impact of clock signal and gating signal.
To sum up analyzing, there is the coarse problem of difference that the upper gating signal of PCB and clock signal track lengths are set in existing PCB layout method, and in prior art, strictly constraining in the more nervous situation of wiring space of PCB layout is difficult to realize.
Summary of the invention
Main purpose of the present invention is to provide a kind of wiring method for PCB and PCB, has to solve existing PCB layout method the coarse problem of difference that the upper gating signal of PCB and clock signal track lengths are set.
According to an aspect of the present invention, provide a kind of wiring method for PCB, having comprised: determined the cabling time delay of the upper gating signal of PCB with respect to clock signal; The wiring of gating signal of PCB and the wiring of the clock signal of PCB are set, make the length difference of wiring corresponding to cabling time delay.
Further, determine that the upper gating signal of PCB comprises with respect to the cabling time delay of clock signal: obtain the first time delay, wherein, the first time delay be on drive end gating signal with respect to the time offset of clock signal; Determine the second time delay, wherein, the second time delay be on receiving terminal gating signal with respect to the time offset of clock signal; Determine the cabling time delay of the upper gating signal of PCB with respect to clock signal according to the difference of the first time delay and the second time delay.
Further, obtaining the first time delay comprises: the gating signal of obtaining drive end with respect to the delay parameter of clock signal as the first time delay.
Further, determine that the second time delay comprises: according to determining the 3rd time delay the settling time of the gating signal of receiving terminal; Determine the 4th time delay according to the retention time of the gating signal of receiving terminal; Obtain on receiving terminal gating signal with respect to the delay parameter that writes order as the 5th time delay; Select the minimum value of the 3rd time delay, the 4th time delay and the 5th time delay as the second time delay.
Further, according to determining that the 3rd time delay comprises the settling time of the gating signal of receiving terminal: determine the 3rd time delay: T according to following rule
sKEW1=T-T
w-T
dSS, wherein, T
sKEW1be the 3rd time delay, the clock cycle that T is clock signal, T
wfor a time migration corresponding to pulsewidth of gating signal, T
dSSfor the settling time of the gating signal of receiving terminal.
Further, above-mentioned T
dSSminimum is 0.2 described clock cycle.
Further, determine that according to the retention time of the gating signal of receiving terminal the 4th time delay comprises: determine the 4th time delay: T according to following rule
sKEW2=T
w-T
dSH, wherein, T
sKEW2be the 4th time delay, T
wfor a time migration corresponding to pulsewidth of gating signal, T
dSHfor the retention time of the gating signal of receiving terminal.
Further, above-mentioned T
dSHminimum is 0.2 clock cycle.
According to a further aspect in the invention, provide a kind of PCB, having comprised: the wiring of gating signal and the wiring of clock signal, the length difference of wiring is the cabling time delay with respect to clock signal corresponding to the upper gating signal of PCB.
Further, the upper gating signal of PCB is determined with respect to the difference of the time offset of clock signal with respect to gating signal on the time offset of clock signal and receiving terminal by gating signal on drive end with respect to the cabling time delay of clock signal.
By the present invention, adopt definite clock signal and the gating signal method in the time delay of PCB upward wiring, the poor of track lengths between the upper clock signal of PCB and gating signal is set, solve existing PCB layout method and had the coarse problem of difference that the upper gating signal of PCB and clock signal track lengths are set, and then guarantee to have on PCB under the prerequisite of relatively loose wiring space, receiving terminal can receive data-signal with correct sequential.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is according to the structural representation of the source synchronous clock system of the embodiment of the present invention;
Fig. 2 is according to the flow chart of the wiring method for PCB of the embodiment of the present invention;
Fig. 3 is the flow chart with respect to the cabling time delay of clock signal according to the upper gating signal of definite PCB of the embodiment of the present invention;
Fig. 4 sets up schematic diagram according to the source synchro system sequential of the embodiment of the present invention;
Fig. 5 is the receiving terminal gating signal sequential chart according to the embodiment of the present invention;
Fig. 6 is the DDR receiving terminal system sequential chart according to the embodiment of the present invention;
Fig. 7 is the flow chart of determining according to the preferred embodiment of the invention the time delay of PCB cabling.
Embodiment
Hereinafter also describe the present invention in detail with reference to accompanying drawing in conjunction with the embodiments.It should be noted that, in the situation that not conflicting, the feature in embodiment and embodiment in the application can combine mutually.
The embodiment of the present invention is applicable to the wiring method of the high speed parallel bus of PCB, be specially adapted to the PCB layout stage of source synchronous clock system, the track lengths difference of processing clock signal and gating signal, for example, the receiving terminal of determining PCB is Double Data Rate synchronous DRAM (Double Data Rate SDRAM, be called for short DDR) after, according to the clock frequency of DDR and time delay feature, determine the track lengths difference of the upper clock signal of PCB and gating signal.
Fig. 1 is according to the structural representation of the source synchronous clock system of the embodiment of the present invention.As shown in Figure 1, drive end (driving chip) has also produced gating signal (Strobe) in sending data-signal, the order that writes that receiving terminal (for example DDR) provides according to clock signal effectively receives gating signal DQS, and the trigger of receiving terminal reading by these gating signal control data.
According to the embodiment of the present invention, first a kind of wiring method for PCB is provided, Fig. 2 is that as shown in Figure 2, the method comprises according to the flow chart of the wiring method for PCB of the embodiment of the present invention:
Step S202, determines the cabling time delay of the upper gating signal of PCB with respect to clock signal;
Step S204, arranges the wiring of gating signal of PCB and the wiring of the clock signal of PCB, makes the length difference of wiring corresponding to this cabling time delay.
In source synchronous clock system, drive chip to produce gating signal in sending data-signal, and the trigger of receiving terminal is synchronous transmission by readout data signal and the source synchronous clock signal of these gating signal control data.Therefore,, if the sequential of transmitting terminal is correct, as long as guarantee that the flight time of these two signals is in full accord, also can obtain right-on sequential at receiving terminal so.The stability of whole system in sequential is embodied in the matching degree of data and gating signal completely, comprises the coupling of transmission delay, and coupling of device performance etc., as long as both conditions are identical, just can guarantee that the sequential of system is absolutely correct.
The research of existing method to clock signal and gating signal time delay, time delay between clock signal and the gating signal of the main circuit by control drive end and receiving terminal, guarantee the correct sequential of the data receiver of receiving terminal, but in design on PCB, ignore the time delay allowed band of clock signal and gating signal, just strictly follow handbook regulation, or the line design of clock signal and gating signal walks isometricly, or the line design of clock signal and gating signal differs 500 inches.
In actual applications, by analysis and checking, time delay between clock signal and gating signal is often different at drive end and receiving terminal both sides, this just means that the upper clock signal of PCB and gating signal have allowed time delay, the in the situation that of wiring space anxiety, the parallel routing of PCB can arrange according to the time delay difference between receiving terminal and transmitting terminal both sides clock signal and gating signal, so not only make the wiring of PCB more flexible, and can not affect receiving terminal with correct sequential reception data-signal.
Based on above-mentioned analysis, the wiring method for PCB that the embodiment of the present invention provides considers that transmitting terminal is different to the delay constraint of clock signal and gating signal with receiving terminal both sides, in the case of meeting transmitting terminal and receiving terminal to the delay requirement of clock signal and gating signal, carry out above-mentioned steps S202, determine the cabling time delay of the upper gating signal of CB with respect to clock signal, again according to this cabling time delay, execution step S204, the wiring of gating signal of PCB and the wiring of the clock signal of PCB are set, make the length difference of wiring corresponding to this cabling time delay.
The wiring method of the PCB providing according to the embodiment of the present invention, solve existing PCB layout method and had the coarse problem of difference that the upper gating signal of PCB and clock signal track lengths are set, both having guaranteed is having relatively loose wiring space on PCB, guaranteed that again receiving terminal can receive data-signal with correct sequential.
Preferably, in step S202, can determine by the following method the cabling time delay of the upper gating signal of PCB with respect to clock signal, as shown in Figure 3, determine that the upper gating signal of PCB comprises the following steps with respect to the cabling time delay of clock signal:
Step S302, obtains the first time delay, wherein, the first time delay be on drive end gating signal with respect to the time offset of clock signal;
Step S304, determines the second time delay, wherein, the second time delay be on receiving terminal gating signal with respect to the time offset of clock signal;
Step S306, determines the cabling time delay of the upper gating signal of PCB with respect to clock signal according to the difference of the first time delay and the second time delay.
In above-mentioned analysis by analysis the upper gating signal of definite PCB with respect to the cabling time delay of clock signal according to being: the gating signal allowing on drive end is with respect to the time offset of clock signal, and the gating signal allowing on receiving terminal is with respect to the time offset of clock signal.Therefore,, by carrying out above-mentioned steps S302-S306, can determine the cabling time delay of the upper gating signal of PCB with respect to clock signal.
Be actually a limiting value according to the upper gating signal of the definite PCB of said method with respect to the cabling time delay of clock signal, as long as in the time of Design PCB parallel bus, the concrete cabling time delay with respect to clock signal of gating signal is less than this limiting value, can guarantee that receiving terminal can receive data-signal with correct sequential.
Can determine accurately that according to above-mentioned steps S302-S306 PCB goes up gating signal and clock signal is walked wire delay, then this is walked within wire delay is controlled at drive end and receiving terminal allowed band, like this PCB layout do not need strictly to walk isometric or strictly follow wiring difference be 500 inches, make the cloth line options of PCB relatively flexible, be easy to realize.
Preferably, the gating signal that can obtain drive end with respect to the delay parameter of clock signal as above-mentioned the first time delay.
Fig. 4 sets up schematic diagram according to the source synchro system sequential of the embodiment of the present invention.As shown in Figure 4, gating signal (DQS) and clock signal (CK) have a relative time delay Tco strobe in driving element inside.If transmitting terminal is FPGA, its inside can stipulate the whole Tco strobe of key within the scope of relative time delay at FPGA, if transmitting terminal is CPU or DSP, its inside does not artificially arrange the function of Tco strobe, but we can obtain the time delay Tco strobe between gating signal DQS and clock signal of system CK from device handbook by CPU or DSP.Also can be by test gating signal (DQS) and clock signal (CK) relative time delay in driving element inside in actual scene, to obtain relative time delay value more accurately.
Delay parameter according to the gating signal of drive end with respect to clock signal, can facilitate and also obtain exactly above-mentioned the first time delay.
Preferably, can determine by the following method the time offset (be above-mentioned second time delay) of gating signal with respect to clock signal: according to determining the 3rd time delay the settling time of the gating signal of receiving terminal; Determine the 4th time delay according to the retention time of the gating signal of receiving terminal; Obtain on receiving terminal gating signal with respect to the delay parameter that writes order as the 5th time delay; Select the minimum value of the 3rd time delay, the 4th time delay and the 5th time delay as the second time delay.
As shown in Figure 5, the gating signal of receiving terminal is within a gating cycle, comprise gating signal that the retention time receiving terminal of settling time, the gating signal of gating signal the allows time offset (above-mentioned the second time delay) with respect to clock signal, need to meet following three conditions:
Condition one, DQS and CK will meet T at receiving terminal
dQSS(being above-mentioned the 5th time delay), T
dQSSreferring to that DQS is with respect to writing the time of delay that order is CK, why have so delay design, is also effectively to receive DQS signal and data-signal in order to guarantee that receiving terminal can be received.
Condition two, the relative CK of DQS will guarantee (T settling time at receiving terminal
dSS) abundance, take the sequential chart shown in Fig. 6 as example, as shown in the CASE 1 of Fig. 6, DQS trailing edge apart from the time of the next rising edge of CK be T
dSS, and T
dSSminimum is 0.2 clock cycle.
Condition three, the relative CK of DQS will guarantee retention time (T at receiving terminal
dSH) abundance, take the sequential chart shown in Fig. 6 as example, as shown in the CASE 2 of Fig. 6, DQS trailing edge apart from the time of a upper rising edge of CK be T
dSH, and T
dSHminimum is 0.2 clock cycle.
Respectively according to above-mentioned three conditions, determine in each condition that gating signal is with respect to the time offset of clock signal, be above-mentioned the 3rd time delay, the 4th time delay and the 5th time delay, select therein gating signal that minimum value allows as receiving terminal with respect to the time offset of clock signal, just guaranteed that DQS can correctly read receiving end by frame of reference clock CK.It should be noted that determining in no particular order of above-mentioned the 3rd time delay, the 4th time delay and the 5th time delay, can carry out simultaneously, also can optionally arrange sequencing, as long as complete definite work of the 3rd time delay, the 4th time delay and the 5th time delay, can select therein gating signal that minimum value allows as receiving terminal with respect to the time offset (being above-mentioned the second time delay) of clock signal.
The gating signal that definite receiving terminal allows by the way, with respect to the time offset (being above-mentioned the second time delay) of clock signal, has been considered T simultaneously
dQSS, T
dSHand T
dSH, the gating signal that receiving terminal is allowed is more accurate with respect to the time offset of clock signal.
Preferably, can determine above-mentioned the 3rd time delay: T according to following rule
sKEW1=T-T
w-T
dSS, wherein, T
sKEW1be the 3rd time delay, the clock cycle that T is clock signal, T
wfor a time migration corresponding to pulsewidth of gating signal, T
dSSfor the settling time of the gating signal of receiving terminal.
The DDR receiving terminal system sequential chart that Fig. 6 is, this sequential chart has specifically described by T
sKEW1, T
wand T
dSSrelation, because DDR only allows to carry out data judgement at rising edge clock, therefore, as shown in the CASE1 of Fig. 6, within the clock cycle of T4 to T5, in a clock cycle T, comprised T
sKEW1, T
wand T
dSS, therefore, the 3rd time delay is really established rules and can is: T
sKEW1=T-T
w-T
dSS.
Above-mentioned T, T
wand T
dSSin the handbook of the device that all can be adopted by receiving terminal, obtain design parameter value or value range, also can obtain concrete parameter value by actual measurement, therefore, can pass through formula T
sKEW1=T-T
w-T
dSScan determine exactly the 3rd time delay.It should be noted that T
dSSminimum can be 0.2 clock cycle, in specific implementation process, can, according to concrete receiving terminal requirement on devices, T be set
dSS.
Preferably, T
dSS0.2 clock cycle of value, can make the 3rd time delay of determining for maximum, thereby has determined the limiting case of the 3rd time delay.
By above-mentioned formula T
sKEW1=T-T
w-T
dSSthe 3rd time delay of determining, in the time determining that gating signal that receiving terminal allows is with respect to the time migration of clock signal, guarantee abundance settling time of gating signal, thereby made the 3rd time delay determined more accurate, and the second time delay of determining thus has theoretical foundation, has more practicality.
Preferably, can determine above-mentioned the 4th time delay: T according to following rule
sKEW2=T
w-T
dSH, wherein, T
sKEW2be the 3rd time delay, T
wfor a time migration corresponding to pulsewidth of gating signal, T
dSHfor the retention time of the gating signal of receiving terminal.
As shown in the CASE2 of Fig. 6, in upper 1/4 clock cycle of T4 to the pulsewidth time of 1/4 clock cycle of the next one of T4, T
wcomprise T
sKEW2, T
dSH, therefore, the 4th time delay is really established rules and can is: T
sKEW2=T
w-T
dSH.
Above-mentioned T
wand T
dSHin the handbook of the device that all can be adopted by receiving terminal, obtain design parameter value or value range, also can obtain concrete parameter value by actual measurement, therefore, can pass through formula T
sKEW2=T
w-T
dSHcan determine exactly the 4th time delay.It should be noted that T
dSHminimum can be 0.2 clock cycle, in specific implementation process, can, according to concrete receiving terminal requirement on devices, T be set
dSH.
Preferably, T
dSH0.2 clock cycle of value, can make the 4th time delay of determining for maximum, thereby has determined the limiting case of the 4th time delay.
By above-mentioned formula T
sKEW2=T
w-T
dSHthe 4th time delay of determining, in the time determining that gating signal that receiving terminal allows is with respect to the time migration of clock signal, guarantee the retention time abundance of gating signal, thereby made the 4th time delay determined more accurate, and the second time delay of determining thus has theoretical foundation, has more practicality.
Below in conjunction with concrete preferred embodiment, the above-mentioned wiring method for PCB is described in detail.
The preferred embodiment is the skew between the constraint to DQS and CK and transmitting terminal DQS and CK by receiving terminal, calculates the maximum cabling time delay that clock signal C K and gating signal DQS allow on PCB.Fig. 7 is the flow chart of determining according to the preferred embodiment of the invention the time delay of PCB cabling, and as shown in Figure 7, the method comprises:
Step S701, determine DQS pulsewidth allow excursion T
w, DQS (T settling time
dSS) and retention time (T
dSH);
Step S702, while calculating the settling time of the gating signal of guaranteeing receiving terminal, the deviation range T that the DQS of receiving terminal and CK allow
sKEW1, according to T
sKEW1=T-T
w-T
dSScalculate T
sKEW1;
Step S703, while calculating the retention time of the gating signal of guaranteeing receiving terminal, the deviation range T that DQS and CK allow
sKEW2, according to T
sKEW2=T
w-T
dSHcalculate T
sKEW2;
Step S704, determines that receiving terminal correctly receives the necessary condition of DQS, and DQS writes the relative time delay T of order relatively
dQSS;
Step S705, gets above-mentioned T
sKEW1, T
sKEW2and T
dQSSminimum value be the deviation range T that receiving terminal DQS and CK allow
sKEW, i.e. T
sKEW=min (T
sKEW1, T
sKEW2, T
dQSS);
Step S706, determines on drive end that gating signal is with respect to the output offset T of clock signal
co strobe;
Step S707, calculates the cabling skew T allowing on PCB
pCB_SKEW=T
sKEW-T
co strobe.
In order to meet the requirement of receiving terminal sequential, the difference of the track lengths between gating signal DQS and clock signal of system CK can not be greater than the value of this calculating.In PCB layout, just can calculate by this method the maximum delay that gating signal DQS and clock signal of system allow on cabling.
According to the embodiment of the present invention, a kind of PCB is also provided, this PCB comprises the wiring of gating signal and the wiring of clock signal, the length difference of the two wiring is the cabling time delay with respect to clock signal corresponding to the upper gating signal of PCB.
Existing PCB is aspect parallel bus wiring, strictly follow handbook regulation, or the line design of clock signal and gating signal is walked isometric, or the line design of clock signal and gating signal differs 500 inches, the PCB providing according to the embodiment of the present invention is different from existing PCB, can be aspect parallel bus wiring, according to drive end and receiving terminal to gating signal the poor definite length of arrangement wire difference of time migration with respect to clock signal.Both having guaranteed is having relatively loose wiring space on PCB, guaranteed that again receiving terminal can receive data-signal with correct sequential.
Preferably, the upper gating signal of PCB is with respect to the cabling time delay of clock signal, and the wiring method of above-mentioned any one PCB that can provide by the embodiment of the present invention is determined.Particularly.Determine PCB upper gating signal cabling time delay with respect to clock signal with respect to gating signal on the time offset of clock signal and receiving terminal with respect to the difference of the time offset of clock signal by gating signal on drive end.
Above-mentioned preferred PCB, the upper gating signal of PCB and clock signal can be set exactly and walk wire delay scope, this is walked within wire delay is controlled at drive end and receiving terminal allowed band, PCB layout do not need strictly to walk isometric or strictly follow wiring difference be 500 inches, make the cloth line options of PCB relatively flexible, be easy to realize.
From above description, can find out, by technical scheme provided by the invention, determine the time delay of gating signal DQS relative system clock signal C K on PCB cabling, thereby within the difference of both length being limited in to allowed scope in PCB layout, can guarantee like this to have relatively loose wiring space on PCB, make receiving terminal receive data-signal with correct sequential simultaneously.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (7)
1. for a wiring method of PCB, it is characterized in that, comprising:
Determine the cabling time delay of the upper gating signal of PCB with respect to clock signal;
The wiring of gating signal of described PCB and the wiring of the clock signal of described PCB are set, make the length difference of described wiring corresponding to described cabling time delay;
Wherein, the upper gating signal of described definite PCB comprises with respect to the cabling time delay of clock signal:
Obtain the first time delay, wherein, described the first time delay be on drive end gating signal with respect to the time offset of clock signal;
Determine the second time delay, wherein, described the second time delay be on receiving terminal gating signal with respect to the time offset of clock signal;
Determine the cabling time delay of the upper gating signal of PCB with respect to clock signal according to the difference of described the first time delay and described the second time delay;
Determine that described the second time delay comprises:
According to determining the 3rd time delay the settling time of the gating signal of described receiving terminal;
Determine the 4th time delay according to the retention time of the gating signal of described receiving terminal;
Obtain on described receiving terminal gating signal with respect to the delay parameter that writes order as the 5th time delay;
Select the minimum value of described the 3rd time delay, described the 4th time delay and described the 5th time delay as described the second time delay.
2. method according to claim 1, is characterized in that, obtains described the first time delay and comprises: the gating signal of obtaining described drive end with respect to the delay parameter of clock signal as described the first time delay.
3. method according to claim 1, is characterized in that, according to determining that the 3rd time delay comprises the settling time of the gating signal of described receiving terminal: determine described the 3rd time delay: T according to following rule
sKEW1=T-T
w-T
dSS, wherein, T
sKEW1for described the 3rd time delay, the clock cycle that T is described clock signal, T
wfor a time migration corresponding to pulsewidth of gating signal, T
dSSfor the settling time of the gating signal of described receiving terminal.
4. method according to claim 3, is characterized in that, described T
dSSminimum is 0.2 described clock cycle.
5. method according to claim 1, is characterized in that, determines that the 4th time delay comprises: determine described the 4th time delay: T according to following rule according to the retention time of the gating signal of described receiving terminal
sKEW2=T
w-T
dSH, wherein, T
sKEW2for described the 4th time delay, T
wfor a time migration corresponding to pulsewidth of gating signal, T
dSHfor the retention time of the gating signal of described receiving terminal.
6. method according to claim 5, is characterized in that, described T
dSHminimum is 0.2 clock cycle.
7. a PCB, is characterized in that, comprising: the wiring of gating signal and the wiring of clock signal, and the length difference of described wiring is the cabling time delay with respect to clock signal corresponding to the upper gating signal of described PCB;
The upper gating signal of described PCB is determined with respect to the difference of the time offset of clock signal with respect to gating signal on the time offset of clock signal and receiving terminal by gating signal on drive end with respect to the cabling time delay of clock signal;
Wherein, on receiving terminal, gating signal is the minimum value in following determined time delay with respect to the time offset of clock signal:
According to definite time delay settling time of the gating signal of described receiving terminal, according to the definite time delay of the retention time of the gating signal of described receiving terminal, the time delay definite with respect to the delay parameter that writes order according to gating signal on described receiving terminal.
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| CN103716981B (en) * | 2013-12-30 | 2017-11-17 | 惠州Tcl家电集团有限公司 | The PCB and its wiring method of stable clock signal |
| CN103973292A (en) * | 2014-05-12 | 2014-08-06 | 浪潮电子信息产业股份有限公司 | Method for facilitating PCB transmission delay compensation of complex topology signal |
| CN105930241B (en) * | 2016-05-05 | 2018-06-08 | 福州瑞芯微电子股份有限公司 | The phase adjusting method and device of EMMC interfaces and NAND Interface |
| CN107478868A (en) * | 2017-07-31 | 2017-12-15 | 郑州云海信息技术有限公司 | A kind of signal testing plate for realizing different delayed time function and its design method |
| CN107466155B (en) * | 2017-08-09 | 2020-10-09 | 晶晨半导体(上海)股份有限公司 | Method for realizing equal time length of signal transmission on parallel signal line |
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| CN107526893B (en) * | 2017-09-05 | 2021-03-12 | 立讯精密工业（滁州）有限公司 | High-speed signal equal-length control algorithm, PCB wiring method and PCB |
| CN111381104A (en) * | 2018-12-29 | 2020-07-07 | 中兴通讯股份有限公司 | Method and device for measuring impedance of transmission channel |
| CN111327500B (en) * | 2020-01-21 | 2022-04-22 | 苏州浪潮智能科技有限公司 | NCSI bus construction method, device, equipment and storage medium |
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| US5889682A (en) * | 1994-09-09 | 1999-03-30 | Fujitsu Limited | Clock routing design method using a hieraichical layout design |
| US20040155690A1 (en) * | 2003-02-11 | 2004-08-12 | Lattice Semiconductor Corporation | Adaptive input logic for phase adjustments |
| CN101419482A (en) * | 2007-10-25 | 2009-04-29 | 船井电机株式会社 | Circuit and design method and electric device |
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