CN107526893B - High-speed signal equal-length control algorithm, PCB wiring method and PCB - Google Patents

High-speed signal equal-length control algorithm, PCB wiring method and PCB Download PDF

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CN107526893B
CN107526893B CN201710790808.8A CN201710790808A CN107526893B CN 107526893 B CN107526893 B CN 107526893B CN 201710790808 A CN201710790808 A CN 201710790808A CN 107526893 B CN107526893 B CN 107526893B
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pcb
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CN107526893A (en
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杨江云
戴玉瑶
叶剑兵
赵云
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Luxshare Precision Industry Chuzhou Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

The invention discloses a high-speed signal equal-length control algorithm, a PCB wiring method and a PCB, wherein the high-speed signal equal-length control algorithm comprises the following steps: based on a preset 10-degree principle, determining equal-length tolerance according to a signal transmission period and a clock period so as to meet the time sequence requirement of a system; and obtaining the control range of the same length of the high-speed signal according to the ratio of the equal length tolerance to the signal delay rate. The embodiment of the invention calculates the isometric tolerance of the high-speed signal and the isometric control range of the high-speed signal based on the preset 10-degree principle, provides a design principle and algorithm with theoretical support for the isometric processing of key signals for the current high-speed circuit PCB design, is simple and practical, and can greatly improve the working efficiency of PCB design engineers while meeting the time sequence requirement of a system.

Description

High-speed signal equal-length control algorithm, PCB wiring method and PCB
Technical Field
The embodiment of the invention relates to the technical field of electronics, in particular to a high-speed signal equal-length control algorithm, a PCB wiring method and a PCB.
Background
With the rapid advancement of electronics technology, the integration technology of electronic transistors has grown exponentially according to moore's law. As the frequency of electronic signals is faster and steeper, the edge of the signals is steeper and steeper, and the wavelength of the signals is shorter and shorter, the time control for receiving and transmitting the signals is also required to be in the picosecond (ps) level, so that the distribution parameters of a Printed Circuit Board (PCB) cannot be ignored, and the time difference control for transmitting and receiving the signals is more and more important.
At present, high-speed circuit design and signal integrity analysis are in the industry which is just rising, and there are a lot of empirical principles for the receiving and sending of high-speed signals and the control of delay time required by time sequence between signals, but the empirical principles only restrict the equal length tolerance of a PCB (printed circuit board) in a physical layer when the signal requirement is changed, and the requirement of a system on the signal transmission time cannot be met when the signal requirement is changed, so that the time sequence is wrong, and the system cannot work normally.
Disclosure of Invention
The invention provides a high-speed signal equal-length control algorithm, a PCB wiring method and a PCB, which provide a design principle and an algorithm with theoretical support for equal-length processing of key signals in the current high-speed circuit PCB design, and improve the working efficiency of PCB design engineers while meeting the system time sequence requirement.
The embodiment of the invention provides a high-speed signal equal-length control algorithm, which comprises the following steps:
based on a preset 10-degree principle, determining equal-length tolerance according to a signal transmission period and a clock period so as to meet the time sequence requirement of a system;
and obtaining the control range of the same length of the high-speed signal according to the ratio of the equal length tolerance to the signal delay rate.
Further, based on the preset 10 ° principle, determining the equal length tolerance according to the signal transmission cycle and the clock cycle includes:
obtaining a signal period ratio according to the ratio of a preset signal period to the signal transmission period, wherein the preset signal period is 10 degrees;
the equal length tolerance is obtained from the product of the ratio of the clock period to the signal period.
Further, the signal transmission period is 360 °.
The embodiment of the invention also provides a PCB wiring method, which comprises the following steps:
determining the relative delay range of the longest signal line and the shortest signal line of each group of signal lines on the PCB for transmitting signals according to the signal transmission period and the clock period based on the preset 10-degree principle;
determining a length difference range of the longest signal line and the shortest signal line according to the ratio of the relative delay range to the signal delay rate;
and setting each group of signal lines so that the length difference between the longest signal line and the shortest signal line of each group of signal lines is within the length difference range.
Further, based on a preset 10 ° principle, determining, according to a signal transmission period and a clock period, a relative delay range of the longest signal line and the shortest signal line of each group of signal lines on the PCB for transmitting signals includes:
obtaining a signal period ratio according to the ratio of a preset signal period to the signal transmission period, wherein the preset signal period is 10 degrees;
determining a product of the clock period and the signal period ratio as the relative delay range.
Further, each set of signal lines includes a data signal line and a clock signal line.
Further, the data signal line includes a single-ended signal line or a differential signal line.
The embodiment of the invention also provides a PCB, which comprises at least one group of signal wires; and each group of signal lines is arranged by adopting the PCB wiring method.
The high-speed signal equal-length control algorithm, the PCB wiring method and the PCB provided by the embodiment of the invention calculate the equal-length tolerance of the high-speed signal and the equal-length control range of the high-speed signal based on the preset 10-degree principle, provide a design principle and algorithm with theoretical support for the equal-length processing of key signals for the current high-speed circuit PCB design, are simple and practical, and can greatly improve the working efficiency of PCB design engineers while meeting the time sequence requirement of a system.
Drawings
Fig. 1 is a schematic flow chart of an isometric control algorithm for high-speed signals according to an embodiment of the present invention;
FIG. 2 is a flow chart of an isometric tolerance calculation method according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart of a PCB wiring method provided by an embodiment of the invention;
fig. 4 is a flowchart illustrating a method for determining a relative delay range according to an embodiment of the present invention;
FIGS. 5-9 are simulation diagrams of signals at the same time and at different lengths according to an embodiment of the present invention;
fig. 10 is a schematic diagram of signal transmission and reception under the preset 10 ° principle according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As is known, when a signal is transmitted on a signal line, a delay is generated, and if a transmission distance of a single-ended signal is long, the delay is also large, so that a relative delay exists between two signals (such as a differential signal or a data signal and a clock signal), which is equivalent to a phase shift of one of the signals, and a signal received by a receiving end is distorted to some extent. If the distortion amplitude is too large, the problems that the signal cannot be normally received at the receiving end and the like may occur, so that the circuit function cannot be normally realized. Therefore, the relative delay between the two single-ended signals is minimized. When a PCB design engineer designs a PCB, corners inevitably occur in the routing due to the density of components and the complexity of wiring, and the existence of the corners makes the lengths of the same group of signal lines inconsistent, and phase differences occur between signals, so that the signal line pairs are usually required to be processed in equal length. However, the relative delay is too large, the signal may be distorted greatly, the integrity of the signal cannot be guaranteed, the relative delay is too small, too strict isometric control consumes a lot of energy, and due to the limitation of the PCB processing technology, too fine design is often difficult to achieve. Therefore, in practical design, the equal length only needs to be controlled in a moderate range.
According to the electromagnetic field theory, the transmission of electromagnetic waves has a direct relation with the dielectric constant in vacuum, and the electric signals are the external expression of the transmission change of the electromagnetic waves and are essentially electromagnetic waves, so the transmission speed and quality of the electric signals can be influenced by the properties of the medium and the transmission environment of the electromagnetic waves; the existing isometric principle and experience of high-speed signals are the physical constraints on the transmission environment and transmission rate, so as to meet the requirement on the signal transmission time (time sequence).
Based on the principle, the invention starts from the aspects of signal modes, the propagation environment and the medium of electromagnetic wave signals, summarizes and designs the isometric principle of PCB high-speed signals, provides a method for calculating the isometric control range of the high-speed signals based on the preset 10-degree principle, and passes simulation verification.
Fig. 1 is a schematic flow chart of an isometric control algorithm for high-speed signals according to an embodiment of the present invention. The high-speed signal equal-length control algorithm provided by the embodiment of the invention can be suitable for signal integrity design in a high-speed circuit and the condition of optimizing equal-length tolerance and equal-length control range of different signals. As shown in fig. 1, the high-speed signal equal length control algorithm includes:
and step 110, determining equal-length tolerance according to a signal transmission period and a clock period based on a preset 10-degree principle so as to meet the time sequence requirement of the system.
The signal transmission period may be expressed by a signal degree, and the signal degree experienced by the signal in one clock period is one signal transmission period, for example, the sinusoidal signal is a projection of a motion trajectory of a point on a circle around a center of the circle, and the signal makes 360 ° around one circle in one clock period, that is, the transmission period of the sinusoidal signal is 360 °. According to the fourier transform, the complex signal is formed by superposing sinusoidal signals, so that the signal has a signal transmission period. And the clock period may be determined by the operating frequency of the memory chip.
In the invention, the preset 10-degree principle is summarized according to various communication protocols of a signal transmission principle and an electronic communication principle, simulation analysis of high-speed signal PCB wiring and a large amount of practice experience verification-provided long-length principles of high-speed signals. For example, taking a data signal and a clock signal as an example, according to a protocol of a communication system, a timing requirement of clock synchronization of a signal source is based on clock verification of the clock signal and the data signal at a receiving end, and a timing problem may be caused by a mode difference caused by a relative delay between the data signal and the clock signal. The equal length tolerance calculated based on the preset 10-degree principle provided by the invention can completely ensure that the relative delay between the data signal and the clock signal is within the controllable modal difference, wherein the controllable modal difference indicates that the system time sequence requirement is met, namely, the receiving end receives the data signal with correct time sequence.
Specifically, as shown in fig. 2, based on the preset 10 ° principle, determining the equal length tolerance according to the signal transmission period and the clock period may include steps 111 and 112:
step 111, obtaining a signal period ratio according to a ratio of a preset signal period to a signal transmission period;
step 112, an equal length tolerance is obtained from the product of the ratio of the clock period to the signal period.
In the embodiment of the present invention, the predetermined signal period is a signal level corresponding to a certain time on the signal transmission period. Preferably, the preset signal period is 10 °, because the original phase difference between the two signal lines determines the mode, and if the reliability of the mode is to be ensured, it is only necessary to satisfy the phase shift between ± 1/20 wavelengths, and the requirement for equal length control of the signal can be fully satisfied by selecting the preset signal period of 10 °. In the embodiment, the ratio of the signal period to the signal transmission period is preset to obtain the corresponding signal period ratio, and further, the product of the clock period and the signal period ratio can obtain the equal-length tolerance. It can be seen that the tolerance is the time that the signal reaches 10 ° of the predetermined signal period within one clock cycle. For example, for sinusoidal signals
Figure DEST_PATH_IMAGE001
Equal length tolerance of
Figure DEST_PATH_IMAGE002
Time, sine signal
Figure DEST_PATH_IMAGE003
The elapsed time can be identified within the time according to the modal requirement of signal transmission and clock signal source synchronization, so that the high-speed signals are equally controlled within a preset signal period of 10 degrees, and the time sequence requirement of the system can be completely met.
For example, the signal transmission cycle of the embodiment may be 360 °, when the signal cycle is preset to 10 °, the operating frequency of the DDR2 system is 400MHz, that is, the clock cycle is 2500ps, at this time, the ratio of the preset signal cycle to the signal transmission cycle obtains a corresponding signal cycle ratio of 1/36, and then the product of the clock cycle and the signal cycle ratio obtains an equal length tolerance of 69ps, that is, as long as the signal length is controlled within 69ps, the timing requirement of the DDR2 system can be met.
And step 120, obtaining a control range with the same length of the high-speed signal according to the ratio of the tolerance with the same length to the signal delay rate.
Based on the scheme, according to the delay rate of the outer layer signal being 140ps/inch, the phase difference of the outer layer is 69/140=490mil, that is, the control range of the high-speed signal equal length is-490 mil to 490mil, so that when the high-speed circuit PCB is designed, the system timing requirement can be met by setting the difference between the longest signal line and the shortest signal line of each group of signal lines of the outer layer within 490 mil.
It should be noted that, according to the actual requirement of the chip register, the preset signal period may also be set to a signal degree of 15 ° or the like when the deviation is allowed, and the present invention is not limited thereto.
The high-speed signal isometric control algorithm provided by the embodiment of the invention calculates the isometric tolerance of the high-speed signal and the isometric control range of the high-speed signal based on the preset 10-degree principle, provides a design principle and algorithm with theoretical support for the isometric processing of key signals for the current high-speed circuit PCB design, is simple and practical, and can greatly improve the working efficiency of PCB design engineers while meeting the time sequence requirement of a system.
Based on the principle of presetting 10 degrees, the embodiment of the invention also provides a PCB wiring method for realizing the design of the high-speed circuit PCB. Fig. 3 is a schematic flow chart of a routing method of a PCB according to an embodiment of the present invention. As shown in fig. 3, the routing method of the PCB may include:
step 210, based on the preset 10 ° principle, determining a relative delay range of the longest signal line and the shortest signal line of each group of signal lines on the PCB for transmitting signals according to the signal transmission period and the clock period.
The signal transmission period can be represented by a signal degree, the signal degree experienced by a signal in one clock period is one signal transmission period, and the clock period can be determined by the working frequency of the memory chip.
The equal length tolerance is calculated based on the preset 10-degree principle provided by the invention, and the equal length tolerance can be used for estimating the relative delay range of the transmission signals of the longest signal line and the shortest signal line of each group of signal lines on the PCB.
Specifically, as shown in fig. 4, based on the preset 10 ° principle, determining the relative delay range of the longest signal line and the shortest signal line of each group of signal lines on the PCB for transmitting signals according to the signal transmission period and the clock period may include steps 211 and 212:
step 211, obtaining a signal period ratio according to a ratio of a preset signal period to a signal transmission period;
step 212 determines the product of the clock period and the signal period ratio as the relative delay range.
In the embodiment of the present invention, the predetermined signal period is a signal level corresponding to a certain time on the signal transmission period. Preferably, the preset signal period is 10 °, because the original phase difference between the two signal lines determines the mode, and if the reliability of the mode is to be ensured, it is only necessary to satisfy the phase shift between ± 1/20 wavelengths, and the requirement for equal length control of the signal can be fully satisfied by selecting the preset signal period of 10 °. In the embodiment, the ratio of the signal period to the signal transmission period is preset to obtain the corresponding signal period ratio, and further, the relative delay range can be obtained according to the product of the clock period and the signal period ratio. It can be seen that the relative delay range is the time that the signal reaches 10 ° of the preset signal period in one clock cycle. For example, for sinusoidal signals
Figure 937329DEST_PATH_IMAGE001
Equal length tolerance of
Figure DEST_PATH_IMAGE004
Time, sine signal
Figure 260994DEST_PATH_IMAGE003
The elapsed time can be identified according to the modal requirement of signal transmission and clock signal source synchronization, and therefore, based on the preset 10 ° principle of the embodiment, the relative delay calculated when the preset signal period is 10 ° is obtainedThe time range can completely meet the time sequence requirement of the system.
Step 220, determining the length difference range of the longest signal line and the shortest signal line according to the ratio of the relative delay range and the signal delay rate.
For example, for the DDR3 system, the operating frequency is 533MHz, i.e. the clock period is 1.876ns, based on the principle of the present embodiment of the preset 10 °, when the preset signal period is 10 ° and the signal transmission period is 360 °, the obtained signal period ratio is 1/36, the relative delay range is 1.876ns/36=52.11ps, at this time, according to the outer layer signal delay rate of 160ps/inch, the length difference between the longest signal line and the shortest signal line of the outer layer obtained according to the ratio between the relative delay range and the signal delay rate is-325 mil to 325 mil.
And step 230, setting each group of signal lines so that the length difference between the longest signal line and the shortest signal line of each group of signal lines is within the length difference range.
Alternatively, each group of signal lines includes a data signal line and a clock signal line, and the data signal line may include a single-ended signal line or a differential signal line.
For the content not described in detail in this embodiment, please refer to the foregoing embodiment, which is not described herein again.
In addition, based on the preset 10-degree principle of the invention, aiming at the design of a high-speed circuit PCB in a DDR3 system, simulation analysis and verification are carried out on signals of the PCB under the conditions of the same time and different equal lengths, wherein the clock period is 1.876ns, the signal transmission period is 360 degrees, and the signal delay rate is 160 ps/inch. Fig. 5-9 are simulation diagrams of signals with the same time and different lengths according to an embodiment of the present invention, in which the solid line curve represents the clock signal and the dotted line curve represents the data signal.
Referring to fig. 5, when the length difference between the data signal line and the clock signal line is 100 mils, the difference between the falling edges of the data signal and the clock signal at the time of 1.51ns is 60mV, and at this time, taking 100 mils as the length difference range of the above scheme, it can be deduced that the corresponding preset signal period is 3.074 °; referring to fig. 6, when the length difference between the data signal line and the clock signal line is 200 mils, the difference between the falling edges of the data signal and the clock signal at 1.51ns is 120mV, and at this time, taking 200 mils as the length difference range of the above scheme, it can be deduced that the corresponding preset signal period is 6.148 °; referring to fig. 7, when the length difference between the data signal line and the clock signal line is 300 mils, the difference between the falling edges of the data signal and the clock signal at 1.51ns is 170mV, and at this time, taking 300 mils as the length difference range of the above scheme, it can be deduced that the corresponding preset signal period is 9.211 °; referring to fig. 8, when the length difference between the data signal line and the clock signal line is 400 mils, the difference between the falling edges of the data signal and the clock signal at the time of 1.51ns is 230mV, and at this time, taking 400 mils as the length difference range of the above scheme, it can be deduced that the corresponding preset signal period is 12.28 °; referring to fig. 9, when the length difference between the data signal line and the clock signal line is 500 mils, the difference between the falling edges of the data signal and the clock signal at 1.51ns is 290mV, and at this time, taking 500 mils as the length difference range of the above scheme, it can be concluded that the corresponding predetermined signal period is 15.35 °.
In summary, when the preset signal period is 12.28 °, the PCB is wired according to the maximum value (400 mil) of the length difference range, and the deviation of the data signal with respect to the clock signal will cause a timing problem; when the preset signal period is 9.211 degrees, the PCB is wired according to the maximum value (300 mil) of the length difference range, and the deviation of the data signal relative to the clock signal is within the deviation allowable range; therefore, based on the principle of presetting 10 degrees, when the period of the preset signal is 10 degrees, the time sequence requirement of the system can be completely met.
Fig. 10 is a schematic diagram of signal transmission and reception under the preset 10 ° principle according to an embodiment of the present invention. In this embodiment, based on the principle of presetting 10 °, a high-speed circuit PCB is designed under the condition that the preset signal period is 10 °, and the transmission and reception of signals in the DDR3 system are verified, as can be seen from fig. 10, compared with signals transmitted by a transmitting end, signals received by a receiving end have a smaller distortion degree, and a better integrity is maintained, so that it can be verified that the PCB designed under the condition of presetting 10 ° signal period of the present invention can ensure the integrity of signals, and meet the timing requirement of the system.
The PCB wiring method provided by the embodiment of the invention calculates the length difference range of the longest signal line and the shortest signal line based on the preset 10-degree principle, and performs wiring according to the length difference range, provides a design principle and an algorithm with theoretical support for the equal length processing of key signals in the current high-speed circuit PCB design, is simple and practical, and can greatly improve the working efficiency of PCB design engineers while meeting the system time sequence requirement.
In addition, the embodiment of the invention also provides a PCB, which comprises at least one group of signal wires; each group of signal lines is arranged by adopting the PCB wiring method provided by the embodiment of the invention, so that the PCB design can meet the system time sequence requirement.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (6)

1. A high-speed signal equal-length control algorithm is characterized by comprising the following steps:
determining an isometric tolerance according to a signal transmission period and a clock period based on a preset 10-degree principle so as to meet the system timing requirement, wherein the isometric tolerance is obtained by obtaining a signal period ratio according to the ratio of a preset signal period to the signal transmission period and obtaining the isometric tolerance according to the product of the clock period and the signal period ratio, and the preset signal period is 10 degrees;
and obtaining the control range of the same length of the high-speed signal according to the ratio of the equal length tolerance to the signal delay rate.
2. The high-speed signal equal length control algorithm according to claim 1, wherein the signal transmission period is 360 °.
3. A wiring method of a PCB, comprising:
determining the equal length tolerance of the transmission signals of the longest signal line and the shortest signal line of each group of signal lines on the PCB according to a signal transmission period and a clock period based on a preset 10-degree principle, wherein the equal length tolerance comprises a signal period ratio obtained by the ratio of a preset signal period to the signal transmission period, and determining the product of the clock period and the signal period ratio as the equal length tolerance, wherein the preset signal period is 10 degrees;
determining the length difference range of the longest signal line and the shortest signal line according to the ratio of the equal length tolerance to the signal delay rate;
and setting each group of signal lines so that the length difference between the longest signal line and the shortest signal line of each group of signal lines is within the length difference range.
4. The routing method of a PCB of claim 3, wherein each set of signal lines comprises a data signal line and a clock signal line.
5. The routing method of a PCB of claim 4, wherein the data signal lines comprise single-ended signal lines or differential signal lines.
6. A PCB is characterized by comprising at least one group of signal lines; wherein each set of signal lines is arranged using the routing method of the PCB according to any one of claims 3 to 5.
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