CN101794729A - Method for forming through holes in semiconductor structure via etching - Google Patents
Method for forming through holes in semiconductor structure via etching Download PDFInfo
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- CN101794729A CN101794729A CN200910005645A CN200910005645A CN101794729A CN 101794729 A CN101794729 A CN 101794729A CN 200910005645 A CN200910005645 A CN 200910005645A CN 200910005645 A CN200910005645 A CN 200910005645A CN 101794729 A CN101794729 A CN 101794729A
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Abstract
The invention relates to a metal and oxide etching method, which comprises the following steps: providing a substrate, depositing a metal layer on the substrate, then depositing an oxide layer, depositing a layer of bottom anti-reflection film above the oxide, and then depositing a layer of light resistance material above the bottom anti-reflection film; etching a part of the light resistance material via exposure to obtain critical dimension; etching the oxide layer, taking the light resistance material which is not etched as a light resistance layer, and etching the exposed bottom anti-reflection layer and oxide after removing the etched light resistance material; cleaning to remove the light resistance layer and the bottom anti-reflection layer, and simultaneously taking the residue oxide layer as a barrier layer to etch the metal layer to the substrate; growing TiN on the exposed oxide layer after cleaning and the etched groove surface; etching to remove the TiN grown on the oxide layer and the groove bottom; and etching by taking the residue oxide layer and the metal layer as the barrier layers, so the critical dimension and the outline of metal etching can be controlled well in the etching process. The invention also relates to a method for forming through holes in a semiconductor structure via etching.
Description
Technical field
The present invention designs a kind of preparation process of semiconductor device, particularly relates to a kind of method that forms the through hole in the semiconductor structure by etching.
Background technology
In the preparation process of semiconductor device, along with the raising of integrated circuit integrated level, require live width more and more thinner, from .25um .18um even below .13um.Prior art goes up formation one deck bottom anti-reflective film (BARC) at substrate (Oxide) usually as shown in Figure 1, forms photoresist layer (PR) more thereon.Use PR as etched barrier layer, adopt gold-tinted that semiconductor device is carried out exposure imaging, according to the pattern that develops semiconductor is carried out etching again.Because the restriction of gold-tinted analytic ability, can only control characteristic size (the Critical Dimension of through hole (Via) by regulating etch process, CD), but because the characteristic of photoresistance itself and adjusting etch process are relatively more difficult, it is very little that the characteristic size of therefore common Via can not be done, and is difficult to reach the more and more littler requirement of Via that circuit interconnection is used in the integrated circuit.
Summary of the invention
The purpose of this invention is to provide the less method of through hole that makes in the semiconductor structure.
For achieving the above object, the invention provides a kind of method, may further comprise the steps by the through hole in the etching formation semiconductor structure:
A substrate is provided, and on this substrate, deposits the layer of metal layer, deposit one deck oxide skin(coating) again, above this oxide, deposit one deck bottom anti-reflective film again, above the bottom anti-reflective film, deposit one deck photoresistance material again;
With exposure etching part photoresistance material, obtain critical dimension earlier;
Above-mentioned oxide skin(coating) is carried out etching, and as the barrier layer, bottom layer anti-reflection layer and the oxide that exposes behind the etching part photoresistance material removed in etching with not etched part photoresistance material;
Clean and remove photoresist layer and bottom layer anti-reflection layer, with the barrier layer of residual oxide skin(coating), metal level is etched to substrate simultaneously as metal etch;
Exposed oxide layer after cleaning and the flute surfaces growth TiN that etches;
The TiN that etching removal oxide skin(coating) and channel bottom grow;
With residual oxide layer and metal level is that etching is carried out on the barrier layer.
According to the thickness of the size of required critical size decision nitride, the thickness of the nitride that forms of the time control by reaction again.
Beneficial effect of the present invention is, by regulating the thickness of clearance wall, can form the through hole of littler characteristic size, and can improve the profile of through hole.
Description of drawings
Fig. 1 is the manufacture process of known through hole.
Fig. 2 is the wafer cutaway view after the through hole manufacture process of a preferred embodiment of the present invention.
Fig. 3 is the wafer cutaway view after the exposure imaging step of a preferred embodiment of the present invention.
Fig. 4 is the wafer cutaway view behind the etching step of a preferred embodiment of the present invention.
Fig. 5 is the wafer cutaway view after the strip step of a preferred embodiment of the present invention.
Fig. 6 is the wafer cutaway view after regrowth mask step on oxide skin(coating) and the feature inwall of a preferred embodiment of the present invention.
Fig. 7 is the wafer cutaway view behind the etching step again of a preferred embodiment of the present invention.
Fig. 8 is the wafer cutaway view of finally making through hole of a preferred embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, through hole engraving method of the present invention is elaborated.
At first as shown in Figure 2, a substrate 1 is provided, and at substrate 1 surface formation layer of metal layer 2, the material of this metal level 2 for example is a titanium nitride (TiN) in the present embodiment, form oxide TEOS layer 3 on the surface of metal level 2, this oxide skin(coating) 3 is a silicon dioxide in the present embodiment, forms bottom anti-reflective film (BARC) layer 4 on the surface of oxide skin(coating) 3 again, forms photoresistance (PR) layer 5 on bottom antireflection rete 4 surfaces at last.
As shown in Figure 3, then, the live width after first gold-tinted development obtains developing, the place that will not be developed removal is as bottom anti-reflective film and oxide skin(coating) etched barrier layer; BARC layer 4 and oxide skin(coating) 3 are carried out etching, until exposing metal level 2, as shown in Figure 4.The using plasma ablution cleans and removes solvent again, and PR layer 5 and BARC layer 4 are peeled off, and in cleaning process, residual oxide layer is as the barrier layer of etch metal layers, and the metal level 2 of exposure is also formed as shown in Figure 5 until exposing substrate 1 by etch.Next adopt the CVD method layer of metal layer 6 of on TEOS layer 3 surface, trench bottom surfaces and trenched side-wall, growing, the material of this metal level is identical with metal level 2, for example all be TiN, the reason that adopts the TiN layer is because the etching selectivity height of TiN layer, sidewall contact-making surface with other materials after the etching is good, and TiN has antiradar reflectivity and good bonding characteristic, certainly, also can select other nitride, for example TaN etc.As shown in Figure 6.Wherein, according to the thickness of the size of required critical size (CD) decision TiN, the thickness of the TiN layer that forms of the time control by reaction again.Grown behind the TiN, again the TiN etching of oxide layer surface and trench bottom surfaces has been got rid of, formed as shown in Figure 7, formed one deck TiN at trenched side-wall and intercept sidewall 8, to regulate the critical size of through hole.Wherein, select different CD as required, and at different CD, the thickness of sidewall is also different.If it is 0.14 μ m that processing procedure requires CD, and the gold-tinted exposure only is 0.2 μ m, then the thickness of sidewall TiN is located 0.03 μ m, to satisfy the demand.And the engraving method that select this moment is an anisotropic etching, because horizontal surface is different with the etch-rate of sidewall, after this TEOS surface was etched with the TiN of channel bottom, trenched side-wall can form TiN and intercept sidewall 8.Finally carry out etching as etched barrier layer, and by in the present embodiment, above-mentioned oxide skin(coating) and barrier layer are silicon dioxide and TiN carries out etching as the barrier layer, obtains CD required on the processing procedure as shown in Figure 8 and profile with oxide skin(coating) and barrier layer.
That is to say that the present invention has further done improvement, step as shown in Figure 6 on the basis of existing technology: after the etching first time, carry out the growth of a TiN again, and then carry out the etching second time.Like this can be in etching process form TiN, can play the effect of protection metal sidewall at trenched side-wall, and if polymer have residually, remove the residual of polymer by the mode of removal of solvents in the successive process again.As shown in Figure 7, can well control the critical dimension and the profile of metal etch by this method.
In other embodiments, above-mentioned oxide can be other oxides outside the silicon dioxide, also can adopt said method to reach above-mentioned effect.
The above is preferred embodiment of the present invention only, is not to be used for limiting practical range of the present invention; If do not break away from the spirit and scope of the present invention, the present invention is made amendment or is equal to replacement, all should be encompassed in the middle of the protection range of claim of the present invention.
Claims (6)
1. one kind forms the method for the through hole in the semiconductor structure by etching, it is characterized in that may further comprise the steps:
A substrate is provided, and on this substrate, deposits the layer of metal layer, deposit one deck oxide skin(coating) again, above this oxide, deposit one deck bottom anti-reflective film again, above the bottom anti-reflective film, deposit one deck photoresistance material again;
With gold-tinted exposure etching part photoresistance material, obtain critical dimension earlier;
Above-mentioned oxide skin(coating) is carried out etching, and as the barrier layer, bottom anti-reflective film and the oxide that exposes behind the etching part photoresistance material removed in etching with not etched part photoresistance material;
Clean and remove photoresist layer and bottom layer anti-reflection layer, with the barrier layer of residual oxide skin(coating), metal level is etched to substrate simultaneously as metal etch;
Exposed oxide layer after cleaning and the flute surfaces growing nitride that etches;
The nitride that etching removal oxide skin(coating) and channel bottom grow keeps the nitride that trenched side-wall grows;
With residual oxide layer and metal level is that etching is carried out on the barrier layer, forms through-hole structure.
2. method according to claim 1, the nitride that it is characterized in that above-mentioned generation in etching process in order to the protection metal sidewall.
3. method according to claim 2 is characterized in that above-mentioned nitride is TiN or TaN.
4. method according to claim 3 is characterized in that above-mentioned oxide is a silicon dioxide.
5. method according to claim 1 after it is characterized in that also comprising etch metal layers, is removed the step of remaining photoresistance material.
6. method according to claim 1 is characterized in that the thickness according to the size decision nitride of required critical size, controls the thickness of the nitride that forms again by the time of reaction.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910005645 CN101794729B (en) | 2009-02-02 | 2009-02-02 | Method for forming through holes in semiconductor structure via etching |
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| CN 200910005645 CN101794729B (en) | 2009-02-02 | 2009-02-02 | Method for forming through holes in semiconductor structure via etching |
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| CN101794729A true CN101794729A (en) | 2010-08-04 |
| CN101794729B CN101794729B (en) | 2012-12-12 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863610A (en) * | 2020-05-12 | 2020-10-30 | 中国电子科技集团公司第十一研究所 | Method for preparing electrode hole and computer readable storage medium |
| TWI752253B (en) * | 2018-02-07 | 2022-01-11 | 南韓商三星電子股份有限公司 | Semiconductor device including via plug and method of forming the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6071812A (en) * | 1998-10-19 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes |
| US7098135B2 (en) * | 2003-01-14 | 2006-08-29 | Samsung Electronics Co., Ltd. | Semiconductor device including bit line formed using damascene technique and method of fabricating the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7250371B2 (en) * | 2003-08-26 | 2007-07-31 | Lam Research Corporation | Reduction of feature critical dimensions |
| KR100642886B1 (en) * | 2005-06-27 | 2006-11-03 | 주식회사 하이닉스반도체 | Method of forming a micro pattern in a semiconductor device |
| CN101295623A (en) * | 2007-04-24 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Production method of semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6071812A (en) * | 1998-10-19 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes |
| US7098135B2 (en) * | 2003-01-14 | 2006-08-29 | Samsung Electronics Co., Ltd. | Semiconductor device including bit line formed using damascene technique and method of fabricating the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI752253B (en) * | 2018-02-07 | 2022-01-11 | 南韓商三星電子股份有限公司 | Semiconductor device including via plug and method of forming the same |
| CN111863610A (en) * | 2020-05-12 | 2020-10-30 | 中国电子科技集团公司第十一研究所 | Method for preparing electrode hole and computer readable storage medium |
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| CN101794729B (en) | 2012-12-12 |
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Address after: 215123 333 Xinghua street, Suzhou Industrial Park, Jiangsu Patentee after: Warship chip manufacturing (Suzhou) Limited by Share Ltd Address before: 215025 Xinghua street, Suzhou Industrial Park, Suzhou, Jiangsu 333 Patentee before: Hejian Technology (Suzhou) Co., Ltd. |
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