CN101789386A - Method for chip alignment - Google Patents
Method for chip alignment Download PDFInfo
- Publication number
- CN101789386A CN101789386A CN200910009848A CN200910009848A CN101789386A CN 101789386 A CN101789386 A CN 101789386A CN 200910009848 A CN200910009848 A CN 200910009848A CN 200910009848 A CN200910009848 A CN 200910009848A CN 101789386 A CN101789386 A CN 101789386A
- Authority
- CN
- China
- Prior art keywords
- material layer
- alignment mark
- wafer
- exposure
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
The invention provides a method for chip alignment, which comprises: firstly, providing a chip comprising a first material layer and a second material layer, wherein the second material layer is positioned on the first material layer and the first material layer has a first alignment mark; secondly, in a lithography machine, measuring the position of the first alignment mark; thirdly, patterning the second material layer and forming a second alignment mark by using the patterned second material layer; and finally, in the aerator, measuring the offset between the second alignment mark and the first alignment mark. In the invention, the relative position error between the material layers is measured by using the alignment marks, and the measurement result is not influenced by the error between different machines as the whole measurement is performed in the same lithography machine rather than the traditional overlay tool.
Description
Technical field
The present invention relates to the wafer aligned method in a kind of semiconductor technology, particularly relate to a kind of method that increases precision of alignment.
Background technology
In semiconductor technology, pass through a lot of treatment steps, for example expose, development, etching.In these steps, in order to form the integrated circuit component of wanting, the circuit pattern between the layers of material layer on the wafer must have relative position accurately.Therefore, in the various handling procedures, all being provided with suitable mark increases alignment accuracy.
Before wafer formally carries out volume production; usually can use the test earlier of a spot of wafer earlier, utilize the alignment mark (alignment mark) that on wafer, is provided with, before exposure; with the placement location of wafer in exposure bench, utilize the alignment mark of anterior layer (pre-layer) to aim at.Anterior layer is meant the material layer of last time having handled in exposure technology, and is meant in this exposure technology the material layer of institute with processing when layer.Alignment mark normally is formed in the edge or Cutting Road of wafer, and its shape may be arranged in the material layer on the wafer for a plurality of strip groove structures.Carrying out on time, exposure bench can be with the laser detecting alignment mark, and the reflected signal that obtains from alignment mark is adjusted the position of wafer.After aligning is finished, can expose.
Behind the end exposure, wafer is sent into developing machine platform develop, after development is finished, must determine that circuit pattern has relative position accurately between each layer of material layer, otherwise the situation that the circuit pattern that follow-up formation may take place can't link up with preceding layer pattern, and then cause the problem of circuit malfunction.So, after development is finished, the wafer of test is sent in the overlay board (overlay tool), owing to all be provided with overlay marks (overlay mark) in each layer of material, mark as relative position, therefore the overlay board can utilize anterior layer and work as the overlay marks of layer, the parameter that the error of calculation is then readjusted exposure and developed.Usually overlay marks can be the groove structure that is depressed in when layer of material, or for protruding from the projective structure of anterior layer material surface.
Because above-mentioned alignment mark and overlay marks are to carry out (exposure bench and overlay board) to measure in two kinds of different boards, yet, the employed wafer carrying bench of individual other board, detector etc. itself just have error amount, if use two different boards, can make that the error amount of measuring is complicated, and can increase whole measure error.
Summary of the invention
In view of this, the invention provides a kind of wafer aligned method, it can increase precision of alignment, the error of avoiding board to produce.
According to claim of the present invention, the method for a kind of wafer aligned of the present invention comprises:
Provide wafer to comprise first material layer and second material layer, comprise first alignment mark on this first material layer, wherein this first material layer of this second layer of material covers; In exposure bench, be benchmark with this first alignment mark, and this second material layer of patterning, and form second alignment mark by this second material layer of patterning; And in this exposure bench, measure the side-play amount between this second alignment mark and this first alignment mark.
The invention is characterized in and utilize alignment mark to carry out the measurement of the relative position error between the layers of material layer, and this measurement all is to use identical exposure bench to carry out, because need not use known overlay board, so can avoid the error amount of different platform itself to influence measurement result.In addition, the present invention can replace known overlay marks fully, does not therefore need to be provided with in addition overlay marks.
Description of drawings
Fig. 1 is the wafer aligned method schematic diagram of known technology.
Fig. 2 is a wafer aligned method schematic diagram of the present invention.
Fig. 3 is the schematic cross-section of wafer by the cutting of A-A ' direction.
Fig. 4 is the schematic cross-section of wafer by the cutting of B-B ' direction.
Fig. 5 is the schematic cross-section that wafer is according to another preferred embodiment of the invention cut by B-B ' direction.
10: wafer 12: alignment mark
14: overlay marks 14 ': overlay marks
30: wafer 31,33,34: material layer
32: alignment mark 32 ': alignment mark
100: exposure bench 200: developing machine platform
300: overlay board L: spacing
Embodiment
Fig. 1 is the wafer aligned method schematic diagram of known technology.
As shown in Figure 1, wafer 10 at first is provided, there are first material layer (figure does not show), second material layer (figure does not show) and the 3rd material layer (figure does not show) to be provided with in regular turn from the bottom to top on it, first material layer and second material layer can be silicon base, conductive layer or insulating barrier, and the 3rd material layer can be photoresist.In first material layer on wafer 10, be provided with alignment mark 12 and overlay marks 14.Alignment mark 12 and overlay marks 14 can be arranged in the edge or Cutting Road of wafer for being depressed in the groove structure of first material layer.Then, wafer 10 is sent into exposure bench 100, before exposure, utilize alignment mark 12 to aim at earlier, so that wafer 10 is placed on the correct exposure position, utilize exposure light source irradiate wafer 10 then, with the circuit pattern transfer printing on the photomask on the 3rd material layer.Afterwards, wafer 10 is sent into developing machine platform 200, develop, utilize developer solution that the 3rd material layer is partly removed, after developing, have the 3rd material layer of part can form overlay marks 14 ', it is arranged at the contiguous part of overlay marks 14, and common overlay marks comprises (box-in-box) overlay marks and strip (bar-in-bar) overlay marks in the box at present.At last, wafer 10 is sent into overlay board 300,, can obtain the side-play amount between first material layer and the 3rd material layer by measuring by the spacing between the overlay marks 14 on the formed overlay marks 14 ' of the 3rd material layer and first material layer.And then side-play amount fed back to the exposure parameter control system, promptly can produce exposure parameter data required when carrying out exposure technology once more.
In photoetching process, generally first material layer is called anterior layer (pre-layer), and the alignment mark 12 on it can be described as the anterior layer alignment mark; And the material layer that present exposure bench 100 will expose, that is, the 3rd material layer then is called when layer (a current layer), and the overlay marks 14 ' on it then is called when stacked to mark.
Fig. 2 is a wafer aligned method schematic diagram of the present invention, and the element that wherein has identical function will prolong the component symbol of using Fig. 1.
As shown in Figure 2, at first provide wafer 30, shown in the schematic cross-section that the A-A ' direction of Fig. 3 is cut.As shown in Figure 3, wafer 30 is provided with material layer 31, material layer 33 and material layer 34 from the bottom to top in regular turn, and wherein, material layer 31 and material layer 33 can be silicon base, conductive layer or insulating barrier.Material layer 34 can be photoresist.In the material layer 31 on wafer 30, be provided with alignment mark 32.Alignment mark 32 can be arranged at for the groove structure that is depressed in material layer 31 in the edge or Cutting Road of wafer 30.Then, wafer 30 is sent into exposure bench 100, before exposure, utilize alignment mark 32 to be benchmark earlier, aim at, for example, adjust the wafer carrying bench position, so that wafer 30 is placed in the exposure bench 100, suitable relative exposure position utilizes exposure light source irradiates light mask then, with the circuit pattern transfer printing on the photomask on photoresist.Afterwards, wafer 30 is sent into developing machine platform 200, develop.For illustrating in greater detail the present invention, the wafer 30 after developing sees also Fig. 4 by the schematic cross-section of B-B ' direction cutting.As shown in Figure 4, utilize after the photoresist removal of developer solution with part, have the photoresist of part can form alignment mark 32 ', for example, protrude from the protrusion photoresist structure on material layer 33 surfaces, be arranged at the contiguous part of alignment mark 32.Please refer to Fig. 5, according to another preferred embodiment of the invention, formed alignment mark can also be the groove structure of depression to utilize developer solution to remove the photoresist of part afterwards, for example, to be arranged in the recessed trench structure of material layer 34, as alignment mark 32 '.Please consult Fig. 2 and Fig. 4 simultaneously, at last, once again wafer 30 is sent into exposure bench 100,, can obtain the side-play amount between material layer 31 and the material layer 34 by measuring spacing L by 32 of the alignment marks on material layer 34 formed alignment marks 32 ' and the material layer 31.And then side-play amount fed back to the exposure parameter control system, promptly can produce exposure parameter data required when carrying out exposure technology once more.And if the side-play amount between alignment mark 32 and the alignment mark 32 ' meets the requirements, can carry out etch process, utilize formerly in the step the material layer 34 of patterning to be used as mask, etched material layer 33, and the pattern transfer of alignment mark 32 ' is arrived material layer 33, with alignment mark as subsequent technique.
Be different from known technology, the present invention utilizes alignment mark to replace overlay marks, utilize exposure bench to replace the overlay board, to carry out anterior layer and the measurement of the deviation between layer, because the anterior layer alignment mark and when the layer alignment mark the position all be in same board, to measure, therefore can avoid known technology because the error of exposure bench and overlay board itself reduces accuracy of measurement.In addition, because in the known technology, existing alignment mark designs on photomask, therefore the present invention does not need additionally to make mark again, only need use original alignment mark to get final product, moreover, because exposure bench had had the function of measuring alignment mark originally, therefore need not revise hardware.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (10)
1. the method for a wafer aligned comprises:
Wafer is provided, comprises first material layer and second material layer, this first material layer comprises first alignment mark, it is characterized in that, this second material layer is positioned on this first material layer;
In exposure bench, be benchmark with this first alignment mark, this second material layer of patterning is to form second alignment mark on this second material layer; And
In this exposure bench, measure the side-play amount between this second alignment mark and this first alignment mark.
2. the method for wafer aligned as claimed in claim 1 is characterized in that, this first material layer is silicon base, conductive layer or insulating barrier.
3. as the method for the wafer aligned of claim 1 or 2, it is characterized in that this second material layer is the photoresist layer.
4. as the method for the wafer aligned of claim 1 or 2, it is characterized in that this first alignment mark is the groove structure that is depressed in this ground floor material layer.
5. the method for wafer aligned as claimed in claim 4 is characterized in that, this second alignment mark is the projective structure that protrudes from this ground floor material surface.
6. the method for wafer aligned as claimed in claim 4 is characterized in that, this second alignment mark is the groove structure that is depressed in this second layer material surface.
7. wafer aligned method as claimed in claim 1 is characterized in that, the patterning step of this second material layer comprises:
With this first alignment mark is benchmark, aims at the placement location of this wafer in this exposure bench;
In this exposure bench, carry out exposure technology, so that this second material layer is exposed; And
This second material layer is carried out developing process.
8. the method for wafer aligned as claimed in claim 1 is characterized in that, the side-play amount by between this second alignment mark and this first alignment mark resets exposure parameter.
9. the method for wafer aligned as claimed in claim 5 is characterized in that, the side-play amount by between this second alignment mark and this first alignment mark resets exposure parameter.
10. the method for wafer aligned as claimed in claim 6 is characterized in that, the side-play amount by between this second alignment mark and this first alignment mark resets exposure parameter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910009848XA CN101789386B (en) | 2009-01-24 | 2009-01-24 | Method for chip alignment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910009848XA CN101789386B (en) | 2009-01-24 | 2009-01-24 | Method for chip alignment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101789386A true CN101789386A (en) | 2010-07-28 |
| CN101789386B CN101789386B (en) | 2011-09-21 |
Family
ID=42532541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910009848XA Active CN101789386B (en) | 2009-01-24 | 2009-01-24 | Method for chip alignment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101789386B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479687A (en) * | 2010-11-22 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Method for increasing latitude of posterior layer exposure process |
| CN102522360A (en) * | 2011-12-22 | 2012-06-27 | 上海宏力半导体制造有限公司 | Lithography alignment precision detection method |
| CN102809899A (en) * | 2011-05-31 | 2012-12-05 | 无锡华润上华半导体有限公司 | Position aligning parameter calculation method |
| CN103165442A (en) * | 2011-12-12 | 2013-06-19 | 上海华虹Nec电子有限公司 | Back side graphical method |
| CN103258768A (en) * | 2012-02-15 | 2013-08-21 | 富士电机株式会社 | Target jig for calibration and semiconductor manufacturing device |
| CN107560521A (en) * | 2017-08-18 | 2018-01-09 | 武汉华星光电半导体显示技术有限公司 | A kind of stacking accuracy measurement method at high offset interface and application |
| WO2023035520A1 (en) * | 2021-09-08 | 2023-03-16 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method therefor, and memory |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW588414B (en) * | 2000-06-08 | 2004-05-21 | Toshiba Corp | Alignment method, overlap inspecting method and mask |
| CN100456142C (en) * | 2006-10-18 | 2009-01-28 | 上海微电子装备有限公司 | Alignment mark and its producing method |
| CN1963679A (en) * | 2006-11-24 | 2007-05-16 | 上海微电子装备有限公司 | Alignment mark structure for aligning wafer |
-
2009
- 2009-01-24 CN CN200910009848XA patent/CN101789386B/en active Active
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479687A (en) * | 2010-11-22 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Method for increasing latitude of posterior layer exposure process |
| CN102479687B (en) * | 2010-11-22 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Method for increasing latitude of posterior layer exposure process |
| CN102809899A (en) * | 2011-05-31 | 2012-12-05 | 无锡华润上华半导体有限公司 | Position aligning parameter calculation method |
| CN103165442A (en) * | 2011-12-12 | 2013-06-19 | 上海华虹Nec电子有限公司 | Back side graphical method |
| CN103165442B (en) * | 2011-12-12 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | Back-patterned method |
| CN102522360A (en) * | 2011-12-22 | 2012-06-27 | 上海宏力半导体制造有限公司 | Lithography alignment precision detection method |
| CN102522360B (en) * | 2011-12-22 | 2016-03-16 | 上海华虹宏力半导体制造有限公司 | Lithography alignment precision detection method |
| CN103258768A (en) * | 2012-02-15 | 2013-08-21 | 富士电机株式会社 | Target jig for calibration and semiconductor manufacturing device |
| CN103258768B (en) * | 2012-02-15 | 2016-01-13 | 富士电机株式会社 | Correction target jig and semiconductor-fabricating device |
| CN107560521A (en) * | 2017-08-18 | 2018-01-09 | 武汉华星光电半导体显示技术有限公司 | A kind of stacking accuracy measurement method at high offset interface and application |
| WO2023035520A1 (en) * | 2021-09-08 | 2023-03-16 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method therefor, and memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101789386B (en) | 2011-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8143731B2 (en) | Integrated alignment and overlay mark | |
| CN101789386B (en) | Method for chip alignment | |
| US6218200B1 (en) | Multi-layer registration control for photolithography processes | |
| CN101398630B (en) | Aligning and stacking marker, mask structure and using method thereof | |
| KR102633183B1 (en) | Alignment method of photolithography mask and corresponding process method for manufacturing integrated circuits on wafers of semiconductor material | |
| KR100519252B1 (en) | Overlay mark, method for forming overlay mark and mearsurement method for overlay | |
| KR102196670B1 (en) | Determination method, formation method, method of manufacturing article and recording medium | |
| CN114296321A (en) | Detection method of photoetching splicing error, manufacturing method of two-dimensional grating and mask plate | |
| US8174673B2 (en) | Method for wafer alignment | |
| US9134628B2 (en) | Overlay mark and application thereof | |
| US7136520B2 (en) | Method of checking alignment accuracy of patterns on stacked semiconductor layers | |
| CN117406552A (en) | Layout method and device of alignment marks | |
| US9753373B2 (en) | Lithography system and semiconductor processing process | |
| US20050244729A1 (en) | Method of measuring the overlay accuracy of a multi-exposure process | |
| KR20090099871A (en) | Alignment key of semiconductor device and method for forming of the same | |
| CN114420674A (en) | Method for measuring film layer alignment precision in LED chip manufacturing process | |
| CN105759563B (en) | Photomask and method for detecting photomask or wafer contamination | |
| JP2004031542A (en) | Method for manufacturing semiconductor device | |
| KR100349106B1 (en) | Method for measuring a pattern displacement in a photomasking process | |
| KR20040059251A (en) | Overlay mark with multiple box-type marks on one layer | |
| TWI596426B (en) | A method for detecting the error of negative film and a system thereof | |
| CN115826369A (en) | Measurement method, measurement device, and marker | |
| JP2006126695A (en) | Method for forming pattern | |
| KR100532761B1 (en) | Method for forming overlay measuring mark | |
| KR100685597B1 (en) | Measurement marks of semiconductor devices and method for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |